Method and system for testing near field communication card chip

Abstract

The invention discloses a method and a system for testing a near field communication card chip. The method comprises the following steps: encoding an original near field communication signal to generate a digital sequence; performing first expansion on the digital sequence; wherein each bit in the digital sequence is expanded into two bits, so that the bit number of the digital sequence is doubled; performing second expansion on the digital sequence after the first expansion to generate a vector which can be read by the logic testing machine; setting the frequency, the voltage and the coding mode of waveform conversion according to the rate and the amplitude of the communication signal; converting the vector into a waveform and outputting the waveform; and collecting an execution result. According to the invention, by using the basic functions of the general logic testing machine, a near field communication card chip testing scheme which is high in cost benefit and simple and convenient to operate is realized, and the dependence on a high-end machine table or a special board card is remarkably reduced.

Description

Technical Field

[0001] The invention relates to a method for testing a near field communication card chip and also to a system for implementing the method, belonging to the technical field of integrated circuit testing. Background Art

[0002] Wafer production testing of Near Field Communication (NFC) Peripheral Interface Controller Chip (PICC) faces special challenges. This is because NFC communication relies on transmitting or receiving electromagnetic waves through an air interface to achieve two-way communication, and traditional integrated circuit test equipment, such as logic testers, analog testers, or mixed signal testers, are not equipped with electromagnetic signal transceiver functions. This limitation makes it complicated to conduct effective production testing of NFC card chips.

[0003] To solve this problem, the industry has adopted two main solutions. The first solution is to integrate a dedicated NFC test board on the logic tester. The NFC test board is equipped with a near-field communication signal transceiver circuit, which can perform necessary tests on the near-field communication card chip. However, this solution is expensive because only high-end machines are equipped with this dedicated NFC test board.

[0004] The second solution is to use a low-end logic tester and design the NFC signal transceiver circuit on the test board (Load Board). Although this method can reduce costs, it increases the difficulty of designing and manufacturing the test board. Designers must consider the complexity of the NFC signal transceiver circuit and need to take measures to reduce electromagnetic interference, which limits the number of NFC card chips that can be tested simultaneously.

[0005] In summary, wafer production testing of near field communication card chips needs to find a balance between cost, test board design complexity and electromagnetic interference control. The industry urgently needs new solutions to further simplify this process. Summary of the invention

[0006] The primary technical problem to be solved by the present invention is to provide a method for testing a near field communication card chip.

[0007] Another technical problem to be solved by the present invention is to provide a system for testing a near field communication card chip.

[0008] In order to achieve the above technical objectives, the present invention adopts the following technical solutions:

[0009] According to a first aspect of an embodiment of the present invention, a method for testing a near field communication card chip is provided, comprising the following steps:

[0010] S1: Encode the original near field communication signal to generate a digital sequence;

[0011] S2: performing a first expansion on the digital sequence, wherein each bit in the digital sequence is expanded to two bits, thereby doubling the number of bits of the digital sequence;

[0012] S3: Perform a second expansion on the digital sequence after the first expansion to generate a vector that can be read by the logic tester;

[0013] S4: setting the frequency, voltage and encoding mode of waveform conversion according to the rate and amplitude of the communication signal;

[0014] S5: converting the vector into a waveform and outputting the waveform;

[0015] S6: Collect execution results.

[0016] Preferably, in step S1, the original near field communication signal is re-encoded according to Miller coding rules to generate a new digital sequence.

[0017] Preferably, in step S2, the first expansion follows the following rules:

[0018] For each bit in the digital sequence, if the previous bit is 0, then expand 0 to 00 and 1 to 01; if the previous bit is 1, then expand 0 to 10 and 1 to 11.

[0019] Preferably, each extended bit consists of two bits, wherein the first bit corresponds to the first half period of the original bit, and the second bit corresponds to the second half period of the original bit.

[0020] Preferably, in step S3, the number of bits after the second expansion is 64 bits to match the reading rate of the logic tester.

[0021] Preferably, in step S4, the set frequency, voltage and coding mode are used to simulate amplitude shift keying modulation of the near field communication signal.

[0022] Preferably, the frequency is between 13.5 MHz and 15 MHz, the voltage is between 0 and 7 V, and the coding mode is non-return-to-zero coding.

[0023] Preferably, in step S5, the logic tester uses an automatic test vector generation function to convert the vector into a waveform and output it.

[0024] Preferably, in the test circuit between the logic tester and the near field communication card chip, a filter capacitor and a DC blocking capacitor are provided at the LA terminal of the near field communication card chip, and the LB terminal is connected to the GND terminal of the logic tester.

[0025] According to a second aspect of an embodiment of the present invention, a system for testing a near field communication card chip is provided, comprising a processor and a memory; wherein the memory is coupled to the processor and is used to store a computer program, and when the computer program is executed by the processor, the processor implements the above method.

[0026] Compared with the prior art, the present invention realizes a cost-effective and easy-to-operate test solution for near-field communication card chips by using the basic functions of a general logic tester, significantly reducing the dependence on high-end machines or dedicated boards. The method improves test efficiency and reduces human errors through automated encoding and sequence expansion processes, while accurately simulating near-field communication signals to ensure the accuracy of test signals and the reliability of communication. In addition, the simplified test circuit design reduces electromagnetic interference, improves signal stability, makes the test process easy to maintain, and helps to improve mass production test speed and output. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is an example diagram of Miller encoding in an embodiment of the present invention;

[0028] Figure 2 Schematic diagram of modulation principle of near field communication signal in an embodiment of the present invention;

[0029] Figure 3 A flow chart of a method for testing a near field communication card chip provided by an embodiment of the present invention;

[0030] Figure 4 Schematic diagram of the expansion process of a near field communication signal in an embodiment of the present invention;

[0031] Figure 5 This is an example diagram of a test circuit between a logic tester and a near field communication card chip in an embodiment of the present invention;

[0032] Figure 6 A system structure diagram of a near field communication card chip test provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] First embodiment

[0035] When NFC communication is transmitting data, the generation of its communication waveform is based on the encoding and modulation process of the baseband signal. The baseband signal is first encoded, and the commonly used encoding methods are Miller encoding and Manchester encoding. Figure 1 In the Miller code shown, binary "1" is represented by any edge change within half a bit period, while binary "0" is represented by keeping the level unchanged throughout the bit period. This coding method helps to improve signal transmission efficiency and reduce transmission errors.

[0036] In the modulation process, the modulation method commonly used in NFC communication is ASK (Amplitude Shift Keying). In different application scenarios, the modulation depth will be different, but the basic principle is the same. Figure 2 As shown in Figure 1, in ASK modulation, the encoded baseband signal s(t) is used to control the amplitude of a 13.56MHz sine wave carrier. When the baseband signal is binary "1", the amplitude of the carrier is fully modulated to produce a complete sine wave; when the baseband signal is binary "0", the amplitude of the carrier is reduced to zero, thus producing a signal with zero amplitude. This modulation method allows the signal to represent binary data at different amplitude levels.

[0037] In an embodiment of the present invention, a general logic tester is used to implement the encoding and modulation process of the NFC communication waveform. By simulating the above encoding and modulation process, the logic tester can generate a waveform that meets the NFC communication standard. This method can not only ensure the accuracy of the waveform, but also flexibly adjust parameters in different test environments to meet different test requirements.

[0038] like Figure 3 As shown, the first embodiment of the present invention provides a method for testing a near field communication card chip. The method includes at least the following steps:

[0039] S1: Encode the original near field communication signal to generate a digital sequence;

[0040] S2: performing a first expansion on the digital sequence, wherein each bit in the digital sequence is expanded to two bits, thereby doubling the number of bits of the digital sequence;

[0041] S3: Perform a second expansion on the digital sequence after the first expansion to generate a vector that can be read by the logic tester;

[0042] S4: setting the frequency, voltage and encoding mode of waveform conversion according to the rate and amplitude of the communication signal;

[0043] S5: converting the vector into a waveform and outputting the waveform;

[0044] S6: Collect execution results.

[0045] like Figure 4 As shown, in one embodiment of the present invention, in step S1, the original near-field communication signal is first encoded to generate a digital sequence. Specifically, the original near-field communication signal needs to undergo a specific encoding process to generate a baseband signal suitable for transmission by a logic tester. This process follows the Miller coding rule, that is, binary "1" is represented by any edge change within half a bit period, and binary "0" is represented by a constant level in the entire bit period. For example, the original command "10110" will be converted to "11011" after being encoded according to the Miller coding rule. This regenerated digital sequence will be used as the input of the logic tester to simulate the actual NFC communication environment. When the NFC chip receives this Miller-encoded baseband signal, it will perform a decoding operation to parse the signal back to the original near-field communication signal to ensure the accuracy and effectiveness of the communication. The encoding process can be automated through scripts or programs to improve efficiency and reduce human errors.

[0046] Miller coding is a widely used coding method in digital communications. Its characteristic is that the transmission time of each bit is divided into two equal parts. Each part can be high, low or unchanged, but the two parts of each bit are in opposite states to represent binary information. The advantage of this coding method is that it can provide a synchronization signal because there is a jump in the middle of each bit, which helps the receiving end to determine the boundary of the bit. In addition, since each bit contains at least one jump, long periods of silence can be detected, which helps error detection. Miller coding is widely used in various communication systems, such as near field communication (NFC), wireless radio frequency identification (RFID) and other digital communication systems that require synchronization and error detection.

[0047] Next, the generated digital sequence is expanded for the first time to ensure that the logic tester can read the vector file more accurately and generate the corresponding waveform. Specifically, in step S2, each bit in the digital sequence is expanded according to the value of its previous bit. If the previous bit is 0, the Miller-encoded 0 is expanded to 00, and the Miller-encoded 1 is expanded to 01; if the previous bit is 1, the Miller-encoded 0 is expanded to 10, and the Miller-encoded 1 is expanded to 11. This expansion rule allows each bit to be decomposed into two sub-bits, corresponding to the first half cycle and the second half cycle of each bit after encoding, thereby doubling the number of bits in the entire digital sequence.

[0048] The first expansion enables more accurate simulation and control of waveform generation. In Miller coding rules, the representation of binary "1" relies on level transitions within half a bit period, while binary "0" is represented by keeping the level unchanged. Expanding each bit to two bits helps the logic tester to more accurately reproduce every detail of the signal when simulating near-field communication signals, thereby improving the accuracy of the test and the reliability of communication. This approach not only enhances the readability of the signal, but is also of great significance for improving the performance of the logic tester in simulating actual NFC communication environments.

[0049] Next, since the general logic tester lacks modulation function, the present invention converts the digital sequence into a vector format that can be read by the logic tester through two expansions. Specifically, in step S3, the digital sequence that has undergone the first expansion is expanded for the second time. The purpose of this step is to generate a vector that can be recognized and read by the logic tester, so as to flexibly set it using the automatic test vector generation (ATPG) function of the logic tester to achieve simulation and debugging of the near field communication signal.

[0050] In the second expansion, each bit is expanded again according to the communication rate, but its value remains unchanged. The number of bits after expansion is converted according to the communication rate to ensure consistency with the actual communication environment. For example, in order to ensure that the vector can be correctly read by the logic tester, the number of bits after the second expansion is preferably 64 bits. This expansion is to ensure that the vector file can match the reading rate of the logic tester, thereby accurately simulating the near-field communication signal. After the second expansion, the generated digital sequence becomes a vector file that can be read by the tester. This process can be automated through scripts or programs to improve efficiency and accuracy.

[0051] Taking the command "10110" as an example, the command is first Miller encoded, and then expanded twice, and the final vector file sequence is: 0...01...11...11...11...10...00...01...11...1. In this sequence, each ellipsis "..." represents 62 bits, which means that each original bit is expanded to 64 bits after the second expansion, thus forming a complete vector file for the logic tester to read and use for NFC signal simulation and testing. This method effectively solves the limitations of the logic tester in simulating NFC signals and improves the accuracy of the test and the reliability of communication.

[0052] In step S4, the parameters of waveform conversion, including frequency, voltage and coding mode, are set according to the rate and amplitude of the communication signal to simulate the amplitude keying modulation of the near field communication signal. In a preferred embodiment of the present invention, the logic tester converts the encoded and extended digital sequence into a corresponding waveform and outputs it through its automatic test vector generation (ATPG) function. In order to simulate the near field communication signal, the frequency range of the communication signal is preferably set between 13.5MHz and 15MHz, wherein the high level is set to 7V and the low level is set to 0V. In terms of coding mode, non-return-to-zero coding (NRZ) is preferably used. In this coding method, the level remains unchanged in each bit period to represent binary "1", and when the level changes, it represents binary "0", thereby simplifying the generation and processing of near field communication signals.

[0053] In one embodiment of the present invention, taking the S50 test platform of YTEC Company as an example, it is necessary to pre-set the TIMING (timing) conditions and voltage conditions of the waveform when performing waveform conversion. Specifically, the vector frequency is set to 14MHz, which is represented by using two lines of vectors with a period of 35 nanoseconds (NS). According to the specific requirements of the product, the frequency can be adjusted between 13.5MHz and 15MHz. In the coding mode setting of the signal P IN, NRZ coding is selected to ensure the accuracy of the waveform and the stability of the communication signal. Through these precise settings, the logic tester can accurately simulate the near field communication signal, providing an effective technical means for the testing and verification of NFC chips.

[0054] It should be noted that Non-Return-to-Zero (NRZ) is a digital signal encoding method in which the "1" and "0" of binary data are represented by different voltage or current levels, and the signal does not return to zero voltage or zero current level within a bit period. In NRZ encoding, a high level usually represents a binary "1" and a low level represents a binary "0".

[0055] There are two forms of NRZ encoding:

[0056] NRZ-Level: In this form, binary "1" is represented by a high level, binary "0" is represented by a low level, and the level remains unchanged throughout the bit period. This is the simplest form of NRZ encoding.

[0057] NRZ-Inverted (or NRZI): In this form, a binary "1" is represented by a level transition, either from high to low or from low to high, while a binary "0" is represented by a level remaining unchanged. This encoding method helps provide clock synchronization because each "1" generates a transition.

[0058] In step S5, the vector is converted into a waveform and output. The logic tester uses its automatic test vector generation (ATPG) function to convert the vector into a waveform and output it. In this way, the logic tester can send an execution command to the near field communication peripheral interface controller chip.

[0059] Below, a command example for the Automatic Test Pattern Generation (ATPG) feature is shown:

[0060] @@AC_SET_7

[0061] [NAME=T7]

[0062] [TS]

[0063] PERIOD = 35NS;

[0064] TEST_PINS:{DRV_RS=0}

[0065] {DRV_FL=5}

[0066] {STB_RS=NULL}

[0067] [END_TS]

[0068] [FMT]

[0069] TEST_PINS:{DRV_FMT=NRZ}

[0070] [END_FMT]

[0071] @@END_AC_SET_7

[0072] Set the voltage condition for waveform conversion. The high level is set to 7V and the low level is set to 0V. It can be adjusted according to different products.

[0073] LOGIC_SET_DRV_LEVEL(TEST_P INS,7V,0V,0V,VR1)

[0074] It should be noted that the existing logic tester is mainly used to perform logic function testing, and does not originally have the ability to convert digital signals into analog signals suitable for wireless communication. However, the present invention generates vectors that can be read by the logic tester by expanding the digital sequence twice, and realizes the modulation function of the near field communication signal by flexibly setting the automatic test vector generation (ATPG) function.

[0075] Finally, in step S6, the execution results are collected to verify the performance and reliability of the near field communication card chip.

[0076] Figure 5The test circuit between the logic tester and the near-field communication card chip in an embodiment of the present invention is shown. In this test configuration, after the automatic test vector generation (ATPG) function is set, the logic tester will output a square wave signal according to the digital sequence in the vector. In order to ensure that these output waveforms can simulate the waveforms in actual use, it is necessary to add filter capacitors and DC blocking capacitors to the LA end of the near-field communication card chip to optimize the signal quality. At the same time, the LB end should be grounded, but it should be noted that the grounding point here is the GND end of the logic tester, not the GND end of the near-field communication card chip. This design helps to avoid ground loop problems and ensure that the reference point of the test signal is the ground of the logic tester, thereby improving the accuracy of the test.

[0077] In the above connection mode, the LA end is the key pin on the NFC card chip, responsible for receiving the test vectors from the logic tester. These vectors are signals used to verify and test the functions of the NFC card chip, which is crucial to ensure the performance of the NFC card chip. The grounding design of the LB end avoids directly grounding the GND end of the NFC card chip, which can reduce ground loop interference and ensure the stability and accuracy of the test signal.

[0078] like Figure 5 As shown, capacitors C13 and C14 are 100nF each, which play a role of filtering and decoupling in the circuit, helping to reduce noise and stabilize the power supply. These capacitors ensure signal stability and reduce external interference during the test process. Resistors R41 and R42 are used to limit current, divide voltage or act as current detection elements. They ensure signal stability in logic testing and protect the circuit from excessive voltage, thereby ensuring the safety and effectiveness of the test process.

[0079] Compared with the prior art, the test circuit design in the embodiment of the present invention is more simplified, which not only improves the efficiency of the test, but also enhances the feasibility of mass production testing. The simplified circuit design reduces the number of components and the complexity of the connection, making the test process more direct and economical, which is particularly important for near field communication card chip testing in a large-scale production environment.

[0080] In the test scheme provided by the present invention, the test of the near field communication card chip is successfully realized through the coordinated work of the carefully designed test program and the test circuit. Taking the sending of the "SELECT" command as an example, an oscilloscope is used to collect waveforms at the antenna pin of the near field communication card chip during the test process to verify the command signal transmitted by the logic tester. When the near field communication card chip receives the "SELECT" command, it will execute the command and feedback the result of the command execution to the logic tester through the IO state or other communication interface. For example, when testing the "RATS" command, if the level of the CH2 channel is reversed, this means that the near field communication card chip has successfully executed the "RATS" command on the CH1 channel. The logic tester determines whether the near field communication card chip has passed the test of the command by monitoring the level flip of the CH2 channel, thereby ensuring the accuracy and reliability of the test process. Through this method, the near field communication card chip can be effectively tested to ensure its performance and stability in practical applications.

[0081] Second embodiment

[0082] Based on the above method, a second embodiment of the present invention provides a system for testing a near field communication card chip.

[0083] like Figure 6 As shown, the system includes one or more processors 61 and a memory 62. The memory 62 is coupled to the processor 61 and is used to store one or more programs. When the one or more programs are executed by the one or more processors 61, the one or more processors 61 implement the test method of the near field communication card chip in the above embodiment.

[0084] Wherein, the processor is used to control the overall operation of the system to complete all or part of the steps of the above method. The processor can be a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processing (DSP) chip, etc. The memory is used to store various types of data to support operations in the system, and these data may include, for example, instructions for any application or method for operating on the system, and application-related data. The memory can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, etc.

[0085] In an exemplary embodiment, the system can be implemented by a computer chip or entity, or by a product with a certain function, for executing the above method and achieving the same technical effect as the above method. Specifically, the computer can be, for example, a personal computer, a laptop computer, a vehicle-mounted human-computer interaction device, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0086] In another exemplary embodiment, the present invention further provides a computer-readable storage medium including program instructions, which, when executed by a processor, implements the steps of the method in any of the above embodiments. For example, the computer-readable storage medium may be the above-mentioned memory including program instructions, which may be executed by a processor to complete the above-mentioned method and achieve the same technical effect as the above-mentioned method.

[0087] It should be noted that the above embodiments are only examples, and the technical solutions of the various embodiments can be combined, all within the protection scope of the present invention.

[0088] The method and system for testing the near field communication card chip provided by the present invention are described in detail above. For those skilled in the art, any obvious changes made to it without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims

1. A method for testing a near field communication card chip, characterized in that The steps include: S1: Encode the original near field communication signal to generate a digital sequence; S2: Performing a first expansion on the digital sequence, wherein each bit in the digital sequence is expanded to two bits, thereby doubling the number of bits of the digital sequence; S3: Perform a second expansion on the digital sequence after the first expansion to generate a vector that can be read by the logic tester; S4: setting the frequency, voltage and encoding mode of waveform conversion according to the rate and amplitude of the communication signal; S5: converting the vector into a waveform and outputting the waveform; S6: Collect execution results.

2. The method according to claim 1, characterized in that In the step S1, the original near field communication signal is re-encoded according to the Miller coding rule to generate a new digital sequence.

3. The method according to claim 1, characterized in that In step S2, the first expansion follows the following rules: For each bit in the digital sequence, if the previous bit is 0, then expand 0 to 00 and 1 to 01; if the previous bit is 1, then expand 0 to 10 and 1 to 11.

4. The method according to claim 3, characterized in that Each extended bit consists of two bits, where the first bit corresponds to the first half period of the original bit, and the second bit corresponds to the second half period of the original bit.

5. The method according to claim 1, characterized in that In step S3, the number of bits after the second expansion is 64 bits to match the reading rate of the logic tester.

6. The method according to claim 1, characterized in that In the step S4, the set frequency, voltage and coding mode are used to simulate the amplitude shift keying modulation of the near field communication signal.

7. The method according to claim 6, characterized in that: The frequency is between 13.5 MHz and 15 MHz, the voltage is between 0 and 7 V, and the encoding mode is non-return-to-zero encoding.

8. The method according to claim 1, characterized in that In step S5, the logic tester uses the automatic test vector generation function to convert the vector into a waveform and output it.

9. The method according to claim 1, characterized in that In the test circuit between the logic tester and the near field communication card chip, the LA terminal of the near field communication card chip is provided with a filter capacitor and a DC blocking capacitor, and the LB terminal is connected to the GND terminal of the logic tester.

10. A system for testing a near field communication card chip, characterized in that It comprises a processor and a memory; wherein the memory is coupled to the processor and is used to store a computer program, and when the computer program is executed by the processor, the processor implements the method described in any one of claims 1 to 9.

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