DRAM (Dynamic Random Access Memory) chip capable of preventing hammer attack, test system and test method

Abstract

The invention discloses a DRAM (Dynamic Random Access Memory) chip capable of preventing a running hammer attack, a test system and a test method, and relates to the technical field of chip security, the DRAM chip is internally provided with one or more DRAM DIE chips, the DRAM chip reads data into a line buffer according to a received access signal, and the DRAM chip comprises a storage chip, a memory chip, a data storage module and a data storage module, the maximum allowable access frequency value stored in each DRAM DIE chip and the corresponding control address are sent; the attack detection control chip forwards a received access signal sent by the outside to the DRAM DIE chip, and sends a refresh signal to refresh a victim row when detecting that the victim row exists in a certain DRAM DIE chip according to the victim detection mode, or sends a refresh signal to refresh the victim row when detecting that the victim row cannot be refreshed, or sends a refresh signal to refresh the victim row when detecting that the victim row cannot be refreshed. And controlling the frequency of an access signal sent to the chip according to the received highest allowable access frequency and the corresponding control address. Therefore, the access frequency is reduced by refreshing or aiming at different self-adaptations, so that the working efficiency of the chip is improved while the chip is prevented from being attacked by a hammer.

Description

Technical Field

[0001] The present application relates to the field of chip security technology, and in particular to a DRAM chip, a test system and a test method for preventing hammer attacks. Background Art

[0002] The emergence of Rowhammer is an unexpected result of the way DRAM is manufactured. The state of the battery cell is determined by the charge on the capacitor, and the charge is easily affected between refresh cycles. Drifting electrons can migrate to the battery, thereby changing the charge in the battery. If it is done too many times, enough charge may accumulate to change the perceived state of the battery, resulting in Rowhammer in the DRAM chip. In the prior art, R&D personnel often use error correction code (ECC) to correct errors caused by rowhammer or increase the refresh rate of all memory to prevent the emergence of Rowhammer in DRAM chips, which undoubtedly increases the complexity of the system from the software level and sacrifices performance to a certain extent. However, these methods cannot completely eliminate the risk of Rowhammer attacks because they do not directly address the physical defects inside the DRAM chip. Therefore, the present invention proposes a new test method to identify and prevent potential Rowhammer problems by directly running the DRAM chip in rowhammer attack detection mode, thereby improving the security and stability of DRAM chips. Summary of the invention

[0003] The main purpose of this application is to provide a DRAM chip that is resistant to Rowhammer attacks, aiming to solve the technical problem that DRAM chips are susceptible to Rowhammer attacks.

[0004] To achieve the above object, the present application proposes a DRAM chip that is resistant to row hammer attacks. The DRAM chip is provided with one or more DRAM DIE chips. The DRAM DIE chip is used to read data into a row buffer according to a received access signal, so as to wait for a read and write operation. The chip includes: A storage chip, used for storing and sending the maximum allowed access frequency value of each DRAM DIE chip and the corresponding control address; An attack detection control chip, wherein a hammer attack detection mode is provided in the attack detection control chip, the attack detection control chip is electrically connected to each of the DRAM DIE chips, and the attack detection control chip is electrically connected to the storage chip, wherein: The attack detection control chip is used to forward the access signal sent from the outside to the DRAM DIE chip. The attack detection control chip is also used to send a refresh signal to refresh the victim row when it is detected that there is a row hammer attack victim row in a certain DRAM DIE chip according to the row hammer attack detection mode, or when it is detected that the victim row in a certain DRAM DIE chip cannot be refreshed, the frequency of the access signal sent to the DRAM DIE chip is controlled according to the maximum allowed access frequency and corresponding control address of the DRAM DIE chip of the receiving storage chip.

[0005] In one embodiment, the attack detection control chip is configured as a C4 chip.

[0006] In one embodiment, the storage chip is configured as an I2C chip.

[0007] In addition, to achieve the above purpose, the present application also proposes a DRAM chip testing system, which is used to test and adjust the maximum allowed access frequency value data of each DRAMDIE chip of the storage chip in the DRAM chip that is anti-hammer attack as described above, and the testing system includes: A testing device, wherein a row hammer test mode is provided in the testing device, and the testing device is electrically connected to the attack detection control chip. The testing device is used to test and record the maximum allowed access frequency value data and the corresponding control address of each DRAM DIE chip in the DRAM chip through the row hammer test mode, and then enter the storage chip through the attack detection control chip.

[0008] In addition, to achieve the above purpose, the present application also proposes a DRAM chip testing method, the DRAM chip testing method for preventing hammer attacks is based on the DRAM chip testing system described above, the DRAM chip includes multiple DRAMDIE chips, a storage chip and an attack detection control chip, the DRAM chip is tested by a testing device, a hammer test mode is set in the testing device, and the method further includes: Get the test signal; Running the hammer test mode according to the test signal to test each of the DRAM DIE chips, and then recording the highest allowed access frequency and the corresponding control address of each of the DRAM DIE chips when a bit flip occurs; According to the recorded highest allowed access frequency and the corresponding control address, they are entered into the storage chip according to the preset entry rules.

[0009] In one embodiment, the row hammer test mode is provided with an initial access frequency value for the frequency of the initial test access to the DRAM DIE chip, and an access frequency step value for adjusting the frequency of the test access to the DRAM DIE chip. The step of running the row hammer test mode according to the test instruction to test each of the DRAM DIE chips and recording the highest allowed access frequency and the corresponding control address when the bit flip occurs in each of the DRAM DIE chips comprises: Accessing each of the DRAM DIE chips according to the initial access frequency value; If a bit flip state occurs when testing according to the initial access frequency value, the maximum allowed access frequency is recorded as 0 and the corresponding control address; If no bit flipping occurs when testing according to the initial access frequency value, the access frequency is adjusted in sequence according to the access frequency step value to calculate and generate the highest allowed access frequency and its corresponding control address and then record them.

[0010] In one embodiment, the step of recording the recorded highest allowed access frequency and the corresponding control address into the storage chip according to a preset recording rule further includes: If the highest allowed access frequency recorded by a certain DRAM DIE chip is 0, a prompt signal is generated according to the corresponding control address to prompt the user to replace it; If the highest allowed access frequency recorded in the DRAM DIE chip is not 0, the highest allowed access frequency and the corresponding control address are recorded and recorded in the storage chip.

[0011] In one embodiment, before the step of acquiring the test signal, the step further includes: Querying the storage mode of the storage chip to distinguish whether the storage chip is in OTP mode or NORFLASH mode; When the memory chip is in OTP mode, the read data of the memory chip is obtained, and compared with the preset test data to check whether the memory chip can be recorded; When the memory chip is in the NORFLASH mode, after the inspection data is written to the memory chip, the written data of the memory chip is read to see whether it is the preset inspection data, so as to check whether the memory chip can be recorded.

[0012] In one embodiment, the step of recording the highest allowed access frequency and the corresponding control address recorded in the storage chip includes: Get the startup command; Controlling the DRAM chip to run the row hammer attack detection mode according to the startup instruction, and running the row hammer test mode again, accessing each DRAM DIE chip according to the highest allowed access frequency and the corresponding control address; After the verification data is written into each of the DRAM DIE chips, the written data of the memory chip is read to determine whether it is the preset verification data.

[0013] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the DRAM chip testing method described above are implemented.

[0014] One or more technical solutions proposed in the present application have at least the following technical effects: a DRAM chip that prevents row hammer attacks, wherein one or more DRAM DIE chips are arranged in the DRAM chip, and the DRAM DIE chip is used to read data into a row buffer according to a received access signal, so as to wait for a read and write operation, and the chip comprises: a storage chip, which is used to send the maximum allowed access frequency value and the corresponding control address of each DRAM DIE chip; an attack detection control chip, wherein a row hammer attack detection mode is arranged in the attack detection control chip, the attack detection control chip is electrically connected to each of the DRAM DIE chips, and the attack detection control chip is electrically connected to the storage chip, wherein the attack detection control chip is used to forward the access signal received from the outside to the DRAM DIE chip, and the attack detection control chip is also used to send a refresh signal to refresh the victim row when it is detected that a row hammer attack victim row exists in a certain DRAM DIE chip according to the row hammer attack detection mode, or when it is detected that a victim row in a certain DRAM DIE chip cannot be refreshed, according to the DRAM DIE chip receiving the attack detection mode of the storage chip, The maximum allowed access frequency and corresponding control address under the DIE chip are used to control the frequency of the access signal sent to the DRAM DIE chip. In this way, when the DRAM chip detects a Rowhammer attack through the rowhammer attack detection mode, it can reduce the access frequency by refreshing or adaptively targeting different DRAM DIE chips to protect the DRAM chip from the Rowhammer attack, thereby protecting the DRAM chip from the hardware level and maximizing the efficiency of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the description, are used to explain the principles of the present application.

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0017] Figure 1 A specific structural block diagram of the DRAM chip embodiment 1 for preventing hammer attacks in this application; Figure 2 A system schematic block diagram provided in an embodiment of a DRAM chip testing system of the present application; Figure 3 A brief flowchart of an embodiment of a DRAM testing method provided by the present application; Figure 4 A brief flowchart of another embodiment of the DRAM testing method provided by the present application; Figure 5 A brief flowchart of another embodiment of the DRAM testing method provided by the present application; Figure 6 A schematic diagram of a simplified flow chart of another embodiment of the DRAM testing method provided by the present application; Figure 7 A schematic diagram of a simplified flow chart of yet another embodiment of the DRAM testing method provided by the present application; Label: 1-DRAM chip; 11-attack detection control chip; 12-storage chip; 13-DRAM DIE chip; 2-test device.

[0018] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0019] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0020] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0021] There are roughly six mainstream technical solutions in the existing technology: 1. Make better DRAM chips that are less prone to damage; Disadvantages: This can be fundamentally solved from the wafer fab production process, but the cost is very high.

[0022] 2. Use (strong) error correction code (ECC) to correct errors caused by row hammer; Disadvantage: Need to increase ECC particles, the cost is higher.

[0023] 3. Increase the refresh rate of all memory; Disadvantages: Memory needs to be redesigned, which is very costly.

[0024] 4. Statically remap / retire units prone to line hammering through a post-manufacturing analysis; Disadvantages: adds significant system complexity from the hardware level and is costly.

[0025] 5. Dynamically remap / exit units that are prone to hammering during system operation; Disadvantages: It adds significant system complexity and high cost from the software level, and does not have system-level versatility.

[0026] 6. Accurately identify hammered rows and refresh their neighbors at runtime; TRR (Target Row Refresh) technology is defined in the JEDEC standard, and TRR describes a set of methods; Disadvantages: DRAM vendors and controller vendors keep TRR confidential, and many of the methods in TRR do not work.

[0027] The present application provides a solution that enables the DRAM chip to reduce the access frequency by refreshing or adaptively reducing the access frequency for different DRAM DIE chips, so as to protect the DRAM chip from Rowhammer attacks, thereby protecting the DRAM chip from the hardware level and maximizing the working efficiency of the chip.

[0028] Therefore, in the embodiment of the present application, a DRAM chip is provided to prevent row hammer attacks. One or more DRAM DIE chips 13 are arranged in the DRAM chip. The DRAM DIE chip 13 is used to read data into the row buffer according to the received access signal to wait for the read and write operations. The chip includes: The storage chip 12 is used to store the highest allowed access frequency value of each DRAM DIE chip 13 and the corresponding control address for transmission; The attack detection control chip 11 has a hammer attack detection mode, the attack detection control chip 11 is electrically connected to each DRAM DIE chip 13, and the attack detection control chip 11 is electrically connected to the storage chip 12, wherein: The attack detection control chip 11 is used to forward the access signal sent from the outside to the DRAM DIE chip 13. The attack detection control chip 11 is also used to send a refresh signal to refresh the victim row when it is detected that there is a row hammer attack victim row in a certain DRAM DIE chip 13 according to the row hammer attack detection mode, or when it is detected that the victim row in a certain DRAM DIE chip 13 cannot be refreshed, according to the maximum allowed access frequency and corresponding control address of the DRAM DIE chip 13 of the receiving storage chip 12, to control the frequency of the access signal sent to the DRAM DIE chip 13.

[0029] In this embodiment, the DRAM chip is formed by sealing a memory chip 12, an attack detection control chip 11 and a plurality of DRAMDIE chips 13 in a package. The plurality of DRAM DIE chips 13, the memory chip 12 and the attack detection control chip 11 are all bare crystal chips to achieve efficient communication within the DRAM chip. A plurality of pins are provided on the top of the package for connecting the attack detection control chip 11 to an external circuit. The memory chip 12 can be set to an OTP type or a norflash type memory chip 12. If an OTP type (one-time programming) memory chip 12 is used for sealing, the factory hardware cost of the DRAM chip can be effectively reduced. If a norflash type (a non-volatile flash memory chip that can be repeatedly erased and programmed) memory chip 12 is used for sealing, the flexibility and repeatability of testing and configuring the DRAM chip can be effectively improved.

[0030] Specifically, the attack detection control chip 11 is used to receive the access signal sent by the outside world and forward it to the DRAM DIE chip 13. According to the row hammer attack detection mode in the attack detection control chip 11, a counter variable can be created to record the access frequency, and a timestamp variable can be created to record the last access time to record the access frequency of the same row line. When the access frequency under the corresponding control address within a certain period of time exceeds a preset threshold or the highest allowed access frequency under the DRAM DIE chip 13, it is determined that a rowhammer victim row behavior has occurred. At the same time, the attack detection control chip 11 sends a refresh signal to refresh the victim row in the DRAM DIE. When it is detected that a victim row in a certain DRAM DIE chip 13 cannot be refreshed through a column remapping mechanism or an ECC mechanism, the attack detection control chip 11 controls the access frequency of the external access device or controls the access frequency forwarded by itself according to the highest allowed access frequency and the corresponding control address of the DRAM DIE chip 13 received from the storage chip 12. The frequency of the access signal of the DIE chip 13 can protect the DRAM chip from a hardware level and can maximize the working efficiency of the chip.

[0031] Furthermore, the attack detection control chip 11 is set as a C4 chip.

[0032] In this embodiment, the attack detection control chip 11 (C4 chip) realizes real-time monitoring and protection of the DRAM DIE chip 13 by directly connecting to the DRAM DIE chip 13. As the attack detection control chip 11, the C4 chip integrates advanced detection algorithms, which can quickly identify and respond to potential hammer attacks. In addition, the C4 chip also has a self-diagnosis function, which can regularly check its own status to ensure that no failure or misjudgment occurs during the detection process. Through this design, the C4 chip not only improves the security of the DRAM DIE chip 13, but also optimizes the overall performance of the system and ensures the integrity and reliability of the data.

[0033] Furthermore, the storage chip 12 is configured as an I2C chip.

[0034] In this embodiment, the storage chip 12 is connected to the attack detection control chip 11 (C4 chip) through the I2C bus, which realizes the rapid transmission of data and the efficient execution of instructions. The I2C chip, as a storage medium, stores detailed information about the DRAM DIE chip 13, including but not limited to key data such as access frequency limit, error log, and diagnosis results. Through this connection method, the C4 chip can obtain the status information of the DRAM DIE chip 13 in real time, and adjust its protection strategy based on this information to deal with different security threats.

[0035] Based on this, the embodiment of the present application also provides a DRAM chip testing system, referring to Figure 2 The DRAM chip test system is used to test and adjust the maximum allowed access frequency value data of each DRAM DIE chip 13 of the storage chip 12 in the DRAM chip that is protected from the hammer attack as described above. The specific structure of the DRAM chip refers to the above embodiment. Since the DRAM chip test system adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here. Among them, the test system includes: The test device 2 is provided with a row hammer test mode. The test device 2 is electrically connected to the attack detection control chip 11. The test device 2 is used to test and record the maximum allowed access frequency value data and the corresponding control address of each DRAM DIE chip 13 in the DRAM chip through the row hammer test mode, and then enter the storage chip 12 through the attack detection control chip 11.

[0036] In this embodiment, the test device 2 can be implemented by an FT repair machine, and a main controller is arranged on the FT repair machine. The main controller can be implemented by, for example, an MCU (Microcontroller Unit), a DSP (Digital Signal Process), an FPGA (Field Programmable Gate Array), or a SOC (System On Chip). The main controller sends specific commands and data to perform a series of test operations such as writing, reading, and accessing on the unpackaged DRAM chip, and then records the results of testing each DRAM DIE chip 13 in the DRAM chip into a test log for entry into the storage chip 12 by the attack detection control chip 11.

[0037] Based on this, the present application embodiment also provides a DRAM chip testing method, referring to Figure 3 The DRAM chip testing method is based on the above-mentioned DRAM chip testing system. The DRAM chip includes a plurality of DRAM DIE chips 13, a storage chip 12 and an attack detection control chip 11. The DRAM chip is tested by a testing device 2. The testing device 2 is provided with a hammer test mode. The method further includes: Step S100, obtaining a test signal; Step S200, running a hammer test mode according to the test signal to test each DRAM DIE chip 13, and recording the highest allowed access frequency and corresponding control address of each DRAM DIE chip 13 when a bit flip occurs; Step S300 , recording the highest allowed access frequency and the corresponding control address into the storage chip 12 according to the preset recording rules.

[0038] In one embodiment, after obtaining a test signal triggered by a user to start the test device 2 to run a row hammer test mode, the row can be "hammered" by alternately reading two addresses, and then verifying whether the content of other addresses has interference errors, thereby detecting bit flipping, or directly accessing the physical pins of the DRAM chip, and using an oscilloscope or other tool to measure voltage changes and charge leakage, etc., to check whether the DRAM DIR chip has bit flipping behavior, and based on this, the maximum allowed access frequency and the corresponding control address of each DRAM DIE chip 13 when a bit flip occurs are recorded in the test log in the test device 2. The test device 2 retrieves the relevant recorded maximum allowed access frequency and corresponding control address data, and enters them into the storage chip 12 according to the preset entry rules, so that after the DRAM chip is sealed, each DRAM DIE chip 13 can work with higher performance while preventing bit flipping.

[0039] In this embodiment, after running the hammer test mode according to the test instruction to test each DRAM DIE chip 13, the step of recording the highest allowed access frequency when the bit flip occurs in each DRAM DIE chip 13 also includes: Steps S210 to S230: Step S210, accessing each DRAM DIE chip 13 according to the initial access frequency value; Step S220, if a bit flip state occurs when testing according to the initial access frequency value, the highest allowed access frequency is recorded as 0 and the corresponding control address; Step S230, if the bit flip state does not appear when testing according to the initial access frequency value, the access frequency is adjusted in sequence according to the access frequency step value to calculate and generate the highest allowed access frequency and its corresponding control address and then record them.

[0040] It should be noted that the initial access frequency value is the frequency when the test device 2 first tests access to the DRAM DIE chip 13 , and the access frequency step value is the access frequency step value for adjusting the frequency when testing access to the DRAM DIE chip 13 .

[0041] Since the DRAM DIE chip 13 is an unpackaged bare crystal wafer, it is usually mass-produced and tested by a manufacturer. However, during the testing process, it is inevitable that some unusable or low-performance bare crystal chips are mixed in and packaged. In order to avoid the emergence of such products, the initial access frequency value can be set to control the test device 2 to access each DRAM DIE chip 13 with the initial access frequency value. If the DRAM DIE chip 13 is in a bit flip state when the test is performed according to the initial access frequency value, the maximum allowed access frequency can be recorded as 0 and the corresponding control address in the test log during the test process, so that the tester can replace the DRAM DIE chip 13 according to the test results. If the DRAM DIE chip 13 is not in a bit flip state when the test is performed according to the initial access frequency value, the access frequency is adjusted in sequence according to the access frequency step value until the bit flip state is detected, and the number of access behaviors of this access frequency step value is recorded, so as to calculate and generate the maximum allowed access frequency according to the initial access frequency value, the access frequency step value and the number of access behaviors (for example, the initial access frequency value A+the number of access behaviors B-1*the access frequency step value, or the initial access frequency value A+the number of access behaviors B*the access frequency step value-the preset value, etc.), and record it with the corresponding control address.

[0042] It is worth mentioning that in order to ensure the test accuracy and test efficiency, R&D personnel can set the numerical relationship between the initial access frequency value and the access frequency step value according to actual conditions, so no restrictions are made here.

[0043] In one embodiment, the step of recording the recorded highest allowed access frequency and the corresponding control address into the storage chip 12 according to the preset recording rule further includes steps S310-S320: Step S310, if the highest allowed access frequency recorded by a certain DRAM chip is 0, a prompt signal is generated according to the corresponding control address to prompt the user to replace it; Step S320 , if the highest allowed access frequency recorded in the DRAM chip is not 0, the highest allowed access frequency and the corresponding control address are recorded in the storage chip 12 .

[0044] In this embodiment, the test device 2 realizes the rapid location and management of the DRAM DIE chip 13 by querying the test log. The test log records the test process and results of each chip in detail, including key information such as the initial access frequency, access frequency step value, number of access behaviors, and maximum allowed access frequency. These data not only help to quickly identify chips with poor performance, but also provide valuable data support for subsequent quality analysis and replacement of DRAM DIE chips 13.

[0045] Specifically, the test device 2 can generate a prompt signal based on the corresponding control address when the recorded maximum allowed access frequency is 0, and the control prompt component or software prompts the user to replace the DRAM DIE chip 13 to facilitate re-sealing. When the maximum allowed access frequency recorded by the DRAM chip is not 0, the recorded maximum allowed access frequency and the corresponding control address can be entered into the storage chip 12 through the preset entry rules of the attack detection control chip 11 or other main control chips, so that the DRAM chip can maximize the working efficiency of the chip while having the ability to prevent Rowhammer attacks.

[0046] In one embodiment, before the step of acquiring the test signal, the steps S000 to S020 are also included: Step S000, querying the storage mode of the storage chip 12 to distinguish whether the storage chip 12 is in OTP mode or NORFLASH mode; Step S010, when the memory chip 12 is in the OTP mode, the read data of the memory chip 12 is obtained and compared with the preset test data to check whether the memory chip 12 can be recorded; Step S020, when the memory chip 12 is in the NORFLASH mode, after writing the inspection data to the memory chip 12, the written data of the memory chip 12 is read to see whether it is the preset inspection data, so as to check whether the memory chip 12 can be recorded.

[0047] In this embodiment, in order to increase the flexibility of the test system and formulate chips with different performance specifications, the test device 2 can establish a chip identification database through software to identify the chip ID, or analyze the interface and protocol to determine whether the memory chip 12 is in OTP mode or NORFLASH mode. Since the test device 2 needs to enter the maximum allowed access frequency and the corresponding control address into the memory chip 12, in order to avoid the situation where the test device 2 can test the DRAM chip but cannot enter the test results into the memory chip 12, when the test device 2 identifies that the memory chip 12 is in OTP mode, the read data of each storage cell (CELL) in the memory chip 12 is read and compared with the preset test data (for example, 0XFF). If there is a read data that is different from the preset test data, it is deemed that it cannot be entered. If the read data and the preset test data are the same, it is deemed that it can be entered. Similarly, when the test device 2 identifies that the memory chip 12 is in NORFLASH mode, after writing the test data to the memory chip 12, the written data of the memory chip 12 is read to see if it is the preset test data, so as to check whether the memory chip 12 can be entered.

[0048] In one embodiment, the step of recording the highest allowed access frequency and the corresponding control address into the memory chip 12 includes: Steps S400 to S420: Step S400, obtaining a start instruction; Step S410, controlling the DRAM chip to run the row hammer attack detection mode according to the startup instruction, and running the row hammer test mode again, accessing each DRAM DIE chip 13 according to the highest allowed access frequency and the corresponding control address; Step S420, after writing the verification data to each DRAM DIE chip 13, read the written data of the memory chip 12 to see whether it is the preset verification data.

[0049] In this embodiment, the DRAM chip is controlled to run the row hammer attack detection mode through a startup instruction, and the row hammer attack detection mode and the row hammer test mode are configured according to the maximum allowed access frequency and the corresponding control address of each DRAM DIE chip 13. The row hammer test mode is started to access and write test data to the DRAM chip according to the maximum allowed access frequency and the corresponding control address. If there is no error in the read test data, the DRAM chip test is deemed to be successful.

[0050] The readable storage medium provided in the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned DRAM chip test method, and can solve the technical problems of the DRAM chip test method. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in the present application are the same as the beneficial effects of the DRAM chip test method provided in the above-mentioned embodiment, and will not be repeated here.

Claims

1. A DRAM chip that is resistant to hammer attacks, characterized in that: One or more DRAM DIE chips are arranged in the DRAM chip, and the DRAM DIE chip is used to read data into the row buffer according to the received access signal, so as to wait for the read and write operation. The chip includes: A storage chip, used for storing and sending the maximum allowed access frequency value of each DRAM DIE chip and the corresponding control address; An attack detection control chip, wherein a hammer attack detection mode is provided in the attack detection control chip, the attack detection control chip is electrically connected to each of the DRAM DIE chips, and the attack detection control chip is electrically connected to the storage chip, wherein: The attack detection control chip is used to forward the access signal sent from the outside to the DRAM DIE chip. The attack detection control chip is also used to send a refresh signal to refresh the victim row when it is detected that there is a row hammer attack victim row in a certain DRAM DIE chip according to the row hammer attack detection mode, or when it is detected that the victim row in a certain DRAM DIE chip cannot be refreshed, the frequency of the access signal sent to the DRAM DIE chip is controlled according to the maximum allowed access frequency and corresponding control address of the DRAM DIE chip of the receiving storage chip.

2. The DRAM chip resistant to hammer attacks as claimed in claim 1, characterized in that: The attack detection control chip is set to be a C4 chip.

3. The DRAM chip resistant to hammer attack as claimed in claim 1, characterized in that: The storage chip is configured as an I2C chip.

4. A DRAM chip testing system, characterized in that: The DRAM chip testing system is used to test and adjust the data of the maximum allowed access frequency value of each DRAM DIE chip in the storage chip of the DRAM chip resistant to hammer attack as claimed in any one of claims 1 to 3, and the testing system comprises: A testing device is provided with a row hammer test mode, and the testing device is electrically connected to the attack detection control chip. The testing device is used to test and record the maximum allowed access frequency value data and the corresponding control address of each DRAMDIE chip in the DRAM chip through the row hammer test mode, and then enter the storage chip through the attack detection control chip.

5. A method for testing a DRAM chip, characterized in that: The DRAM chip testing method is based on the DRAM chip testing system according to claim 4, wherein the DRAM chip comprises a plurality of DRAM DIE chips, a storage chip and an attack detection control chip, and the DRAM chip is tested by a testing device, wherein a hammer test mode is provided in the testing device, and the method further comprises: Get the test signal; Running the hammer test mode according to the test signal to test each of the DRAM DIE chips, and then recording the highest allowed access frequency and the corresponding control address when a bit flip occurs in each of the DRAM DIE chips; According to the recorded highest allowed access frequency and the corresponding control address, they are entered into the storage chip according to the preset entry rules.

6. The DRAM chip testing method according to claim 5, characterized in that: The row hammer test mode is provided with an initial access frequency value for the frequency of the initial test access to the DRAM DIE chip, and an access frequency step value for adjusting the frequency of the test access to the DRAM DIE chip. The step of running the row hammer test mode according to the test instruction to test each of the DRAM DIE chips and recording the highest allowed access frequency and the corresponding control address when the bit flip occurs in each of the DRAM DIE chips comprises: Accessing each of the DRAM DIE chips according to the initial access frequency value; If a bit flip state occurs when testing according to the initial access frequency value, the highest allowed access frequency is recorded as 0 and the corresponding control address; If no bit flipping occurs when testing according to the initial access frequency value, the access frequency is adjusted in sequence according to the access frequency step value to calculate and generate the highest allowed access frequency and its corresponding control address and then record them.

7. The DRAM chip testing method according to claim 6, wherein: The step of recording the highest allowed access frequency and the corresponding control address recorded into the storage chip according to a preset recording rule also includes: If the highest allowed access frequency recorded by a certain DRAM DIE chip is 0, a prompt signal is generated according to the corresponding control address to prompt the user to replace it; If the highest allowed access frequency recorded in the DRAM DIE chip is not 0, the highest allowed access frequency and the corresponding control address are recorded and recorded into the storage chip.

8. The DRAM chip testing method according to claim 5, wherein: The step of obtaining the test signal also includes: Querying the storage mode of the storage chip to distinguish whether the storage chip is in OTP mode or NORFLASH mode; When the memory chip is in OTP mode, the read data of the memory chip is obtained, and compared with the preset test data to check whether the memory chip can be recorded; When the memory chip is in the NORFLASH mode, after the inspection data is written to the memory chip, the written data of the memory chip is read to see whether it is the preset inspection data, so as to check whether the memory chip can be recorded.

9. The DRAM chip testing method according to claim 5, characterized in that: The step of recording the highest allowed access frequency and the corresponding control address recorded in the memory chip includes: Get the startup command; Controlling the DRAM chip to run the row hammer attack detection mode according to the startup instruction, and running the row hammer test mode again, accessing each DRAM DIE chip according to the highest allowed access frequency and the corresponding control address; After the verification data is written into each of the DRAM DIE chips, the written data of the memory chip is read to determine whether it is the preset verification data.

10. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the method for testing a DRAM chip that is resistant to hammer attacks as described in any one of claims 5 to 9 are implemented.

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