Current and voltage self-balancing high-voltage-conversion-ratio converter and control method thereof

Abstract

The invention discloses a current and voltage self-balancing high-voltage-conversion-ratio converter and a control method thereof, and belongs to the technical field of power electronics. According to the high-voltage-conversion-ratio power converter provided by the invention, current / voltage self-balancing can be realized under the condition that an additional control circuit is not applied. According to the flying capacitor charge balance relation in the proposed control process, the inductive current can be automatically balanced under the condition that an additional control circuit is not applied. According to a voltage clamping relation caused by reverse conduction of a semiconductor switch body diode, flying capacitor voltage can be automatically balanced under the condition that an additional control circuit is not applied. Therefore, the design of a control circuit can be simplified, the working reliability is improved, optimal current ripple offset during inductive current superposition is ensured, and output current ripples are reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronics technology, and more specifically, relates to a current and voltage self-balancing high conversion ratio converter and a control method thereof. Background Art

[0002] In order to cope with the growing power demand in data centers, automotive electronics and other application scenarios, the power supply bus voltage is gradually evolving from 12V to 48V to reduce the energy transfer loss on the line. High conversion ratio power converters can directly convert the high-voltage bus voltage into the power supply voltage required by the low-voltage load, so they have good power density and conversion efficiency, and are suitable for load point power supply under the 48V bus voltage standard.

[0003] The existing high conversion ratio power converter topology adopts a cascade structure of a discontinuous buck charge pump and a continuous buck converter. The discontinuous buck charge pump can achieve pre-step-down with high power density, while the continuous buck converter can achieve precise output voltage regulation and avoid hard charging of the charge pump. By combining the advantages of both, this cascade structure allows high conversion ratio continuous step-down while ensuring power density and efficiency.

[0004] Traditional buck converters Switching buck converters need to work at an extremely narrow duty cycle (D) to achieve extremely high conversion ratio (CR) voltage conversion. When the operating frequency is high, the extremely narrow duty cycle will result in an extremely short switch on time. However, due to the limitation of control and drive circuit delay, the switch on time cannot be lower than the minimum value specified by the system. Therefore, it is difficult for traditional switching buck converters to achieve extremely high conversion ratio voltage conversion. Secondly, there is current-voltage overlap loss in the switching process of power devices of traditional switching buck converters. Since the switching voltage of traditional switching buck converters is equal to the bus voltage, when the bus voltage increases, it will lead to higher overlap loss, thereby causing the energy efficiency of the converter to decrease. Finally, when the traditional switching buck converter works in parallel with multiple phases, due to the mismatch of circuit parasitic parameters, the current borne by each phase in the open-loop state is unbalanced, which will cause local device heating and accelerated aging, seriously affecting the working reliability of the converter. In addition, the voltage on the flying capacitor of the existing converter that can achieve a high conversion ratio cannot be balanced in an open-loop state, which may lead to an increase in the output current ripple and a decrease in the converter performance. Summary of the invention

[0005] In view of the defects of the prior art, the purpose of the present invention is to provide a high conversion ratio converter with self-balanced current and voltage and a control method thereof, aiming to solve the problems of limited conversion ratio, large switching overlap loss and current / voltage imbalance in existing step-down converters.

[0006] To achieve the above object, the present invention provides a current-voltage self-balancing high conversion ratio converter, comprising: first to sixth switches S1-S6, first to third flying capacitors C1-C3, first and second inductors L1 and L2, an output capacitor C o ;

[0007] The drain of S1 is connected to the input voltage V BUS , the source is connected to one end of C1 and the drain of S2;

[0008] The drain of S2 is connected to the source of S1 and one end of C1, and the source is connected to the drain of S3 and one end of C2;

[0009] The drain of S3 is connected to the source of S2 and one end of C2, and the source is connected to the drain of S4 and one end of C3;

[0010] The drain of S4 is connected to the source of S3 and one end of C3, and the source is connected to the drain of S6 and the other end of C2;

[0011] The drain of S5 is connected to the other end of C1 and one end of L1, and the source is connected to the ground;

[0012] The drain of S6 is connected to the other end of C2 and one end of L2, and the source is connected to the ground;

[0013] One end of L1 is connected to the drain of S5, the other end of C1 and the other end of C3, and the other end is connected to C o one end of

[0014] One end of L2 is connected to the source of S4, the drain of S6 and the other end of C2, and the other end is connected to C o one end of

[0015] C o The other end is connected to ground.

[0016] Furthermore, the current-voltage self-balancing high conversion ratio converter has five working phases in the working mode;

[0017] In the Φ1 phase, S1 and S6 are turned on, and S2 to S5 are turned off; V BUS L1 is excited by C1, and the voltage V L1 =V BUS -V C1 -V Co ; L2 demagnetizes, the voltage across L2 is V L2 =-V Co ;

[0018] In the Φ2 phase, S2 and S5 are turned on, S1, S3, S4 and S6 are turned off; C1 and C2 are connected in series to excite L2, and the voltage V across L2 L2 =V C1 -VC2 -V Co ; L1 demagnetization, voltage V across L1 L1 =-V Co ;

[0019] In the Φ3 phase, S3 and S6 are turned on, S1, S2, S4 and S5 are turned off; C2 and C3 are connected in series to excite L1, and the voltage across L1 is V L1 =V C2 -V C3 -V Co ; L2 demagnetizes, the voltage across L2 is V L2 =-V Co ;

[0020] In the Φ4 phase, S4 and S5 are turned on, S1~S3 and S6 are turned off; C3 excites L2, and the voltage across L2 is V L2 =V C3 -V Co ; L1 demagnetization, voltage V across L1 L1 =-V Co ;

[0021] In the Φ5 phase, S5 and S6 are turned on, S1~S4 are turned off; L1 and L2 are demagnetized, and the voltage across L1 and L2 is equal to -V Co ;

[0022] Any adjacent phases from Φ1 to Φ4 operate alternately with a phase difference of 90°. The converter operates in the Φ5 phase except for the Φ1 to Φ4 phases, where V C1 is the voltage across C1, V C2 is the voltage across C2, V C3 is the voltage across C3, V Co C o Voltage across both ends.

[0023] Furthermore, the volt-second balance relationship between the inductors L1 and L2 in a steady state is expressed as:

[0024]

[0025] Among them T sw is the switching cycle;

[0026] When in steady state in the working mode, the relationship between the conversion ratio CR and the duty cycle D of the current-voltage self-balanced high conversion ratio converter is expressed as:

[0027] Furthermore, the voltage across C1 is 3V BUS / 4, the voltage across C2 is V BUS / 2, the voltage across C3 is V BUS / 4, so that the flying capacitors C1-C3 can achieve voltage balance.

[0028] The present invention also provides a control method for a current-voltage self-balanced high-conversion ratio converter, which controls switches in the above-mentioned current-voltage self-balanced high-conversion ratio converter, specifically comprising:

[0029] In the Φ1 phase, S1 and S6 are turned on, and S2 to S5 are turned off; V BUS L1 is excited by C1, and the voltage across L1 is equal to (V BUS -V C1 -V Co ); L2 demagnetizes, and the voltage across L2 is equal to -V Co ;

[0030] In the Φ2 phase, S2 and S5 are turned on, S1, S3, S4 and S6 are turned off; C1 and C2 are connected in series to excite L2, and the voltage across L2 is equal to (V C1 -V C2 -V Co ); L1 demagnetizes, and the voltage across L1 is equal to -V Co ;

[0031] In the Φ3 phase, S3 and S6 are turned on, S1, S2, S4 and S5 are turned off; C2 and C3 are connected in series to excite L1, and the voltage across L1 is equal to (V C2 -V C3 -V Co ); L2 demagnetizes, and the voltage across L2 is equal to -V Co ;

[0032] In the Φ4 phase, S4 and S5 are turned on, S1~S3 and S6 are turned off; C3 excites L2, and the voltage across L2 is equal to (V C3 -V Co ); L1 demagnetizes, and the voltage across L1 is equal to -V Co ;

[0033] In the Φ5 phase, S5 and S6 are turned on, S1~S4 are turned off; L1 and L2 are demagnetized, and the voltage across L1 and L2 is equal to -V Co ;

[0034] Any adjacent phases from Φ1 to Φ4 operate alternately with a phase difference of 90°, where V C1 is the voltage across C1, V C2 is the voltage across C2, V C3 is the voltage across C3, V Co C o Voltage across both ends.

[0035] The present invention also provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is executed by a processor, the above-mentioned control method of the device where the storage medium is located is controlled.

[0036] The present invention also provides an electronic device, comprising: a computer-readable storage medium and a processor;

[0037] The computer-readable storage medium is used to store executable instructions;

[0038] The processor is used to read the executable instructions stored in the computer-readable storage medium to execute the above control method.

[0039] Compared with the prior art, the above technical solutions conceived by the present invention can achieve the following

[0040] Beneficial effects:

[0041] 1. The high conversion ratio power converter topology and control method proposed in the present invention can achieve current / voltage self-balancing without applying additional control circuits. According to the flying capacitor charge balance relationship in the proposed control process, the inductor current can automatically reach balance without applying additional control circuits. According to the voltage clamping relationship caused by the reverse conduction of the semiconductor switch body diode in the proposed control process, the flying capacitor voltage can automatically reach balance without applying additional control circuits. This can not only simplify the control circuit design and improve the working reliability, but also ensure the optimal current ripple cancellation when the inductor current is superimposed, reducing the output current ripple.

[0042] 2. The high conversion ratio power converter topology proposed in the present invention uses only 6 semiconductor switches, which is less than the existing high conversion ratio power converter topology, and the switch voltage is V BUS / 4. Due to the reduction in the number of semiconductor switches and the switching voltage, the power loss caused by the current and voltage overlap during the high-frequency switching process is reduced, thereby improving the energy efficiency of the converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 The invention is a circuit topology of an existing high conversion ratio power converter;

[0044] Figure 2 A control method and key waveform of an existing high conversion ratio power converter;

[0045] Figure 3 A circuit topology of a high conversion ratio power converter provided by the present invention;

[0046] Figure 4A control method and key waveform of a high conversion ratio power converter provided by the present invention;

[0047] Figure 5 A potential voltage clamping relationship satisfied by a high conversion ratio power converter in a high-side conduction phase is provided by the present invention. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0049] An existing high conversion ratio power converter topology and control method thereof is composed of Figure 1 , Figure 2 express. Figure 1 The composition and structure of the converter topology are shown, which is composed of a 2:1 charge pump and a dual buck converter cascade, including 7 semiconductor switches S1~S7, 2 flying capacitors C1, C2 and 2 inductors L1, L2. The 2:1 charge pump can reduce the bus voltage by 1 / 2 in advance, and the dual buck converter can further reduce the charge pump output voltage to the voltage required by the load with a conversion ratio of 2 / D.

[0050] Figure 2 The control method and key waveforms of the converter topology are shown. The converter has four working phases (Φ1 to Φ4). During the high-side conduction period of the Φ1 phase, S1 and S3 are turned on; C1 and C2 are connected in series and connected through I L1 Charging; L1 excitation, its high side voltage is equal to (V BUS -V C1 -V C2 ); L2 demagnetizes, and its low-side voltage is equal to 0. During the high-side conduction period of Φ2 phase, S5 and S6 are turned on; C1 is turned off, and C2 is turned on by I L2 Discharge; L2 excitation, its high side voltage is equal to V C2 ; L1 demagnetizes, and its low-side voltage is equal to 0. During the high-side conduction period of Φ3 phase, S2 and S4 are turned on; C1 and C2 are connected in series, and C1 is connected through I L1 Discharge, C1 through I L1 Charging; L1 excitation, its high side voltage is equal to (V C1 -V C2 ); L2 demagnetizes, and its low-side voltage is equal to 0. During the high-side conduction period of Φ4 phase, S5 and S6 are turned on; C1 is turned off, and C2 is turned on by I L2 Discharge; L2 excitation, its high side voltage is equal to V C2; L1 is demagnetized, and its low-side voltage is equal to 0. During the low-side conduction period of phase Φ1~Φ4, S5 and S7 are turned on; C1 and C2 are disconnected; L1 and L2 are demagnetized, and their low-side voltages are both equal to 0. In order to achieve the maximum inductor current ripple cancellation, any adjacent phases of Φ1~Φ4 operate alternately with a phase difference of 90°. According to the working principle, the volt-second balance relationship of inductors L1 and L2 in steady state can be described as formula (1):

[0051]

[0052] Assume that in equilibrium, the voltage across C1 (V C1 ) is V BUS / 2, the voltage across C2 (V C2 ) is V BUS / 4, substituting into formula (1), the conversion ratio of the converter topology can be deduced as:

[0053]

[0054] The voltage across the flying capacitor of the existing high-conversion ratio power converter topology cannot automatically reach a balance. Without applying an additional control circuit, only V can be deduced based on the volt-second balance of L1 and L2 in the steady state. C2 Equal to V BUS / 4, and V C1 Can be any value. C1 During operation, the deviation from the equilibrium value (V BUS / 2), the current change rates on L1 and L2 will be unequal, and the optimal current ripple cancellation cannot be achieved when superimposed, which will eventually lead to the deterioration of the output current ripple.

[0055] The semiconductor switches S1 to S4 used in the 2:1 charge pump of the existing high-conversion ratio power converter topology work at V BUS / 2. Since the current and voltage overlap in the switching process will generate energy loss, and the energy loss is proportional to the switching voltage, the high switching voltage semiconductor switches S1-S4 will cause high power loss in the high-frequency switching process, thereby reducing the energy efficiency of the converter.

[0056] The circuit diagram of the present invention is shown in Figure 3 The high conversion ratio power converter topology comprises semiconductor switches S1 to S6, flying capacitors C1 to C3, inductors L1 and L2, and output capacitor C o composition.

[0057] The drain of S1 is connected to the input voltage V BUS, the source is connected to one end of C1 and the drain of S2; the drain of S2 is connected to the source of S1 and one end of C1, and the source is connected to the drain of S3 and one end of C2; the drain of S3 is connected to the source of S2 and one end of C2, and the source is connected to the drain of S4 and one end of C3; the drain of S4 is connected to the source of S3 and one end of C3, and the source is connected to the drain of S6 and the other end of C2; the drain of S5 is connected to the other end of C1 and one end of L1, and the source is connected to ground; the drain of S6 is connected to the other end of C2 and one end of L2, and the source is connected to ground; one end of the inductor L1 is connected to the drain of S5, the other end of C1 and the other end of C3, and the other end is connected to C o One end of the inductor L2 is connected to the source of S4, the drain of S6 and the other end of C2, and the other end is connected to C o One end.

[0058] Figure 4 The control method and key waveforms of the converter topology are shown. The converter has four working phases (Φ1 to Φ4). In one cycle, the phases other than Φ1 to Φ4 can be regarded as Φ5. During the high-side conduction period of the Φ1 phase, S1 and S6 are turned on; C2 and C3 are turned off, and C1 is connected through I L1 Charging; L1 excitation, its high side voltage is equal to (V BUS -V C1 ), the voltage across the two ends is equal to (V BUS -V C1 -V Co ); L2 demagnetizes, its low-side voltage is equal to 0, and the voltage across both ends is equal to -V Co During the high-side conduction period of the Φ2 phase, S2 and S5 are turned on; C3 is turned off, C1 and C2 are connected in series and pass through I L2 Discharge; L2 excitation, its high side voltage is equal to (V C1 -V C2 ), the voltage across the two ends is equal to (V C1 -V C2 -V Co ); L1 demagnetizes, its low-side voltage is equal to 0, and the voltage across both ends is equal to -V Co During the high-side conduction period of the Φ3 phase, S3 and S6 are turned on; C1 is turned off, C2 and C3 are connected in series and pass through I L1 Discharge; L1 excitation, its high side voltage is equal to (V C2 -V C3 ), the voltage across the two ends is equal to (V C2 -V C3 -V Co ); L2 demagnetizes, its low-side voltage is equal to 0, and the voltage across both ends is equal to -V Co During the high-side conduction period of Φ4 phase, S4 and S5 are turned on; C1 and C2 are turned off, and C3 is turned on by I L2 Discharge; L2 excitation, its high side voltage is equal to V C3 , the voltage across the two ends is equal to (V C3 -VCo ). During the low-side conduction period of Φ1~Φ4 phases, S5 and S7 are turned on; C1~C3 are disconnected; L1 and L2 are demagnetized, and their low-side voltages are both equal to 0, and the voltages at both ends are equal to -V Co In order to achieve the maximum inductor current ripple cancellation, any adjacent phases of Φ1 to Φ4 are operated alternately with a phase difference of 90°. According to the working principle, the charge balance relationship of the flying capacitors C1 to C3 in the steady state can be described as formula (3):

[0059] I L1 ·(DT SW )=I L2 ·(DT SW ) (3)

[0060] According to the charge balance relationship described in formula (3), the current balance flowing through the converter inductors L1 and L2 can be derived:

[0061] I L1 =I L2 (4)

[0062] In addition, due to the presence of a parasitic body diode inside the semiconductor switch, under the control method, the potential voltage clamping relationship satisfied by the voltage on the flying capacitors C1 to C3 during the high-side conduction phase of the Φ1 to Φ4 phases is as follows: Figure 5 As shown, it can be described by formula (5):

[0063]

[0064] Where V TH is the threshold voltage of the parasitic body diode conduction, which is about 0.7 V. By combining the inequality groups in the formula and simplifying them, the capacitor voltage balance of the converter can be derived, and its balance values ​​are:

[0065]

[0066] The balance error is ±V TH Since the current / voltage of the converter is self-balanced, the working reliability of the converter is better than that of the conventional switching buck converter and the existing high conversion ratio buck converter.

[0067] In addition, according to the working principle, the volt-second balance relationship between inductors L1 and L2 in steady state can be described as formula (7):

[0068]

[0069] Substituting formula (6) into formula (7), the conversion ratio of the converter topology can be deduced as:

[0070]

[0071] Compared with the traditional switching buck converter topology, the conversion ratio is increased by 4 times.

[0072] Finally, since the voltage on the flying capacitor automatically stabilizes near its equilibrium value during operation, under the control method, all semiconductor switches used in the converter topology operate at V BUS Compared with the existing high conversion ratio buck converter, the energy loss caused by the current and voltage overlap during the switching process of the converter is reduced, thereby improving the energy efficiency.

[0073] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A high conversion ratio converter with current and voltage self-balancing, characterized in that: include: The first to sixth switches S1 to S6, the first to third flying capacitors C1 to C3, the first and second inductors L1 and L2, the output capacitor C o ; The drain of S1 is connected to the input voltage V BUS , the source is connected to one end of C1 and the drain of S2; The drain of S2 is connected to the source of S1 and one end of C1, and the source is connected to the drain of S3 and one end of C2; The drain of S3 is connected to the source of S2 and one end of C2, and the source is connected to the drain of S4 and one end of C3; The drain of S4 is connected to the source of S3 and one end of C3, and the source is connected to the drain of S6 and the other end of C2; The drain of S5 is connected to the other end of C1 and one end of L1, and the source is connected to the ground; The drain of S6 is connected to the other end of C2 and one end of L2, and the source is connected to the ground; One end of L1 is connected to the drain of S5, the other end of C1 and the other end of C3, and the other end is connected to C o one end of One end of L2 is connected to the source of S4, the drain of S6 and the other end of C2, and the other end is connected to C o one end of C o The other end is connected to ground.

2. The current-voltage self-balancing high conversion ratio converter according to claim 1, characterized in that: The current-voltage self-balancing high conversion ratio converter has five working phases Φ1 to Φ5 in the working mode; In the Φ1 phase, S1 and S6 are turned on, and S2 to S5 are turned off; V BUS L1 is excited by C1, and the voltage V L1 =V BUS -V C1 -V Co ; L2 demagnetizes, the voltage across L2 is V L2 =-V Co ; In the Φ2 phase, S2 and S5 are turned on, S1, S3, S4 and S6 are turned off; C1 and C2 are connected in series to excite L2, and the voltage V across L2 L2 =V C1 -V C2 -V Co ; L1 demagnetization, voltage V across L1 L1 =-V Co ; In the Φ3 phase, S3 and S6 are turned on, S1, S2, S4 and S5 are turned off; C2 and C3 are connected in series to excite L1, and the voltage V L1 =V C2 -V C3 -V Co ; L2 demagnetizes, the voltage across L2 is V L2 =-V Co ; In the Φ4 phase, S4 and S5 are turned on, S1~S3 and S6 are turned off; C3 excites L2, and the voltage across L2 is V L2 =V C3 -V Co ; L1 demagnetization, voltage V across L1 L1 =-V Co ; In the Φ5 phase, S5 and S6 are turned on, S1 to S4 are turned off; L1 and L2 are demagnetized, and the voltage across L1 and L2 is equal to -V Co ; Any adjacent phases from Φ1 to Φ4 operate alternately with a phase difference of 90°. The converter operates in the Φ5 phase except for the phases from Φ1 to Φ4, where V C1 is the voltage across C1, V C2 is the voltage across C2, V C3 is the voltage across C3, V Co C o Voltage across both ends.

3. The current-voltage self-balancing high conversion ratio converter according to claim 1, characterized in that: The volt-second balance relationship of the inductors L1 and L2 in steady state is expressed as: Where T sw is the switching cycle; When in steady state in the working mode, the relationship between the conversion ratio CR and the duty cycle D of the current-voltage self-balanced high conversion ratio converter is expressed as:

4. The current-voltage self-balancing high conversion ratio converter according to claim 1, characterized in that: When the voltage of flying capacitors C1 to C3 is balanced, the voltage across C1 is 3V BUS / 4, the voltage across C2 is V BUS / 2, the voltage across C3 is V BUS / 4.

5. A control method for a current and voltage self-balanced high conversion ratio converter, characterized in that: Controlling a switch in the current-voltage self-balancing high conversion ratio converter according to any one of claims 1 to 4 specifically comprises: In the Φ1 phase, S1 and S6 are turned on, and S2 to S5 are turned off; V BUS L1 is excited by C1, and the voltage across L1 is equal to (V BUS -V C1 -V Co ); L2 demagnetizes, and the voltage across L2 is equal to -V Co ; In the Φ2 phase, S2 and S5 are turned on, S1, S3, S4 and S6 are turned off; C1 and C2 are connected in series to excite L2, and the voltage across L2 is equal to (V C1 -V C2 -V Co ); L1 demagnetizes, and the voltage across L1 is equal to -V Co ; In the Φ3 phase, S3 and S6 are turned on, S1, S2, S4 and S5 are turned off; C2 and C3 are connected in series to excite L1, and the voltage across L1 is equal to (V C2 -V C3 -V Co ); L2 demagnetizes, and the voltage across L2 is equal to -V Co ; In the Φ4 phase, S4 and S5 are turned on, S1~S3 and S6 are turned off; C3 excites L2, and the voltage across L2 is equal to (V C3 -V Co ); L1 demagnetizes, and the voltage across L1 is equal to -V Co ; In the Φ5 phase, S5 and S6 are turned on, S1~S4 are turned off; L1 and L2 are demagnetized, and the voltage across L1 and L2 is equal to -V Co ; Any adjacent phases from Φ1 to Φ4 operate alternately with a phase difference of 90°, where V C1 is the voltage across C1, V C2 is the voltage across C2, V C3 is the voltage across C3, V Co C o Voltage across both ends.

6. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the control method according to claim 5.

7. An electronic device, characterized in that: include: A computer readable storage medium and a processor; The computer-readable storage medium is used to store executable instructions; The processor is used to read the executable instructions stored in the computer-readable storage medium to execute the control method as claimed in claim 5.

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