Bottom gate type InAs / AlSb MOS-HEMT device and preparation method thereof

Abstract

The invention discloses a bottom gate type InAs / AlSb MOS-HEMT device and a preparation method thereof, and relates to the technical field of microelectronic devices, and the device comprises a substrate, a buffer layer, a lower barrier layer, a doping layer, an isolation layer, a channel layer, an upper barrier layer and a cover layer which are sequentially stacked from bottom to top. The channel layer comprises an undoped InAs channel region, an n-InAs high-resistance region and an n + InAs low-resistance region from inside to outside; a passivation isolation region is arranged below the n-InAs high-resistance region, and a source-drain region is arranged below the n + InAs low-resistance region; the substrate is provided with a gate groove, and a gate electrode is arranged in the gate groove. According to the invention, the grid electrode is arranged on the substrate, so that the high interface state density is reduced, and the problem of grid electrode electric leakage caused by corrosion residue or over-corrosion of the InAs cover layer is avoided; the n-InAs high-resistance region is arranged on the channel layer, so that the collision ionization effect generated by the InAs material under high electric field intensity is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of microelectronic devices, and in particular to a bottom-gate InAs / AlSb MOS-HEMT device and a preparation method thereof. Background Art

[0002] InAs / AlSb quantum well heterojunction has a high 2 / V·s electron mobility can be used to prepare ultra-high-speed, low-power InAs / AlSb HEMT devices, which are used in wireless high-frequency communications, military radar, portable mobile devices, vacuum detection and other fields.

[0003] In the prior art, Chinese patent CN107195548A discloses a method for preparing InAs / AlSb HEMT and MOS-HEMT devices, wherein the method for preparing InAs / AlSb MOS-HEMT devices includes the following process steps: 1) epitaxial material growth; 2) mesa isolation; 3) preparation of ohmic contact; 4) preparation of insulating gate; 5) pad deposition; 6) passivation. This prior art omits the gate trench etching step, reduces gate current leakage, and simultaneously reduces the on-resistance of the device.

[0004] However, the InAs / AlSb HEMT devices prepared by the prior art still have a large gate leakage current, which seriously affects the performance of the device. On the one hand, because the InAlAs layer and the gate metal in the InAs / AlSb HEMT device form a Schottky gate structure, although InAlAs can block holes to form gate leakage current to a certain extent as a barrier layer, its blocking effect is not ideal. If a gate dielectric layer is added between the InAlAs layer and the gate metal to form an InAs / AlSb MOS-HEMT structure, the gate leakage current can be reduced to a certain extent. However, there is a high interface state density between the III-V compound and the gate dielectric interface, forming a carrier scattering center, resulting in a low electron mobility in the channel layer. On the other hand, when the InAs cap layer is wet-etched to form a gate groove in the InAs / AlSb HEMT or MOS-HEMT device, the etching time and depth are uncontrollable, and it is easy to produce residual or over-etching of the InAs cap layer, which will also cause a certain degree of gate leakage current. Thirdly, as the applied bias voltage increases, the InAs / AlSb HEMT device will experience collision ionization effect, resulting in an increase in channel leakage current, so that the channel current no longer presents a saturation state as the applied voltage increases, and the Kink effect occurs. However, the above-mentioned prior art does not study or solve the above-mentioned problem. Summary of the invention

[0005] The present application provides a bottom-gate InAs / AlSb MOS-HEMT device and a preparation method thereof, which are used to solve the problems in the existing InAs / AlSb MOS-HEMT device technology that the high interface state density between the III-V compound and the gate dielectric interface leads to low electron mobility in the channel layer, corrosion residue or over-corrosion is easily generated when the InAs cap layer is corroded, and the channel layer is prone to collision ionization effect under a strong electric field.

[0006] On the one hand, the present application provides a bottom-gate InAs / AlSb MOS-HEMT device, comprising: an SOI substrate, a buffer layer, an AlSb lower barrier layer, an InAs doped layer, an AlSb isolation layer, an InAs channel layer, an AlSb upper barrier layer and an InAlAs cap layer stacked in sequence from bottom to top.

[0007] The SOI substrate comprises a bottom Si layer, a middle SiO 2 layer and top Si layer.

[0008] The InAs channel layer comprises, from inside to outside, an undoped InAs channel region, an n-InAs high resistance region and an n+InAs low resistance region.

[0009] A SiO 2 A passivation isolation region is provided with a source and drain region below the n+InAs low resistance region.

[0010] The SiO 2 A gate groove is disposed below the layer, and a gate is disposed in the gate groove.

[0011] In a possible implementation, the initial thickness of the bottom Si layer is 100-500 μm, and the resistivity is greater than or equal to 1000 Ω•cm; 2 The initial thickness of the layer is 50-200nm; the initial thickness of the top Si layer is less than or equal to 100nm, and the resistivity is greater than or equal to 1000Ω•cm.

[0012] In a possible implementation, the gate groove is formed by etching the bottom Si layer of the SOI substrate between the source and drain regions until the bottom Si layer is completely etched, and then aligning the SiO 2 It is formed by etching the middle area of ​​the layer.

[0013] After etching, SiO 2 The thickness of the layer is 1-10 nm.

[0014] In a possible implementation, the material of the buffer layer is GaAs, AlSb, GaSb, GaP or a ternary or quaternary compound thereof, and the structure of the buffer layer is a single-layer structure of one material or a multi-layer composite structure composed of different materials.

[0015] The thickness of the buffer layer is 100-1000 nm.

[0016] In a possible implementation, the n-InAs high resistance region is formed by Be doping, and the n+InAs low resistance region is formed by Si doping.

[0017] In a possible implementation, the width of the n-InAs high resistance region is 5-2000 nm, and the width of the n+InAs low resistance region is 1-50 μm.

[0018] In a possible implementation, the thickness of the AlSb lower barrier layer is 5-50nm, the thickness of the InAs doping layer is 1-2nm, the thickness of the AlSb isolation layer is 1-5nm, the thickness of the InAs channel layer is 10-30nm, the thickness of the AlSb upper barrier layer is 5-10nm, and the thickness of the InAlAs cap layer is 2-20nm.

[0019] On the other hand, the present application provides a method for preparing a bottom-gate InAs / AlSb MOS-HEMT device, comprising the following steps: Step 1: A buffer layer, an AlSb lower barrier layer, an InAs doped layer, an AlSb isolation layer, an InAs channel layer, an AlSb upper barrier layer and an InAlAs cap layer are sequentially grown on the SOI substrate to obtain an epitaxial structure of an InAs / AlSb MOS-HEMT device.

[0020] Step 2: Invert the epitaxial structure and etch downward from the outer area of ​​the bottom Si layer of the SOI substrate until the InAs channel layer is exposed.

[0021] Step three: Be-doping the inner region of the exposed portion of the InAs channel layer to form an n-InAs high resistance region.

[0022] Step 4: Si-doping is performed on the outer region of the exposed portion of the InAs channel layer to form an n+InAs low resistance region.

[0023] Step five: depositing metal on the n+InAs low resistance region to form source and drain regions.

[0024] Step 6: Etch the bottom Si layer of the SOI substrate between the source and drain regions until the bottom Si layer is completely etched, and then etch the middle SiO2 The middle area of ​​the layer is etched to form a gate groove.

[0025] Step seven: depositing metal in the gate groove to form a gate.

[0026] Step 8: SiO2 is applied to the area outside the source, drain and gate. 2 Passivation, forming SiO 2 The isolation region is passivated to obtain a bottom-gate InAs / AlSb MOS-HEMT device.

[0027] A bottom-gate InAs / AlSb MOS-HEMT device and a preparation method thereof in the present application have the following advantages: Through the SiO 2 The gate layer is set in SiO 2 The layer is used as the gate dielectric layer of the InAs / AlSb MOS-HEMT device, which can avoid the high interface state density caused by growing the gate dielectric layer on the surface of the III-V compound, thereby improving the electron mobility of the InAs channel layer, and at the same time avoids the corrosion residue or over-corrosion problem caused by etching the InAs cap layer when forming the gate groove in the prior art.

[0028] By setting an n-InAs high resistance region in the InAs channel layer, there are lightly doped regions on both sides of the undoped InAs channel region, which reduces the electric field strength applied to the undoped InAs channel region and reduces the impact ionization effect of the narrow bandgap InAs material under high electric field strength.

[0029] The ohmic contact resistance of the InAs / AlSb MOS-HEMT device is reduced by arranging the source and drain regions below the n+InAs low resistance region.

[0030] By placing SiO below the n-InAs high resistance region 2 Passivation isolation region, SiO 2 The passivation isolation region isolates the source and drain regions from the SOI substrate, the buffer layer, the AlSb lower barrier layer, the InAs doping layer, and the AlSb isolation layer, so that carriers are only transmitted in the InAs channel layer, thereby avoiding leakage of the InAs / AlSb MOS-HEMT device.

[0031] The bottom-gate InAs / AlSb MOS-HEMT device prepared in the present application can adopt flip chip bonding packaging technology when packaging, which can save wires and reduce the packaging size compared with the traditional wire bonding technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 A schematic diagram of the structure of a bottom-gate InAs / AlSb MOS-HEMT device provided in an embodiment of the present application; Figure 2 A schematic diagram of a process for preparing a bottom-gate InAs / AlSb MOS-HEMT device provided in an embodiment of the present application; Figure 3 A schematic diagram of the epitaxial structure of an InAs / AlSb MOS-HEMT device corresponding to step 1 provided in an embodiment of the present application; Figure 4 A schematic diagram of the epitaxial structure of an InAs / AlSb MOS-HEMT device corresponding to step 2 provided in an embodiment of the present application; Figure 5 A schematic diagram of the epitaxial structure of an InAs / AlSb MOS-HEMT device corresponding to step three provided in an embodiment of the present application; Figure 6 A schematic diagram of the epitaxial structure of an InAs / AlSb MOS-HEMT device corresponding to step 4 provided in an embodiment of the present application; Figure 7 A schematic diagram of the epitaxial structure of an InAs / AlSb MOS-HEMT device corresponding to step five provided in an embodiment of the present application; Figure 8 A schematic diagram of the epitaxial structure of an InAs / AlSb MOS-HEMT device corresponding to step six provided in an embodiment of the present application; Fig. 9 Schematic diagram of the epitaxial structure of the InAs / AlSb MOS-HEMT device corresponding to step seven provided in an embodiment of the present application.

[0034] Description of reference numerals: 101- bottom Si layer, 102- middle SiO 2 layer, 103-top Si layer, 2-buffer layer, 3-AlSb lower barrier layer, 4-InAs doped layer, 5-AlSb isolation layer, 6-InAs channel layer, 7-AlSb upper barrier layer, 8-InAlAs cap layer, 601-undoped InAs channel region, 602-n-InAs high resistance region, 603-n+InAs low resistance region, 604-SiO 2Passivation isolation region, 605 - source region, 606 - drain region, 104 - gate. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] Embodiment 1: like Figure 1 As shown, Example 1 of the present application provides a bottom-gate InAs / AlSb MOS-HEMT device, comprising: an SOI substrate, a buffer layer 2, an AlSb lower barrier layer 3, an InAs doping layer 4, an AlSb isolation layer 5, an InAs channel layer 6, an AlSb upper barrier layer 7 and an InAlAs cap layer 8 stacked in sequence from bottom to top.

[0037] The SOI substrate comprises a bottom Si layer 101, a middle SiO 2 layer 102 and a top Si layer 103 .

[0038] The InAs channel layer 6 includes, from inside to outside, an undoped InAs channel region 601 , an n-InAs high resistance region 602 , and an n+InAs low resistance region 603 .

[0039] SiO is disposed below the n-InAs high resistance region 602. 2 The passivation isolation region 604 has a source and drain region disposed below the n+InAs low resistance region 603 .

[0040] Specifically, the source-drain region includes a source region 605 and a drain region 606 .

[0041] The SiO 2 A gate groove is disposed downwardly of the layer 102 , and a gate 104 is disposed in the gate groove.

[0042] Exemplarily, the gate groove is formed by etching the bottom Si layer 101 of the SOI substrate between the source and drain regions until the bottom Si layer 101 is completely etched, and then etching the middle SiO 2 The middle region of the layer 102 is etched.

[0043] Exemplarily, the n-InAs high resistance region 602 is formed by Be doping, and the n+InAs low resistance region 603 is formed by Si doping.

[0044] Specifically, in this embodiment, the initial thickness of the bottom Si layer 101 is 100 μm, and the resistivity is 1000 Ω•cm; 2 The initial thickness of the Si layer 102 is 200 nm, the initial thickness of the top Si layer 103 is 100 nm, and the resistivity is 1000 Ω•cm; 2 The thickness of layer 102 is 1nm; the buffer layer 2 adopts an AlSb single-layer structure with a thickness of 1μm; the width of the n-InAs high resistance region 602 is 5nm, and the width of the n+InAs low resistance region 603 is 1μm; the thickness of the AlSb lower barrier layer 3 is 5nm, the thickness of the InAs doping layer 4 is 1nm, the doping material is Si, the thickness of the AlSb isolation layer 5 is 1nm, the thickness of the InAs channel layer 6 is 10nm, the thickness of the AlSb upper barrier layer 7 is 5nm, and the thickness of the InAlAs cap layer 8 is 2nm.

[0045] like Figure 2 As shown, Example 1 of the present application also provides a method for preparing a bottom-gate InAs / AlSb MOS-HEMT device, comprising the following steps: Step 1: A buffer layer 2, an AlSb lower barrier layer 3, an InAs doped layer 4, an AlSb isolation layer 5, an InAs channel layer 6, an AlSb upper barrier layer 7 and an InAlAs cap layer 8 are sequentially grown on the SOI substrate to obtain an epitaxial structure of an InAs / AlSb MOS-HEMT device.

[0046] Step 2: Invert the epitaxial structure and etch downward from the outer area of ​​the bottom Si layer 101 of the SOI substrate until the InAs channel layer 6 is exposed.

[0047] Step three: Be-doping the inner region of the exposed portion of the InAs channel layer 6 to form an n-InAs high resistance region 602 .

[0048] Step 4: Si-doping is performed on the outer region of the exposed portion of the InAs channel layer 6 to form an n+InAs low resistance region 603 .

[0049] Step five: depositing metal on the n+InAs low resistance region 603 to form source and drain regions.

[0050] Step 6: Etch the bottom Si layer 101 of the SOI substrate between the source and drain regions until the bottom Si layer 101 is completely etched, and then etch the middle SiO 2 The middle region of the layer 102 is etched to form a gate groove.

[0051] Step seven: depositing metal in the gate groove to form the gate 104.

[0052] Step 8: SiO2 is applied to the area outside the source, drain and gate. 2 Passivation, in particular, depositing SiO on the n-InAs high resistance region 602 2 , forming SiO 2 The isolation region 604 is passivated, and the resulting epitaxial structure is inverted again to obtain a bottom-gate InAs / AlSb MOS-HEMT device.

[0053] like Figures 3 to 9 The following are schematic diagrams of the epitaxial structure of the InAs / AlSb MOS-HEMT device corresponding to each step from step 1 to step 7. The bottom-gate InAs / AlSb MOS-HEMT device obtained in step 8 corresponds to Figure 1 .pass Figures 3 to 9 , Figure 1 , combined with steps 1 to 8, the preparation process of the bottom-gate InAs / AlSb MOS-HEMT device of the present application can be intuitively and clearly seen.

[0054] Embodiment 2: In Example 2, the initial thickness of the bottom Si layer 101 is 300 μm and the resistivity is 10000 Ω•cm; 2 The initial thickness of the Si layer 102 is 100 nm, the initial thickness of the top Si layer 103 is 50 nm, and the resistivity is 10000 Ω•cm; 2 The thickness of the layer 102 is 5nm; the buffer layer 2 adopts a two-layer structure of AlSb / GaSb, wherein the thickness of AlSb is 100nm and the thickness of GaSb is 900nm; the width of the n-InAs high resistance region 602 is 1000nm, and the width of the n+InAs low resistance region 603 is 25μm; the thickness of the AlSb lower barrier layer 3 is 20nm, the thickness of the InAs doping layer 4 is 1.2nm, the doping material is Si, the thickness of the AlSb isolation layer 5 is 3nm, the thickness of the InAs channel layer 6 is 15nm, the thickness of the AlSb upper barrier layer 7 is 8nm, and the thickness of the InAlAs cap layer 8 is 10nm. The other structures and preparation methods of Example 2 are the same as those of Example 1.

[0055] Embodiment 3: In Example 3, the initial thickness of the bottom Si layer 101 is 500 μm and the resistivity is 100,000 Ω•cm; 2 The initial thickness of the layer 102 is 50nm, the initial thickness of the top Si layer 103 is 30nm, and the resistivity is 100000Ω•cm; 2The thickness of the layer 102 is 10nm; the buffer layer 2 adopts a three-layer structure of AlSb / GaSb / AlGaSb, wherein the thickness of AlSb is 100nm, the thickness of GaSb is 100nm, and the thickness of AlGaSb is 800nm; the width of the n-InAs high resistance region 602 is 2μm, and the width of the n+InAs low resistance region 603 is 50μm; the thickness of the AlSb lower barrier layer 3 is 50nm, the thickness of the InAs doping layer 4 is 2nm, the doping material is Si, the thickness of the AlSb isolation layer 5 is 5nm, the thickness of the InAs channel layer 6 is 30nm, the thickness of the AlSb upper barrier layer 7 is 10nm, and the thickness of the InAlAs cap layer 8 is 20nm. The other structures and preparation methods of Example 3 are the same as those of Example 1.

[0056] Specifically, in Examples 1 to 3, the metals deposited when forming the source / drain regions and the gate are all made of Pd / Ti / Pt / Au alloy materials. In other possible embodiments, Ni / Au alloy materials or other metal materials may also be used. The etching techniques used in Examples 1 to 3 are all inductively coupled plasma etching (ICP etching). In other possible embodiments, wet etching techniques may also be used.

[0057] In the embodiment of the present application, SiO 2 The gate 104 is set in the layer 102, and the SiO 2 Layer 102 serves as the gate dielectric layer of the InAs / AlSb MOS-HEMT device, which can avoid the high interface state density caused by growing the gate dielectric layer on the surface of the III-V compound, thereby improving the electron mobility of the InAs channel layer 6, and at the same time avoiding the corrosion residue or over-corrosion problem caused by etching the InAs cap layer when forming the gate groove in the prior art.

[0058] By setting the n-InAs high resistance region 602 in the InAs channel layer 6, lightly doped regions exist on both sides of the undoped InAs channel region 601, which reduces the electric field strength applied to the undoped InAs channel region 601 and reduces the impact ionization effect of the narrow bandgap InAs material under high electric field strength.

[0059] By arranging the source and drain regions below the n+InAs low resistance region 603 , the ohmic contact resistance of the InAs / AlSb MOS-HEMT device is reduced.

[0060] By providing SiO below the n-InAs high resistance region 602 2 Passivation isolation region 604, SiO 2The passivation isolation region 604 isolates the source and drain regions from the SOI substrate, the buffer layer 2, the AlSb lower barrier layer 3, the InAs doping layer 4, and the AlSb isolation layer 5, so that carriers are only transmitted in the InAs channel layer 6, thereby avoiding leakage of the InAs / AlSb MOS-HEMT device.

[0061] The bottom-gate InAs / AlSb MOS-HEMT device prepared in the present application can adopt flip chip bonding packaging technology when packaging, which can save wires and reduce the packaging size compared with the traditional wire bonding technology.

[0062] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0063] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A bottom-gate InAs / AlSb MOS-HEMT device, characterized in that: include: An SOI substrate, a buffer layer, an AlSb lower barrier layer, an InAs doping layer, an AlSb isolation layer, an InAs channel layer, an AlSb upper barrier layer and an InAlAs cap layer are stacked sequentially from bottom to top; The SOI substrate comprises, from bottom to top, a bottom Si layer, a middle SiO2 layer and a top Si layer; The InAs channel layer includes, from inside to outside, an undoped InAs channel region, an n-InAs high resistance region, and an n+InAs low resistance region; A SiO2 passivation isolation region is disposed below the n-InAs high resistance region, and a source-drain region is disposed below the n+InAs low resistance region; A gate groove is arranged downward in the SiO2 layer of the SOI substrate, and a gate is arranged in the gate groove.

2. A bottom-gate InAs / AlSb MOS-HEMT device according to claim 1, characterized in that: The initial thickness of the bottom Si layer is 100-500 μm, and the resistivity is greater than or equal to 1000 Ω•cm; the initial thickness of the middle SiO2 layer is 50-200 nm; the initial thickness of the top Si layer is less than or equal to 100 nm, and the resistivity is greater than or equal to 1000 Ω•cm.

3. A bottom-gate InAs / AlSb MOS-HEMT device according to claim 1, characterized in that: The gate groove is formed by etching the bottom Si layer of the SOI substrate between the source and drain regions until the bottom Si layer is completely etched, and then etching the middle area of ​​the middle SiO2 layer; The thickness of the SiO2 layer after etching is 1-10nm.

4. A bottom-gate InAs / AlSb MOS-HEMT device according to claim 1, characterized in that: The material of the buffer layer is GaAs, AlSb, GaSb, GaP or a ternary or quaternary compound thereof, and the structure of the buffer layer is a single-layer structure of a single material or a multi-layer composite structure composed of different materials; The thickness of the buffer layer is 100-1000 nm.

5. The bottom-gate InAs / AlSb MOS-HEMT device according to claim 1, characterized in that: The n-InAs high resistance region is formed by Be doping, and the n+InAs low resistance region is formed by Si doping.

6. A bottom-gate InAs / AlSb MOS-HEMT device according to claim 5, characterized in that: The width of the n-InAs high resistance region is 5-2000 nm, and the width of the n+InAs low resistance region is 1-50 μm.

7. The bottom-gate InAs / AlSb MOS-HEMT device according to claim 1, characterized in that: The thickness of the AlSb lower barrier layer is 5-50nm, the thickness of the InAs doping layer is 1-2nm, the thickness of the AlSb isolation layer is 1-5nm, the thickness of the InAs channel layer is 10-30nm, the thickness of the AlSb upper barrier layer is 5-10nm, and the thickness of the InAlAs cap layer is 2-20nm.

8. A method for preparing a bottom-gate InAs / AlSb MOS-HEMT device according to any one of claims 1 to 7, characterized in that: The following steps are involved: Step 1: growing a buffer layer, an AlSb lower barrier layer, an InAs doping layer, an AlSb isolation layer, an InAs channel layer, an AlSb upper barrier layer and an InAlAs cap layer in sequence on the SOI substrate to obtain an epitaxial structure of an InAs / AlSb MOS-HEMT device; Step 2, inverting the epitaxial structure, and etching downward from the outer area of ​​the bottom Si layer of the SOI substrate until the InAs channel layer is exposed; Step 3, Be-doping the inner region of the exposed portion of the InAs channel layer to form an n-InAs high resistance region; Step 4, Si-doping the outer region of the exposed portion of the InAs channel layer to form an n+InAs low resistance region; Step 5, depositing metal on the n+InAs low resistance region to form source and drain regions; Step 6, etching the bottom Si layer of the SOI substrate between the source and drain regions until the bottom Si layer is completely etched, and then etching the middle area of ​​the middle SiO2 layer to form a gate groove; Step seven, depositing metal in the gate groove to form a gate; Step eight, performing SiO2 passivation on the area outside the source, drain and gate to form a SiO2 passivation isolation region, and obtaining a bottom-gate InAs / AlSb MOS-HEMT device.

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