Data transmission path suitable for FFT algorithm

Abstract

The invention relates to the technical field of data transmission, in particular to a data transmission path suitable for an FFT (Fast Fourier Transform) algorithm, and provides a scheme as follows: data is acquired from a DDR (Double Data Rate) memory through an AXI (Advanced eXtensible Interface) bus and is transmitted to an SRAM (Static Random Access Memory) array through DMA ( A data transmission interface is combined with an fftport module, so that 256-bit data (four 64-bit floating-point numbers) are transmitted in each period, and the transmission rate is increased by four times. The path includes a conflict-free access controller that efficiently stores data to the SRAM through an index-address translation rule. Besides, the system supports multi-batch processing and zero padding operation, ensures that the number of data points meets the requirements of an FFT algorithm, and adapts to the processing requirements of 2 < n > power and non 2 < n > power data sets. And the handshake signal control unit dynamically manages the ack signal and pauses data transmission during the zero padding period. The access supports FFT operation of maximum 4M points, and meets efficient and large-scale data processing requirements.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a data transmission path suitable for FFT algorithm. Background Art

[0002] Under the design structure of the three-dimensional reconfigurable hardware acceleration core, the implementation of the FFT algorithm needs to rely on the butterfly memory controller. Before the butterfly memory controller starts calculating, it needs to move the source data in the DDR into the storage area (SRAM) through DMA. This function is implemented by the fft_port module (data transmission interface), which transmits the data sent by DMA to different locations in SRAM according to specific no-memory access conflict corresponding rules. Because the data transmission on the axi bus is 256 bits at a time, and the data processed by the butterfly memory controller is 64-bit single-precision floating point numbers, it is equivalent to DMA transmitting 4 data to the butterfly memory controller in one cycle. In previous hardware designs, due to the no-memory conflict corresponding rules and the limitations of data zero padding operations, fft_port can only complete 4 cycles of transmission at a transmission rate of 256 bits.

[0003] At the same time, it should be added that the data transmission from DMA to the SRAM array needs to wait until fft_port receives the data and returns an ack signal to DMA normally before continuing the next data transmission, that is, data transmission can continue after handshake.

[0004] The above patents all have the problem raised by this background technology: fft_port can only complete 4 cycles of transmission at a transmission rate of 256 bits. To solve the above problem, this application designs a data transmission path suitable for the FFT algorithm. Summary of the invention

[0005] The technical problem to be solved by the present invention is to address the deficiencies of the prior art and provide a data transmission path suitable for the FFT algorithm, which obtains source data from the DDR memory through the AXI bus and transmits it to the SRAM array. The data transmission interface adopts direct memory access (DMA) technology to transmit 256-bit data in each cycle, and includes a conflict-free memory access controller for mapping each 64-bit floating-point number to an independent storage address in the SRAM through the index-address conversion rule. In order to cope with data that is not a power of 2, the data zero padding module is responsible for padding the data to the power of 2 before transmitting it, and controls the suspension and resumption of data transmission through a handshake signal control unit. The system can dynamically adjust the state of the ack signal to adapt to the processing requirements of FFT data sets with different numbers of points, and realize efficient and conflict-free data transmission and storage.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A data transmission path suitable for an FFT algorithm, wherein the data transmission path obtains source data from a DDR memory through an AXI bus and transmits the source data to an SRAM array, comprising:

[0008] A data transmission interface is used to obtain data from an external memory through direct memory access technology and transmit the data to an SRAM array. The data is a 64-bit single-precision floating point number, and the data width transmitted in each cycle is 256 bits.

[0009] AXI bus, used for data transfer between external memory and SRAM array;

[0010] A conflict-free memory access controller, the controller comprising an index-address conversion rule, for mapping each 64-bit data in the received 256-bit data to an independent storage address of the SRAM according to the index conversion rule;

[0011] The data zero-filling module is used to fill the insufficient data with zeros to the power of 2 before transmitting it to the SRAM when the amount of data to be transmitted does not meet the requirements of the FFT algorithm.

[0012] The data transmission interface also includes a handshake signal control unit, which is used to suspend or resume DMA data transmission by controlling the pulling down and pulling up of the ack signal during the data transmission process. When a data zero padding operation needs to be performed, the ack signal is actively pulled down to suspend data transmission, and after the zero padding operation is completed, the ack signal is pulled up to resume data transmission.

[0013] The data transmission interface can complete the data transmission of multiple 64-bit floating-point numbers at the same time. In one data transmission cycle, the 256-bit data transmitted by DMA to SRAM is divided into four groups, each group corresponds to a 64-bit floating-point number, and the conflict-free storage of each floating-point number in SRAM is achieved through the index-address conversion rule.

[0014] The handshake signal control unit dynamically calculates when to start pulling down the ack signal according to the amount of data transmission, so as to suspend data transmission and perform zero padding when necessary. The calculation method is to determine the time point of pulling down the ack signal by the quotient of the data transmission modulo 4.

[0015] The zero-filling module further includes a register storage unit, which is used to temporarily store unused data during the data zero-filling operation, and transmit it to the SRAM after being combined with subsequent data during the next data transmission.

[0016] When the transmission batch is a plurality of batches of data that is not a power of 2, the register storage unit can store unused data at the end of the previous batch of data transmission cycles.

[0017] The index-address conversion rule generates a unique storage address corresponding to each data in real time according to the batch of data transmission and the storage location in the SRAM.

[0018] After receiving the 256-bit data transmitted from the DDR, the data transmission interface can immediately transfer the data to a specific location in the SRAM according to the index rule, and ensure that there is no address conflict during the transmission process through the internal address conversion logic.

[0019] The handshake signal control unit dynamically adjusts the pull-up or pull-down of the ack signal according to the current data transmission amount and the zero-filling requirement to ensure that the data transmission of the DMA will not affect the data storage in the SRAM when performing the data zero-filling operation.

[0020] The data transmission interface is suitable for processing FFT data sets of different number of points, including data sets of 2 to the power of n and non-2 to the power of n, and can automatically perform data zero padding operations according to the size of the data set to meet the requirements of the FFT algorithm for data of a specific number of points.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] 1. The present invention combines the AXI bus and DMA to transmit 256-bit data in each cycle and supports parallel transmission of multiple 64-bit floating-point numbers, which greatly improves the bandwidth and speed of data transmission, meets the requirements of the FFT algorithm for efficient data processing, and increases the data transmission rate by four times;

[0023] 2. The present invention adopts index-address conversion rules to map each data block to an independent storage address in SRAM, thereby avoiding data storage conflicts, ensuring reasonable distribution of data in SRAM, and improving storage utilization and computing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0025] Figure 1 This is a module schematic diagram of a data transmission path suitable for an FFT algorithm in Embodiment 1 of the present invention;

[0026] Figure 2 This is a data transmission flow diagram of embodiment 1 of the present invention;

[0027] Figure 3 This is a butterfly memory access storage space partition diagram of embodiment 1 of the present invention;

[0028] Figure 4This is a flowchart of the butterfly memory access controller according to Embodiment 1 of the present invention; DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0030] Embodiment 1:

[0031] See also Figure 1 , an embodiment of the present invention provides: a data transmission path suitable for an FFT algorithm, the data transmission path obtains source data from a DDR memory through an AXI bus and transmits it to a DMA, and distributes the data to an SRAM array through an fft_port, comprising:

[0032] AXI bus, used to transfer data between DDR memory and DMA;

[0033] Data transfer interface, used to obtain bus data from DMA through direct memory access technology, and transfer the data to the SRAM array, the data is 64-bit single-precision floating point number, the data width transmitted in each cycle is 256 bits, the data transmission width is 256 bits, and 4 64-bit single-precision floating point numbers are transmitted in each cycle. The data transfer interface also includes multiple parallel channels to ensure the stability and accuracy of data during high-speed transmission. The data transfer interface is responsible for managing the data scheduling from DDR to SRAM, and includes a cache mechanism to ensure the continuity and consistency of the data flow;

[0034] A conflict-free memory access controller, the controller includes an index-address conversion rule, which is used to map each 64-bit data in the received 256-bit data to an independent storage address of the SRAM according to a preset index conversion rule. Each 64-bit data is assigned a unique index value, and the controller maps the data to a specific storage unit in the SRAM according to the index value to ensure that there is no storage address conflict during the data transmission process. The index-address conversion rule is based on a hash algorithm or a linear mapping algorithm, which can generate the storage address of the data in real time, ensure the conflict-free memory access, and dynamically adjust the mapping strategy according to the data batch and transmission progress to optimize the data storage efficiency. The conflict-free memory access controller also includes an address mapping table, which is used to record the specific storage location of each data, ensuring that the relevant data can be accessed quickly and accurately when performing FFT calculations;

[0035] The data zero-filling module is used to fill the insufficient data with zeros to the power of 2 before transmitting it to the SRAM when the amount of data to be transmitted does not meet the requirements of the FFT algorithm. The FFT algorithm usually requires the amount of input data to be the power of 2. If the amount of source data is insufficient, a zero-filling operation needs to be performed at the end of the data. The data zero-filling module includes:

[0036] Zero-filling detection unit: used to detect whether the number of points of the input data meets the requirement of 2 to the power of n. If not, the zero-filling operation is automatically started;

[0037] Zero-padding control unit: calculates the amount of data to be padded with zeros according to the feedback from the zero-padding detection unit, and generates zero-padding data, wherein the zero-padding data is filled with all zeros and is used to complete the source data;

[0038] Zero-padding execution unit: During the data transmission process, the zero-padding data is inserted into the transmission queue, and the zero-padding data is ensured to be transmitted to the SRAM array according to the AXI bus protocol. The execution unit supports the zero-padding operation of multiple batches of data to ensure that each batch of data meets the input requirements of the FFT algorithm;

[0039] Register storage unit: used to temporarily store unprocessed data during the zero-filling operation. In particular, when the amount of transmitted data is insufficient, the register can record the unfinished data in the previous transmission cycle to ensure the correctness of the zero-filling operation in the next cycle. The register also supports cross-cycle data storage management and can maintain data consistency in multiple transmission cycles.

[0040] See also Figure 2 , the data transmission flow diagram of the embodiment of the present invention, the components involved include AXI bus, DMA, FFT_DMA_PORT and multiple groups of storage BANK (a, b, c, d), the data is first obtained from the DDR memory through the AXI bus and transmitted to the DMA module. The DMA module divides the transmitted 256-bit data into 4 64-bit floating-point numbers and transmits them to FFT_DMA_PORT. According to the index-address conversion rule, FFT_DMA_PORT maps each 64-bit floating-point number to different BANKs (a, b, c, d) in the SRAM for storage. In order to avoid storage conflicts, FFT_DMA_PORT uses a dynamic address generation algorithm to ensure that each data block has a unique storage address. When the amount of data is less than 2 to the power of n, FFT_DMA_PORT triggers the data zero-filling module to automatically fill the data and continue to transmit.

[0041] During data transmission, the handshake signal control unit is responsible for controlling the ack signal to ensure that data is not lost or out of order during transmission and zero padding.

[0042] The AXI bus is the core of the entire data transmission path, used to transfer data between DDR memory and other modules (such as DMA and SRAM arrays). The figure shows the AXI bus as the top-level module, which is responsible for obtaining data from the external memory and passing the data through the downstream DMA module. In this embodiment, the AXI bus transmits 256 bits of data each time to ensure that the bandwidth requirements of the FFT algorithm are met. Through multi-channel parallel processing, the AXI bus can transmit multiple data blocks in a single cycle, ensuring the efficiency and reliability of data transmission;

[0043] The DMA module is used to transfer data between the AXI bus and the FFT_DMA_PORT. It can communicate directly with the AXI bus and transfer the data obtained from the DDR to the FFT_DMA_PORT. In the embodiment, the DMA obtains 256-bit data through the AXI bus and divides it into 4 64-bit floating-point numbers. During the data transmission process, the DMA does not rely on the control of the CPU, but directly transmits data, which improves the efficiency of data processing. The DMA also cooperates with the handshake signal control unit to dynamically adjust the ack signal to achieve the suspension and resumption of data transmission, especially during the zero-filling operation, which can ensure the order and accuracy of data transmission;

[0044] FFT_DMA_PORT is the module responsible for transferring the data from DMA to SRAM. Its main function is to map each 64-bit floating-point number in the 256-bit data to an independent storage address in SRAM according to the index-address conversion rule. FFT_DMA_PORT, combined with a conflict-free memory access controller, can generate storage addresses in real time after receiving data to ensure that there are no address conflicts when the data is stored. By using a hash algorithm or linear mapping, FFT_DMA_PORT can allocate data to different storage units in SRAM. In addition, FFT_DMA_PORT is also responsible for zero-padding operations. When the data is less than 2 to the power of n, it will perform zero-padding operations during data transmission;

[0045] exist Figure 2 In the figure, four independent SRAM storage banks (a, b, c, d) are shown. Each bank represents a storage area in the SRAM, which is used to store the data required for the FFT algorithm. Under the control of FFT_DMA_PORT, the data is allocated to different storage banks according to the index rule to ensure that the data can be stored without conflict. In the embodiment, each bank is responsible for storing the transmitted 64-bit data block, and FFT_DMA_PORT evenly distributes the data to these storage banks according to the index and batch of the data. In this way, storage resources can be effectively utilized to ensure efficient FFT calculation;

[0046] See also Figure 3 , the butterfly memory access storage space partition diagram of the embodiment of the present invention, the data in each BANK is arranged in a certain order, these storage areas are used to support the data allocation and storage of butterfly operations, in the butterfly memory access algorithm, data will be read or written from different BANKs according to specific rules to support the parallelism of FFT calculations, by dispersing data in multiple BANKs, data in multiple storage areas can be accessed at the same time, avoiding memory access conflicts, thereby improving data transmission efficiency, this partitioning method supports parallel transmission and processing of multiple batches of data. The data in each BANK can be read or written at the same time, making the entire memory access process more efficient;

[0047] The data transmission interface also includes a handshake signal control unit, which is used to suspend or resume DMA data transmission by controlling the pull-down and pull-up of the ack signal during the data transmission process. When a data zero padding operation is required, the ack signal is actively pulled down to suspend data transmission, and after the zero padding operation is completed, the ack signal is pulled up to resume data transmission.

[0048] The core function of the handshake signal control unit is to manage the data transmission rhythm of DMA by controlling the state of the ack signal. In each data transmission cycle, the unit dynamically adjusts the pull-down and pull-up states of the ack signal according to the current data transmission situation. It mainly includes the following functions:

[0049] The ack signal is used to identify whether data can continue to be transmitted. During normal data transmission, the ack signal remains high, and the DMA continues to transfer the data block to the SRAM after receiving the high-level signal. When data transmission needs to be suspended, such as for data zero padding or memory access adjustment, the ack signal will be pulled low.

[0050] Controlling the active pull-down and pull-up of ack requires consideration from two aspects

[0051] a. The amount of data determines when to pull down ACK. Since the scheme transmits 4 64-bit data in the next cycle, it is necessary to calculate the quotient of the data after modulo 4, that is, it can be determined in which cycle after the start of data transmission to start pulling down ACK. For example, 13-point data needs to be padded with zeros to 16 points, and the quotient of 13 modulo 4 is 3, that is, zero padding will be faced when the data starts to be transmitted for the fourth beat. Therefore, the ACK signal will be pulled low in this cycle, causing DMA to stop transmitting data. At the same time, fft_port continues to complete the zero padding operation internally; when it is about to reach 16 points, ACK will be pulled high, and DMA will continue to transmit the next data after receiving the ACK signal.

[0052] A register is needed to store the next batch of unused data in the zero filling process. For example, if there are 3 batches of 15 data, then in the last cycle of the first batch of data transmission, 13, 14, and 15 data need to be normally transferred to the SRAM array, and the first data of the second batch needs to be stored in the register, and when the ack is pulled high, it is combined with the 2nd, 3rd, and 4th data in the next wave of data transmission and then transferred to the SRAM array;

[0053] When the amount of transmitted data is not enough to meet the FFT algorithm's requirement that the number of data points is 2 to the power of 2, the ack signal will be actively pulled low, causing the DMA to temporarily stop data transmission. During this period, the data zero-filling module completes the zero-filling operation. After the zero-filling operation is completed, the ack signal is pulled high again, and the DMA resumes data transmission;

[0054] The handshake signal control unit can adjust the state of the ack signal in real time according to the amount of data transmitted and the need for zero padding. It determines when to pull down the ack signal for zero padding by monitoring the index and transmission status of the data in each cycle, and accurately resumes data transmission after zero padding. Each time data is transmitted, the control unit determines whether zero padding is required by detecting the size of the current data batch. Assuming that the current batch of transmitted data is 13 points, and the FFT algorithm requires 16 points of input, the zero padding algorithm will be triggered;

[0055] The handshake signal control unit can adjust the data index in real time according to the zero-filling status. Even if the data flow is paused, the index will still advance according to the predetermined rules to ensure that the zero-filled data can be correctly mapped to the storage address in the SRAM.

[0056] The control unit can manage the zero-padding operation of multiple data channels at the same time, ensuring that the data streams of all channels can work together in high-bandwidth data transmission scenarios, avoiding the zero-padding operation of a single channel affecting the overall data throughput;

[0057] See also Figure 4 , the workflow diagram of the butterfly memory access controller of the embodiment of the present invention, the controller first determines whether the number of data points meets the requirements of the FFT algorithm, and performs a zero-filling operation if it is insufficient. After the conditions are met, the controller selects a suitable BANK to transfer data from the SRAM to the computing unit to perform a butterfly operation. After the operation is completed, check again whether there is any remaining data. If so, repeat the BANK selection and transfer process until all data processing is completed, ensuring that data is efficiently and conflict-freely transmitted and calculated to support the needs of the FFT algorithm;

[0058] In the hardware implementation of the FFT algorithm, the data volume often does not meet the requirement of 2 to the power of n. The ack signal control mechanism of the handshake signal control unit enables the system to flexibly respond to the transmission requirements of different batches and data volumes, and complete the zero padding and correct transmission of the data without affecting the overall transmission efficiency.

[0059] Through this sophisticated ack signal control mechanism, the handshake signal control unit ensures the smoothness and efficiency of the entire data transmission process, especially in the case of complex zero padding and multi-batch data transmission, the system can maintain efficient and accurate operation;

[0060] The data transmission interface can complete the data transmission of multiple 64-bit floating-point numbers at the same time. In one data transmission cycle, the 256-bit data transmitted by DMA to SRAM is divided into four groups, each group corresponds to a 64-bit floating-point number, and the conflict-free storage of each floating-point number in SRAM is realized through the index-address conversion rule;

[0061] Based on the design of AXI bus, data is obtained from DDR memory through direct memory access (DMA) technology and transferred to on-chip memory (SRAM). In each data transmission cycle, the 256-bit data read by DMA from DDR will be divided into four groups, each group is 64 bits, representing a 64-bit single-precision floating point number. The data transmission interface packs the 256-bit data according to pre-defined rules. Each 64-bit floating point number is divided into independent data units and mapped to different storage addresses in SRAM through special index-address conversion rules. This operation ensures that each group of data can be stored in SRAM without address conflicts;

[0062] During the transmission process, each 64-bit floating point number is assigned a unique index value. The system maps the index value to the storage address in the SRAM through the index-address conversion rule to ensure that the transmitted data can be stored in different address spaces without conflict. The index rule is generated according to a predefined mapping algorithm, such as dynamic address allocation through a hash function or an incremental algorithm;

[0063] By transmitting four 64-bit floating-point numbers simultaneously in each data cycle, the data transmission interface effectively utilizes the bandwidth of the AXI bus and reduces the transmission time. Under the traditional transmission mechanism, only one 64-bit floating-point number can be transmitted in one cycle, but in this embodiment, four floating-point numbers can be transmitted in one cycle, which greatly improves the data transmission rate.

[0064] By using the index-address conversion rule, each floating-point number has an independent storage address, avoiding storage conflicts when multiple data are written to SRAM at the same time. This rule ensures that data can be accurately written to different storage units of SRAM even in a high-concurrency transmission environment.

[0065] The storage space of SRAM is more efficiently utilized. Through the mapping of index rules, data can be evenly distributed in each storage unit of SRAM, reducing the waste of storage space. Especially when processing large amounts of data, this storage optimization strategy can improve the overall efficiency of the system.

[0066] For example, when performing a 1024-point FFT calculation, 1024 64-bit floating-point numbers need to be transmitted. Through this parallel data transmission mechanism, the system can complete the transmission of all floating-point numbers within 256 cycles, while the traditional serial transmission mechanism requires 1024 cycles. This significant cycle reduction directly improves the overall computational efficiency of the FFT algorithm and is suitable for fields such as signal processing and image processing with high real-time requirements;

[0067] During the transmission process, each 64-bit floating point number is assigned a unique index value. The system maps the index value to the storage address in the SRAM through the index-address conversion rule to ensure that the transmitted data can be stored in different address spaces without conflict. The index rule is generated according to a predefined mapping algorithm, such as dynamic address allocation through a hash function or an incremental algorithm;

[0068] The handshake signal control unit dynamically calculates when to start pulling down the ack signal according to the amount of data transmission, so as to suspend data transmission and perform zero padding operation when necessary, and the calculation method is to determine the time point of pulling down the ack signal by the quotient of the data transmission amount modulo 4;

[0069] The zero-filling module further includes a register storage unit for temporarily storing unused data during the data zero-filling operation, and transmitting the unused data to the SRAM after being combined with subsequent data during the next data transmission;

[0070] The register storage unit is a multi-level register structure, and each level of register has a FIFO (first in, first out) mode, which is used to store unused data in the current cycle. During the zero-filling operation, if the amount of data to be transmitted is not enough to fill the 256-bit transmission width (for example, when transmitting 13 64-bit data, only 3 64-bit data are satisfied, and there is still 1 64-bit space), the multi-level register storage unit will be responsible for storing the remaining unused data into the corresponding register unit;

[0071] Each level of register has a capacity of 64 bits, which can automatically allocate and manage the storage of unused data according to the amount of input data. This structure can support continuous zero-filling transmission of multiple batches of data, avoiding data loss caused by zero-filling during cross-batch data transmission;

[0072] When the zero-padding operation starts, the zero-padding detection unit first determines whether the amount of transmitted data is 2 to the power of n. If it is insufficient, the zero-padding process is immediately started.

[0073] When insufficient data (such as 15 64-bit data) is transmitted and cannot fill a complete transmission cycle (256 bits), the register storage unit temporarily stores the excess data in the FIFO structure.

[0074] In the next cycle of data transmission, the data in the register will be merged with the subsequent data to ensure that the transmission width of each cycle is always 256 bits. The storage time of the untransmitted data in the register does not exceed one data transmission cycle to avoid the impact of data retention on the overall transmission process;

[0075] The register storage unit is linked with the handshake signal control unit and the zero padding control unit. When the data is not used, the handshake signal control unit will suspend the DMA transmission to prevent data overflow or transmission error. At this time, the register storage unit will receive and store the data that is not used in the current cycle. Through the control logic inside the register, these unused data are temporarily stored until the next data transmission cycle.

[0076] During the next data transfer, the register control logic will automatically combine the stored data with the new batch of data through index matching, and form a complete 256-bit data packet and transfer it to the SRAM;

[0077] When the transmission batch is a plurality of batches of data that is not a power of 2, the register storage unit can store unused data at the end of the previous batch of data transmission cycles.

[0078] Assume that the amount of data in the transmission batch is 13 64-bit data, and the amount of data required by the FFT algorithm is 16 64-bit data. Therefore, three zero points need to be added after the last three data:

[0079] Step 1: When the data is transferred to the 12th data, the register storage unit enters the activated state and prepares to transfer the three data 13, 14, and 15 to the SRAM, but the 16th data is not in place yet, so a zero-filling operation is required.

[0080] Step 2: The handshake signal control unit actively pulls down the ack signal to suspend data transmission. The zero-filling control unit calculates and generates 3 zero-filling data, and the register storage unit temporarily stores the unused 13th data.

[0081] Step 3: When the next transmission cycle starts, the ack signal is restored, and the register storage unit combines the 13th data with the new data (the subsequent new data may be the first data of the next batch) to form a complete 256-bit data packet and continue to transmit it to the SRAM;

[0082] The index-address conversion rule generates a unique storage address corresponding to each data in real time according to the batch of data transmission and the storage location in the SRAM. The index address conversion rule is as follows:

[0083]

[0084] During the data transmission process, the index-address conversion rule is used to convert the index value of each data block into a unique storage address in the SRAM to ensure that the data is stored in the SRAM without conflict. Specifically, the data transmission interface obtains 256 bits of data from the DDR each time, and divides it into four 64-bit data blocks. Each data block is accompanied by a unique index value. The index value consists of the data transmission batch number and the sequential number of the data in the batch;

[0085] The index generator generates the corresponding index value in real time and converts it into an address in the SRAM through an index mapping algorithm.

[0086] After receiving the 256-bit data transmitted from the DDR, the data transmission interface can immediately transfer the data to a specific location in the SRAM according to the index rule, and ensure that there is no address conflict during the transmission process through the internal address conversion logic;

[0087] The data transmission interface is responsible for obtaining data from DDR and transmitting it to SRAM through the AXI bus. Each 256-bit data block transmitted will be divided into four 64-bit floating-point numbers and stored in different locations of SRAM according to the index rules. The data transmission interface has parallel processing capabilities and can process the transmission of multiple data blocks at the same time to improve transmission efficiency. The data transmission interface supports multi-channel parallel transmission and can transmit four 64-bit data blocks simultaneously in each cycle, shortening data transmission delays.

[0088] For each transmission cycle, the data in the data queue is taken out and transferred to the SRAM in the order of the index. Since the amount of data transmitted in each cycle is 256 bits, and the AXI bus supports multi-channel transmission, the scheduler will allocate the data in the data queue to different transmission channels to achieve parallel transmission;

[0089] The handshake signal control unit dynamically adjusts the pull-up or pull-down of the ack signal according to the current data transmission amount and the zero padding requirement to ensure that the data transmission of the DMA does not affect the data storage in the SRAM when the data zero padding operation is performed;

[0090] The handshake signal control unit is responsible for controlling the data transmission synchronization between DMA and SRAM. By dynamically adjusting the state of the ack signal (pulling low or high), the data transmission can be paused and resumed. This unit is mainly used in the process of data zero filling to ensure that the data transmission can proceed in an orderly manner after the zero filling operation is completed;

[0091] The data transmission interface is suitable for processing FFT data sets of different numbers of points, including data sets of 2n and non-2n, and can automatically perform data zero padding operations according to the size of the data set to meet the requirements of the FFT algorithm for data of a specific number of points;

[0092] The FFT algorithm usually requires the input data point number to be a power of 2, but the number of points of the data set actually transmitted may not be a power of 2. Therefore, the data transmission interface needs to be able to handle data sets with different point numbers, especially when the number of points is insufficient, it needs to automatically perform zero padding;

[0093] For example, for a 15-point data set, the system will automatically determine that the number of data points is insufficient, start the zero-padding module, and pad the data to 16 points. The register temporarily stores the unused 16th point data, and after the zero-padding is completed, it is transferred to the SRAM together with the zero-padding data. The zero-padding data set will meet the input requirements of the FFT algorithm and will not affect the integrity of the original data.

[0094] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A data transmission path suitable for FFT algorithm, characterized in that: The data transmission path obtains source data from the DDR memory through the AXI bus and transmits it to the DMA, and distributes the data to the SRAM array through the fft_port, including: AXI bus, used to transfer data between DDR memory and DMA; A data transfer interface is used to obtain bus data from DMA through direct memory access technology and transfer the data to the SRAM array. The data is a 64-bit single-precision floating point number, and the data width transmitted in each cycle is 256 bits. A conflict-free memory access controller, the controller comprising an index-address conversion rule, for mapping each 64-bit data in the received 256-bit data to an independent storage address of the SRAM according to the index conversion rule; The data zero-filling module is used to fill the insufficient data with zeros to the power of 2 before transmitting it to the SRAM when the amount of data to be transmitted does not meet the requirements of the FFT algorithm.

2. A data transmission path suitable for FFT algorithm according to claim 1, characterized in that: The data transmission interface also includes a handshake signal control unit, which is used to suspend or resume DMA data transmission by controlling the pulling down and pulling up of the ack signal during the data transmission process. When a data zero padding operation needs to be performed, the ack signal is actively pulled down to suspend data transmission, and after the zero padding operation is completed, the ack signal is pulled up to resume data transmission.

3. A data transmission path suitable for FFT algorithm according to claim 1, characterized in that: The data transmission interface can complete the data transmission of multiple 64-bit floating-point numbers at the same time. In one data transmission cycle, the 256-bit data transmitted by DMA to SRAM is divided into four groups, each group corresponds to a 64-bit floating-point number, and the conflict-free storage of each floating-point number in SRAM is achieved through the index-address conversion rule.

4. A data transmission path suitable for FFT algorithm according to claim 2, characterized in that: The handshake signal control unit dynamically calculates when to start pulling down the ack signal according to the amount of data transmission, so as to suspend data transmission and perform zero padding when necessary. The calculation method is to determine the time point of pulling down the ack signal by the quotient of the data transmission modulo 4.

5. A data transmission path suitable for FFT algorithm according to claim 1, characterized in that: The zero-filling module further includes a register storage unit, which is used to temporarily store unused data during the data zero-filling operation, and transmit it to the SRAM after being combined with subsequent data during the next data transmission.

6. A data transmission path suitable for FFT algorithm according to claim 5, characterized in that: When the transmission batch is a plurality of batches of data that is not a power of 2, the register storage unit can store unused data at the end of the previous batch of data transmission cycles.

7. A data transmission path suitable for FFT algorithm according to claim 1, characterized in that: The index-address conversion rule generates a unique storage address corresponding to each data in real time according to the batch of data transmission and the storage location in the SRAM.

8. A data transmission path suitable for FFT algorithm according to claim 1, characterized in that: After receiving the 256-bit data transmitted from the DDR, the data transmission interface can immediately transfer the data to a specific location in the SRAM according to the index rule, and ensure that there is no address conflict during the transmission process through the internal address conversion logic.

9. A data transmission path suitable for FFT algorithm according to claim 2, characterized in that: The handshake signal control unit dynamically adjusts the pull-up or pull-down of the ack signal according to the current data transmission amount and the zero-filling requirement to ensure that the data transmission of the DMA will not affect the data storage in the SRAM when the data zero-filling operation is performed.

10. A data transmission path suitable for FFT algorithm according to claim 1, characterized in that: The data transmission interface is suitable for processing FFT data sets of different number of points, including data sets of 2 to the power of n and non-2 to the power of n, and can automatically perform data zero padding operations according to the size of the data set to meet the requirements of the FFT algorithm for data of a specific number of points.

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