Three-dimensional reconfigurable hardware acceleration core chip

Abstract

The invention discloses a three-dimensional reconfigurable hardware acceleration core chip, belongs to the technical field of chips, and is characterized in that the three-dimensional reconfigurable hardware acceleration core chip comprises a reconfigurable operation array used for providing at least one unit-level calculation unit and at least one algorithm-level calculation unit; the storage array is used for storing operation data input by the AXI bus and output by the reconfigurable operation array; the controller set is used for controlling the at least one cell-level computing unit and the at least one algorithm-level computing unit so as to achieve cell-level computing operation and algorithm-level computing operation respectively and controlling operation data storage of the storage array. The three-dimensional reconfigurable hardware acceleration core chip based on static scheduling and a static data flow model is constructed by managing scheduling functions such as configuration decoding, reconfiguration control, calculation control, data distribution and storage control through an independent control system, and the chip realizes multi-dimensional reconfiguration of a space dimension, a time dimension and a resource dimension through storage and calculation decoupling.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and more specifically to a three-dimensional reconfigurable hardware acceleration core chip. Background Art

[0002] DSP algorithms are used in communication systems for modulation and demodulation, signal encoding and decoding, and error correction, improving the efficiency and reliability of communication; in audio processing, they are used for noise reduction, echo cancellation, and sound enhancement, and are widely used in audio systems and speech recognition equipment; in image processing, these algorithms support image filtering, edge detection, and image compression, and are used in digital cameras, video surveillance, and medical image analysis; radar and sonar systems rely on DSP algorithms for target detection and tracking to improve accuracy and resolution; in medical equipment, DSP algorithms are used for medical imaging and electrocardiogram analysis to achieve high-precision diagnosis and real-time monitoring; in automatic control systems, they help achieve real-time control and signal analysis. DSP chips play a vital role in these applications. They are designed for efficient processing of digital signals, can perform complex operations at extremely high speeds, have dedicated computing units such as multipliers and cyclic shifters, optimize power consumption, and are usually programmable, allowing processing algorithms to be adjusted as needed. This integrated design simplifies system design, reduces cost and complexity, and makes DSP chips a core component in modern electronic systems.

[0003] For example, the Chinese invention patent with authorization announcement number CN114185599A provides a computing system based on a DSP chip array. The DSP chip array and array support unit connected by hardware links support parallel computing, greatly improves the computing power of module-level computing units, starts loading faster, and effectively reduces hardware costs.

[0004] However, the above patents are similar to traditional DSP chips, which usually use fixed hardware architectures and preset computing units, and are optimized specifically for specific types of computing tasks. Although this dedicated architecture can provide high performance when processing specific algorithms, it is difficult to adapt to changing application requirements and algorithm upgrades. With the diversification of application scenarios and the continuous evolution of computing needs, fixed hardware architectures often cannot meet new algorithm requirements or performance optimization needs. Especially when processing complex and diverse digital signal processing algorithms, such as fast Fourier transform (FFT), finite impulse response (FIR) filters, autocorrelation, cross-correlation, and various matrix operations, the existing DSP chips have low resource utilization and low design efficiency, so the existing technology has shortcomings. Summary of the invention

[0005] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a three-dimensional reconfigurable hardware acceleration core chip that can realize multi-dimensional on-chip reconfiguration in spatial dimension, temporal dimension and resource dimension, and complete the efficient mapping and deployment of signal processing algorithms in a data flow driven manner, while reducing the design complexity of data and control paths, thereby effectively reducing the difficulty of physical implementation.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A three-dimensional reconfigurable hardware acceleration core chip, the three-dimensional reconfigurable hardware acceleration core chip comprising: a reconfigurable computing array, a storage array and a controller set;

[0008] The reconfigurable computing array is used to provide at least one unit-level computing unit and at least one algorithm-level computing unit;

[0009] The storage array is used to store operation data input via the AXI bus and output by the reconfigurable operation array;

[0010] The controller set is used to control the at least one unit-level computing unit and the at least one algorithm-level computing unit to respectively implement unit-level computing operations and algorithm-level computing operations, and to control the storage of computing data of the storage array.

[0011] As a further improvement of the present invention, the controller set includes: a DSP scheduler, a computing resource controller, a memory access resource controller, and a DMA resource controller;

[0012] The computing resource controller is used to schedule and control the reconfigurable computing array;

[0013] The memory access resource controller is used to control data scheduling between the storage array and the reconfigurable computing array;

[0014] The DMA resource controller is used to control the data transfer between the storage array and the AXI bus;

[0015] The DSP scheduler is used to control the reconstruction mode and operation status of the computing resource controller, the memory access resource controller and the DMA resource controller.

[0016] As a further improvement of the present invention, the computing resource controller includes an input and output buffer, a computing resource decoder, a first register module and a first reconstruction state machine module;

[0017] The input and output buffer is used to cache the output data of the memory access resource controller and the reconfigurable operation array;

[0018] The computing resource decoder is used to decode the control instructions sent by the DSP scheduler;

[0019] The first register module is used to store the reconstruction information of the computing resource controller;

[0020] The first reconfiguration state machine module is used to control the operation process of the reconfigurable operation array.

[0021] As a further improvement of the present invention, the memory access resource controller includes: a data buffer module, a second reconstruction state machine module, a second register module and a sub-controller;

[0022] The data buffer module is used to cache the output data of the DMA resource controller and the computing resource controller;

[0023] The second reconstruction state machine module is used to control the reconstruction process of the sub-controller;

[0024] The second register module is used to store the reconstruction information of the memory access resource controller;

[0025] The sub-controller includes a plurality of unit-level memory access controllers and a plurality of algorithm-level memory access controllers, each of the unit-level memory access controllers corresponds to a unit-level memory access mode, and each of the algorithm-level memory access controllers corresponds to an algorithm-level memory access mode.

[0026] As a further improvement of the present invention, the DMA resource controller includes: a DMA module, a logic control module, a data configuration module and a DMA_Port;

[0027] The DMA module comprises a first status register, wherein the first status register is used to store the working status of the DMA module;

[0028] The logic control module is used to control the state machine jump, the state machine is used to control the data handling process of the DMA module, and the state machine is composed of the first state register and a combinational logic circuit;

[0029] The data configuration module is used to store the configuration information of the DMA module and use the configuration information to configure the DMA module;

[0030] The DMA_Port is used for data transmission between the DMA module and the device's built-in memory.

[0031] As a further improvement of the present invention, the DSP controller includes: a buffer area, a decoder, a configuration circuit module, a register group, a FSM state machine and a transmitter;

[0032] The buffer is used to cache instructions sent on the AXI bus;

[0033] The decoder is used to decode the instructions received by the three-dimensional reconfigurable hardware acceleration core;

[0034] The configuration circuit module includes a read configuration circuit, a write configuration circuit and an interface circuit.

[0035] As a further improvement of the present invention, the register group includes a device register, a configuration register and a second status register;

[0036] The device register is used to store the response mode information and the working mode information of the three-dimensional reconfigurable hardware acceleration core chip;

[0037] The configuration register is used to store configuration information of the memory access resource controller and the DMA resource controller;

[0038] The second status register is used to store the running status information of the controller set.

[0039] As a further improvement of the present invention, the FSM state machine is used to manage the register group, manage storage permissions, manage calculation sequences and detect data correlation.

[0040] As a further improvement of the present invention, the transmitter includes a LEN instruction counter unit and a path selection unit;

[0041] The LEN instruction counter unit is used to record the number of instructions sent by the device register, identify the address of the instruction, and send the address to the DSP scheduler;

[0042] The path selection unit is used to select a distribution path for the configuration information of the configuration register, or a receiving path for the status information of the status register.

[0043] The present invention provides an algorithm task reconstruction method, which is applied to the above-mentioned three-dimensional reconfigurable hardware acceleration core chip, and is characterized in that the algorithm task reconstruction method comprises:

[0044] The three-dimensional reconfigurable hardware acceleration core chip receives the device configuration information sent by the management core chip, and writes the device configuration information into the configuration register;

[0045] Each controller in the controller set completes configuration according to the device configuration information and realizes reconstruction of the algorithm task.

[0046] As a further improvement of the present invention, if the three-dimensional reconfigurable hardware acceleration core chip is the main processing device of the algorithm task, the three-dimensional reconfigurable hardware acceleration core chip receives the device configuration information sent by the management core chip and writes the device configuration information into the configuration register, including:

[0047] The three-dimensional reconfigurable hardware acceleration core chip obtains the device configuration information by polling the control command area in the double-rate synchronous dynamic random access memory, and writes the device configuration information into the configuration register. The device configuration information is written into the control command area of ​​the double-rate synchronous dynamic random access memory by the management core chip through a cross switch matrix.

[0048] As a further improvement of the present invention, if the three-dimensional reconfigurable hardware acceleration core chip is a slave processing device of the algorithm task, the three-dimensional reconfigurable hardware acceleration core chip receives the device configuration information sent by the management core chip and writes the device configuration information into the configuration register, including:

[0049] The three-dimensional reconfigurable hardware acceleration core chip receives the device configuration information sent by the management core chip through the crossbar switch matrix, and writes the device configuration information into the configuration register in sequence.

[0050] The present invention provides a processing device equipped with the management core chip and the three-dimensional reconfigurable hardware acceleration core chip.

[0051] The present invention dynamically configures multiple computing units through a reconfigurable computing array, so that the computing array can adapt to different digital signal processing tasks without designing dedicated hardware for each task. Users can also configure computing units according to specific application requirements, optimize computing performance and improve resource utilization, thereby achieving efficient processing of multiple DSP algorithms. Therefore, the present invention can overcome the shortcomings of traditional DSP chips in terms of flexibility and achieve wider applications and higher computing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 This is the overall architecture diagram of the three-dimensional reconfigurable hardware acceleration core chip;

[0053] Figure 2 It is the structural diagram of DSP scheduling controller;

[0054] Figure 3 Main state machine state jump diagram;

[0055] Figure 4 Refactor implementation flow charts for algorithmic tasks. DETAILED DESCRIPTION

[0056] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations of the technical solution of the present invention.

[0057] The term "and / or" in the following text is only a description of the association relationship between the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0058] like Figure 1 As shown, a three-dimensional reconfigurable hardware acceleration core chip according to an embodiment of the present application includes: a reconfigurable computing array, a storage array, and a controller set;

[0059] The reconfigurable computing array is used to provide at least one unit-level computing unit and at least one algorithm-level computing unit;

[0060] The storage array is used to store the operation data input through the AXI bus and output from the reconfigurable operation array;

[0061] The controller set is used to control at least one unit-level computing unit and at least one algorithm-level computing unit to respectively implement unit-level computing operations and algorithm-level computing operations, and to control the storage of computational data in the storage array.

[0062] Specifically, the reconfigurable computing array, namely the PE array, is divided into two types: single-precision PE array and double-precision PE array. The single-precision PE array consists of two multifunctional arithmetic computing units (1 / 2PE) with independent data paths and a multiplication-add bypass array outside the PE. The 1 / 2PE can realize reconstruction within the PE and reconstruction between PEs by connecting the multiplication-add bypass outside the PE. Each independent 1 / 2PE computing unit includes 8 multiplication-accumulation structures and 1 comparator, wherein the multiplication-accumulation structure includes 1 complex multiplier and 2 multiplexers, the comparator array includes 8 comparators, and the PE external multiplication-addition bypass is composed of 4 multiplexers, 2 complex multipliers, 1 SQRT and a register group, that is, the final computing resources of the single-precision PE array are composed of 18 complex multipliers, 36 multiplexers, 16 comparators and 1 sqrt computing unit; the double-precision PE array is an algorithm-level computing unit, which is used solely for the double-precision matrix inversion algorithm through algorithm-level reconstruction. Its final computing resources are composed of 8 double-precision complex adders, 2 double-precision complex multipliers, 1 double-precision comparator, and 1 double-precision division unit.

[0063] The storage array is composed of sram_array and rom_array, and its function is to store the data and results required for each algorithm operation. sram_array is composed of 64 bank submodules, with a total storage of 2MB. Its bit width can support 8 / 16 / 32 / 64 / 128 / 256 bits, and has two independent ports, one port is read-only and the other port is write-only. The ROM array is composed of 16 ROMs with a capacity of 8KB, and its interface bit width is fixed at 64bit (ROM frequency 1Ghz). Each bank module is composed of 4 2-port SRAM_1024×64bit to form 32KB storage, and through internal logic control, it can realize the reading and writing of data with different data bit widths. Each group of signals connected to BANK includes clock signal clk, chip select signal bce, write mode configuration bwmod, read-write signal bwren, write address signal bwaddr, write data signal bwdata, read mode configuration brmod, read address signal bradr, read data signal brdata, etc.

[0064] The embodiment of the present application dynamically configures multiple computing units through a reconfigurable computing array, so that the computing array can adapt to different digital signal processing tasks, thereby enabling the hardware chip to be adjusted in real time according to different algorithm requirements without the need to design dedicated hardware for each task.

[0065] Further, the controller set includes: a DSP scheduler, a computing resource controller, a memory access resource controller, and a DMA resource controller;

[0066] The computing resource controller is used for scheduling and controlling the reconfigurable computing array;

[0067] The memory access resource controller is used to control the data scheduling between the storage array and the reconfigurable computing array;

[0068] The DMA resource controller is used to control the data transfer between the storage array and the AXI bus;

[0069] The DSP scheduler is used to control the reconstruction mode and operation status of the computing resource controller, the memory access resource controller and the DMA resource controller.

[0070] The computing resource controller includes an input and output buffer, a computing resource decoder, a first register module and a first reconstruction state machine module;

[0071] The input and output buffer is used to cache the output data of the memory resource controller and the reconfigurable operation array;

[0072] The computing resource decoder is used to decode the control instructions sent by the DSP scheduler;

[0073] The first register module is used to store the reconstruction information of the computing resource controller;

[0074] The first reconfiguration state machine module is used to control the operation process of the reconfigurable operation array.

[0075] The output data of the memory access resource controller is used as the input data of the computing resource controller, the output data of the reconfigurable computing array is used as the output data of the computing resource controller, and the reconstruction information of the computing resource controller includes data format, computing resource type and computing resource interconnection method, etc.

[0076] Specifically, the computing resource controller is responsible for allocating computing resources, controlling the execution order and timing of computing modules, and managing and scheduling reconfigurable computing arrays. It can control the reconstruction and interconnection modes of multiple computing resources. The three-dimensional reconfigurable acceleration core contains more than ten unit-level computing modes, including: (real / complex) multiplication, (real / complex) addition, (real / complex) subtraction, (complex) conjugate operation, (complex) conjugate accumulation tree, butterfly unit, (real / complex) multiplication-accumulation tree, (real / complex) accumulation tree, (real / complex) mean accumulation tree, (complex) conjugate multiplication, (real) comparison, (real) comparison tree, (complex) multiplication-accumulation, (complex) conjugate multiplication-addition tree, (complex) multiplication-addition operation, etc.; and four algorithm-level computing modes, namely: butterfly operation, double-precision multiplication-addition operation, double-precision division operation, double-precision comparison operation.

[0077] The memory access resource controller includes: a data buffer module, a second reconstruction state machine module, a second register module and a sub-controller;

[0078] The data buffer module is used to cache the output data of the DMA resource controller and the computing resource controller;

[0079] The second reconstruction state machine module is used to control the reconstruction process of the sub-controller;

[0080] The second register module is used to store the reconstruction information of the memory access resource controller;

[0081] The sub-controller includes a plurality of unit-level memory access controllers and a plurality of algorithm-level memory access controllers, each unit-level memory access controller corresponds to a unit-level memory access mode, and each algorithm-level memory access controller corresponds to an algorithm-level memory access mode.

[0082] The output data of the DMA resource controller, that is, the output data of the DMA_Port, is used as the input data of the memory access resource controller, and the output data of the computing resource controller is used as the output data of the memory access resource controller. The second reconstruction state machine module is also used to allocate the bank cluster space and the interface of the data buffer. The reconstruction information of the memory access resource controller includes the memory access resource type, the bank cluster division strategy and the bank cluster intra-ping pong strategy.

[0083] Specifically, the memory resource controller is responsible for efficiently distributing data, managing read and write timing control, and completing data scheduling between the storage array and the reconfigurable computing array to ensure effective data transmission. It contains four unit-level memory controllers: sliding window memory controller supporting DSP algorithms, vector memory controller, two-dimensional memory controller, and sorting memory controller. And two algorithm-level memory controllers: butterfly memory controller, single-precision matrix inversion memory controller, and double-precision matrix inversion memory controller.

[0084] The DMA resource controller includes: a DMA module, a logic control module, a data configuration module and a DMA_Port;

[0085] The DMA module includes a first status register, and the first status register is used to store the working status of the DMA module;

[0086] The logic control module is used to control the state machine jump, and the state machine is used to control the data handling process of the DMA module. The state machine is composed of a first state register and a combinational logic circuit;

[0087] The data configuration module is used to store the configuration information of the DMA module and use the configuration information to configure the DMA module;

[0088] DMA_Port is used for data transfer between the DMA module and the device's built-in memory.

[0089] The data transfer process of the DMA module specifically includes dividing data blocks, setting data transfer dimensions, controlling outstanding and controlling burst length, etc. The configuration information of the DMA module includes data address segment, data dimension and data length, etc. In the three-dimensional reconfigurable hardware acceleration core architecture, the device built-in memory is SRAM (static ram, static random access memory).

[0090] Specifically, the DMA resource controller includes a DMA module, which performs data transmission through an AXI bus interface and implements the following main functions: each DMA supports 2 channels; configures register request transmission and hardware request transmission; supports read, write, read and write, frame transmission, and multi-block data transmission; supports interrupts and error interrupts; supports pause and cancel of DMA transmission; each DMA channel supports at least 16 outstanding numbers; uses physical addresses; each channel contains a 16KB buffer, and a total of 32KB buffer; supports more than ten data transfer modes; supports configuration and data transfer.

[0091] like Figure 2As shown, the DSP scheduler includes: a buffer area, a decoder, a configuration circuit module, a register group, a FSM state machine and a transmitter;

[0092] The buffer is used to cache the instructions sent on the AXI bus;

[0093] The decoder is used for decoding the instructions received by the three-dimensional reconfigurable hardware acceleration core;

[0094] The configuration circuit module includes a read configuration circuit, a write configuration circuit and an interface circuit.

[0095] The register group includes a device register, a configuration register and a second status register;

[0096] The device register is used to store the response mode information and the working mode information of the three-dimensional reconfigurable hardware acceleration core chip;

[0097] The configuration register is used to store configuration information of the memory access resource controller and the DMA resource controller;

[0098] The second status register is used to store the operation status information of the controller set.

[0099] The FSM state machine is used to manage register groups, manage storage permissions, manage calculation sequences, and detect data dependencies.

[0100] The transmitter includes a LEN instruction counter unit and a path selection unit;

[0101] The LEN instruction counter unit is used to record the number of instructions sent by the device register, identify the address of the instruction, and send the address to the DSP scheduler;

[0102] The path selection unit is used to select a distribution path for configuration information of the configuration register or a receiving path for status information of the status register.

[0103] Specifically, the DSP scheduler is responsible for decoding configuration information, supervising and controlling the reconstruction mode and operation status of each submodule. It contains a register group, a finite state machine, a program counter, a decoder and a buffer. Among them, the register group includes: device registers responsible for controlling the response mode and working mode of the acceleration core; configuration registers responsible for storing parameters such as the starting address, memory access type, operation type, data length, and number of operation points; main mode registers responsible for controlling the program operation in the main mode; status registers responsible for characterizing the operation status of submodule controllers such as the memory access resource controller and the computing resource controller; and abnormal status registers indicating abnormal calculations.

[0104] Furthermore, the DSP scheduling controller is also used to execute the operation control of the acceleration core. If the acceleration core is currently idle, the scheduling controller reads out the relevant information in the configuration register, such as the starting address, data length, and operation points, and writes them into the DMA internal register and the reconfigurable control unit internal register respectively, starts DMA to carry out data transfer, and notifies the operation array to perform the specified operation. After the operation array completes the operation, it notifies the scheduling controller, and the scheduling controller performs the next control scheduling.

[0105] The FSM main state machine is used to control the signal processing algorithm. When the acceleration core is in the startup state, the corresponding state machine is selected and started according to the executed algorithm. When the acceleration core is started, the main state machine is in the IDLE state. The state machine jump process is as follows: Figure 3 The meanings of each status are as follows:

[0106] IDLE: If the configuration information is valid, the configuration information is read in and the system enters the READY state. If the configuration register is invalid, the master controller sends an acceleration core idle flag to the DSP and keeps IDLE. The submodule enable signals are all in the reset state.

[0107] READY: Analyze the operation type in the configuration information. If it is an illegal operation type (that is, an undefined operation type), an error is reported, the err of the status register becomes 4'b1111, and the state machine returns to the IDLE state; if the operation type is legal, it is decoded and enters the CONFIG_READY state.

[0108] CONFIG_READY: The master pulls up the DMA resource controller enable (only indicates data transfer start), memory access controller enable and computing resource controller enable, waits for the configuration completion signal to return, and enters the SRC_TRANS state. Otherwise, keep the CONFIG_READY state

[0109] SRC_TRANS: If there is no need to continue to transfer the source data (the source data transfer completion signal is pulled high, or the source data transfer is skipped and the DMA resource controller pulls up the source data transfer completion signal), jump to the CALCULATE_READY state, otherwise maintain the SRC_TRANS state.

[0110] CALCULATE_READY: The master queries the memory access resource status register. If the memory access resource controller is idle, it jumps to the CALCULATE state and generates a cal_strat signal. Otherwise, it maintains the CALCULATE_READY state.

[0111] CALCULATE: The master queries the memory access resource status register. If the memory access resource controller is idle and the calculation completion flag is pulled high, it jumps into the RESULT_TRANS state, otherwise, it maintains the CALCULATE state.

[0112] RESULT_TRANS: If there is no need to continue to transfer the result data (the result data transfer is completed, or the result data transfer is skipped and the DMA resource controller pulls up the result data transfer completion signal), jump to the RESULT_TRANS_FINSH state, otherwise maintain CALCULATE_FINISH.

[0113] RESULT_TRANS_FINSH: The master checks whether the next configuration register in slave mode is valid or whether it is the last one in master mode. If it is valid, it jumps into the MASTER_TRANS state and continues the next batch of configuration decoding. If it is invalid, it writes the DONE signal to the master status register, the master returns to the IDLE state, and generates an interrupt signal to the CPU.

[0114] Furthermore, the three-dimensional reconfigurable hardware acceleration core chip provided in this embodiment also includes an AXI interface, and the AXI interface uses DW_axi_gsIP in the DesignWare synthesizable device group of Synopsis. This IP provides a simple method for third parties to connect to the AMBA AXI bus. They use simplified interfaces to reduce the design complexity of third-party controllers required when third parties connect to the AXI bus.

[0115] The three-dimensional reconfigurable hardware acceleration core chip provided in this embodiment forms a reconfigurable acceleration architecture that implements static scheduling and static data flow models through independent configuration decoding, reconstruction control, computing control, data distribution and storage control scheduling systems. This architecture realizes multi-dimensional reconfigurable technology in spatial dimensions, temporal dimensions, and resource dimensions through storage and computing decoupling.

[0116] Further, such as Figure 4 As shown, an algorithm task reconstruction method according to an embodiment of the present application is applied to the above-mentioned three-dimensional reconfigurable hardware acceleration core chip, including:

[0117] The three-dimensional reconfigurable hardware acceleration core chip receives the device configuration information sent by the management core chip, and writes the device configuration information into the configuration register;

[0118] Each controller in the controller set completes the configuration according to the device configuration information and realizes the reconstruction of the algorithm task.

[0119] Among them, if the three-dimensional reconfigurable hardware acceleration core chip is the main processing device of the algorithm task, the three-dimensional reconfigurable hardware acceleration core chip obtains the device configuration information by polling the control command area in the double-rate synchronous dynamic random access memory, and writes the device configuration information into the configuration register, wherein the device configuration information is written into the control command area of ​​the double-rate synchronous dynamic random access memory by the management core chip through the cross switch matrix.

[0120] If the three-dimensional reconfigurable hardware acceleration core chip is a slave processing device for the algorithm task, the three-dimensional reconfigurable hardware acceleration core chip receives the device configuration information sent by the management core chip through the cross switch matrix, and writes the device configuration information into the configuration register in sequence.

[0121] Specifically, when the acceleration core is used as the master device, the management core needs to compile and generate configuration information in advance, and the management core writes the configuration information into the control command area of ​​DDR through L3 Cache via CrossBar (cross switch matrix). The acceleration core obtains the configuration information by polling the control command area in DDR (double rate synchronous dynamic random access memory), and writes one or more batches of configuration information into the configuration register in the core. In the master mode, the three-dimensional reconfigurable acceleration core has a configuration register containing 512-bit configuration information. When the configuration information is transferred, the DMA resource controller waits for the next command from the master. At this time, the decoder in the core decodes the configuration information and starts the configuration of the DMA resource controller, memory access resource controller, and computing resource controller. When all configuration completion signals in the status register are pulled high, the acceleration core starts the operation, and the DMA resource controller starts data transfer according to the configuration information. After the first batch of data transfer is completed, the DMA resource controller writes the (first batch) data transfer completion signal to the status register, and the computing resource controller and the memory access resource controller are started, and the calculation begins. When the unit-level operation is completed, the unit-level memory access controller writes the result data transfer signal to the status register. After the DMA resource controller queries the status register, it transfers the calculation result to the DDR. After the current result data transfer is completed, if it is not the last batch of main mode configuration information, the main control will send the configuration transfer task to the DMA resource controller again. The DMA continues to obtain the next batch of configuration information by polling the control command area in the DDR until the last batch of configuration operations in the main mode are completed, and the main control sends an interrupt request to the CPU.

[0122] When the speed core is used as a slave device, the management core can write the generated configuration information into the configuration register in the core in sequence through CrossBar. In slave mode, the 3D reconfigurable acceleration core has four configuration registers, each of which contains 512-bit configuration information. The acceleration core master will execute valid configurations in sequence until all configurations are executed, thereby realizing the configuration and calculation of the acceleration core in slave mode.

[0123] The three-dimensional reconfigurable hardware acceleration core chip provided in this embodiment adopts a three-dimensional reconfigurable hardware acceleration core architecture, supports unit-level reconstruction mode when executing different algorithms, and realizes rapid reconstruction of algorithm-level tasks through a combination of reconfigurable operation and memory access modes.

[0124] The existing RASP architecture adopts the control mode of the algorithm reconstruction controller, and realizes specific algorithm functions and uses by selecting different algorithm controllers. Different from the prior art, the three-dimensional reconfigurable chip provided in this embodiment adopts a three-dimensional reconfigurable hardware acceleration core architecture, decouples the computing reconstruction control from the data access control through the control mode of storage and computing decoupling, and realizes specific algorithm functions and uses through the cross-combination of different computing resources and memory access resources.

[0125] Specifically, the DSP scheduling controller offloads the past data flow control tasks to the sub-controllers, which are divided into: 1) a computing resource controller responsible for computing resource allocation and computing timing control; 2) a memory access resource controller responsible for efficient data distribution and read and write timing control; 3) a DMA resource controller responsible for data storage location and transport strategy control.

[0126] All modules complete unified information exchange through the register group, which includes device registers, configuration registers, status registers, etc. The configuration register is used to implement reconstruction control, and its maintenance is completed by the scheduling controller (writable), and the other modules are read-only. Each status register is used to implement unified information exchange, and its maintenance is completed by each sub-resource controller (writable), and the other modules except the scheduling controller are read-only. Based on the above design, the data flow and control flow are logically isolated. Except for the scheduling controller, each sub-resource controller has the read permission of all configuration and status registers and the write permission of the status registers maintained by itself, which reduces the risk of data flow conflicts, improves the maintenance efficiency of hardware, and facilitates subsequent testing and use.

[0127] In addition, the existing RASP architecture still has the problem of high wiring complexity. The main reasons for this are: 1) There are many BANKs: The increase in the number of BANKs will lead to a year-on-year increase in the number of wiring; 2) The reconfigurable computing resources and BANKs are interconnected separately: There is no unified connection method between computing resources and BANKs. The reconstruction process of each computing resource is carried out inside the reconfigurable controller. Each computing unit is interconnected with all BANK areas. With each additional reconfigurable controller, the number of wiring increases exponentially; 3) Redundant data control logic. For the same BANK area, the address generation and address distribution logic between reconfigurable controllers of different algorithms cannot be reused even if they are the same. As a result, with each additional algorithm, a reconfigurable controller must be added, and the number of wiring increases exponentially.

[0128] In view of the above problems, the present application provides three methods for reducing wiring complexity, which are:

[0129] 1. Reduce the number of BANKs. This solution is the most direct way to reduce the number of wirings. The architecture design is optimized to reduce the number of BANKs from 128 to 72 BANKs to reduce the number of wirings.

[0130] 2. Modify the computing resource reconstruction method: Reconstruct the computing structure required by the algorithm by configuring the computing resource path, isolate the computing resources inside the PE array from the external interaction, and interconnect with the BANK through a unified input and output buffer to reduce the number of interconnection lines.

[0131] 3. Storage and computing decoupling: Through storage and computing decoupling, for the same bank area, one address generation and address distribution logic corresponds to one memory access mode. Even if the algorithms are different, the same memory access methods can be reused. At the same time, computing resources and storage resources are decoupled. Through the unified data buffer interconnection, they can be combined to realize multiple algorithm modes, and a large number of reconstruction resources can be reused to reduce the number of wiring.

[0132] Furthermore, the present application implements two configuration time optimization strategies for three-dimensional reconfigurable hardware acceleration cores, namely:

[0133] 1. Compress redundant configuration information to improve configuration efficiency: The total length of the configuration information of the 3D reconfigurable acceleration core is 512 bits, which is 39% shorter than the 832 bits of the Rui core.

[0134] 2. Expand the size of a single configuration register to 256 bits, reduce the number of configuration registers and save configuration time. The 256-bit length is selected to maximize the use of the AXI bus bandwidth.

[0135] After the above two optimizations, the configuration time of the FFT algorithm of the 3D reconfigurable hardware acceleration core will be shortened from the original 7.857us to 0.657us, a reduction of 91.6%.

[0136] Through the above analysis, it can be seen that the three-dimensional reconfigurable acceleration core chip provided in the embodiment of the present application is designed based on the static scheduling and static data flow execution (SSD) model of storage and computing decoupling. Its design goal is to provide high-performance and low-power signal processing acceleration capabilities, and has the following characteristics:

[0137] 1. Scalability: The storage-computing decoupling method is used to combine the solidified storage mode with the computing mode to expand the scope of algorithm support. It can adapt to different application scenarios and algorithm requirements and support some unknown algorithms. For example, the chip supports different data types and different computing unit and storage unit configurations, rather than different algorithm configuration modes.

[0138] Specifically, scalability is reflected in the following aspects:

[0139] 1) Based on the SSD model, the design idea of ​​storage and computing decoupling is added to further split the static data flow, and the data transmission path is divided into three categories: storage, computing and distribution, which are encapsulated separately. While utilizing the high computing efficiency of static data flow, the coupling method is increased and the application function is expanded.

[0140] 2) A unit-level scheduling mechanism is designed to implement multiple algorithms through the combination of different storage control logics and dozens of computing control logics, and supports variable parameters. This design provides scalable algorithm support for future users.

[0141] 3) For typical algorithms with certain requirements, they are implemented using the support of API function libraries, and the reconstruction path, algorithm type and execution order are determined to ensure their performance. For algorithms with uncertain requirements, they are implemented using unit-level configuration to ensure that algorithms that meet the acceleration core requirements proposed by new applications in the future can be deployed on the acceleration core to achieve scalability.

[0142] 4) Computing resources and memory access resources are divided into independent data flow units, which perform computing operations in parallel under the control of clock signals. Static data flow will solidify the data transmission path for different algorithms inside the hardware and encapsulate it as a black box. The computing state in the black box is controlled by the configuration register. This design method can reduce the complexity of the data path, reduce or avoid problems caused by data conflicts and resource competition, thereby providing scalability while taking into account the improvement of computing efficiency.

[0143] 5) In addition, with the widespread application of digital images, the ability to efficiently process and analyze high-precision image data is urgently needed in new fields such as computer vision, medical image processing, and unmanned driving. Image processing algorithms play a vital role in these applications and can be used for tasks such as image enhancement, object recognition, and motion tracking. High-performance DSP processors are often able to execute image processing algorithms more efficiently, providing real-time processing speed and lower power consumption. This provides a technical basis for the development of image processing algorithms, allowing more complex algorithms to be implemented in practical applications. Therefore, in order to improve the scalability of the algorithm, a two-dimensional sliding window memory access controller for image processing is added to the three-dimensional reconfigurable hardware acceleration chip, which can realize a two-dimensional sliding window process, and then realize image enhancement related algorithms, such as neighborhood averaging, weighted averaging, Gaussian filtering, bilateral filtering, Laplace operator and Sobel operator, edge detection, etc.

[0144] 2. Versatility, specifically reflected in the following aspects:

[0145] 1) It has the characteristics of software-defined hardware. Its design concept is to abstract hardware resources into programmable modules so that they can be reconfigured and reallocated as needed. Through software-defined hardware, the function of the hardware can be changed by reprogramming and reconfiguring without replacing the hardware. Such functions make it suitable for multiple application fields and scenarios, such as: graphics processing, machine learning reasoning, signal processing, etc.

[0146] 2) The resources of computing units can be reallocated according to the needs of the task to achieve better performance and efficiency. In addition, since static scheduling is performed at runtime, it can adapt to a variety of different computing loads and requirements, providing better versatility.

[0147] 3) Supports breaking down computing tasks into many small operations, each of which corresponds to a node in the computing structure diagram. These operation steps can be executed in different orders, thereby achieving the decomposition and reorganization of computing tasks.

[0148] 4) Fixed-length configuration registers are used to control the configuration mode and corresponding API configuration functions are provided, so that the chip architecture can be easily integrated into other compilation frameworks, thereby further improving the versatility of the chip architecture.

[0149] 3. Parallelism: The static data flow execution method can give full play to the advantages of parallel data flow, make full use of hardware resources, and achieve higher computing parallelism.

[0150] 4. Flexibility: It can support real-time processing requirements, and reconstruct in a short time by combining CPU scheduling with static data flow execution to achieve real-time processing requirements of multiple algorithms or data, and provide flexible acceleration solutions for various applications. For example, it can support different data flow processing methods as needed, such as high-parallelism and low-correlation data flow processing, low-parallelism and high-correlation data flow processing, full-pipeline high-speed data flow processing, etc.; it supports different operation sequence combinations, such as free combination of memory access, calculation and storage modes.

[0151] 5. Ease of use: It has better usability and can provide users with more friendly function libraries and programming interfaces, allowing users to use acceleration cores more easily to accelerate signal processing tasks.

[0152] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0153] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0154] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0155] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0156] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A three-dimensional reconfigurable hardware acceleration core chip, characterized in that: The three-dimensional reconfigurable hardware acceleration core chip includes: a reconfigurable computing array, a storage array and a controller set; The reconfigurable computing array is used to provide at least one unit-level computing unit and at least one algorithm-level computing unit; The storage array is used to store operation data input via the AXI bus and output by the reconfigurable operation array; The controller set is used to control the at least one unit-level computing unit and the at least one algorithm-level computing unit to respectively implement unit-level computing operations and algorithm-level computing operations, and to control the storage of computational data in the storage array.

2. A three-dimensional reconfigurable hardware acceleration core chip according to claim 1, characterized in that: The controller set includes: a DSP scheduler, a computing resource controller, a memory access resource controller, and a DMA resource controller; The computing resource controller is used to schedule and control the reconfigurable computing array; The memory access resource controller is used to control data scheduling between the storage array and the reconfigurable computing array; The DMA resource controller is used to control the data transfer between the storage array and the AXI bus; The DSP scheduler is used to control the reconstruction mode and operation status of the computing resource controller, the memory access resource controller and the DMA resource controller.

3. The three-dimensional reconfigurable hardware acceleration core chip according to claim 2, characterized in that: The computing resource controller includes an input and output buffer, a computing resource decoder, a first register module and a first reconstruction state machine module; The input and output buffer is used to cache the output data of the memory access resource controller and the reconfigurable operation array; The computing resource decoder is used to decode the control instructions sent by the DSP scheduler; The first register module is used to store the reconstruction information of the computing resource controller; The first reconfiguration state machine module is used to control the operation process of the reconfigurable operation array.

4. The three-dimensional reconfigurable hardware acceleration core chip according to claim 2, characterized in that: The memory access resource controller includes: a data buffer module, a second reconstruction state machine module, a second register module and a sub-controller; The data buffer module is used to cache the output data of the DMA resource controller and the computing resource controller; The second reconstruction state machine module is used to control the reconstruction process of the sub-controller; The second register module is used to store the reconstruction information of the memory access resource controller; The sub-controller includes a plurality of unit-level memory access controllers and a plurality of algorithm-level memory access controllers, each of the unit-level memory access controllers corresponds to a unit-level memory access mode, and each of the algorithm-level memory access controllers corresponds to an algorithm-level memory access mode.

5. The three-dimensional reconfigurable hardware acceleration core chip according to claim 2, characterized in that: The DMA resource controller includes: a DMA module, a logic control module, a data configuration module and a DMA_Port; The DMA module comprises a first status register, wherein the first status register is used to store the working status of the DMA module; The logic control module is used to control the state machine jump, and the state machine is used to control the data handling process of the DMA module, and the state machine is composed of the first state register and a combinational logic circuit; The data configuration module is used to store the configuration information of the DMA module and use the configuration information to configure the DMA module; The DMA_Port is used for data transmission between the DMA module and the device's built-in memory.

6. The three-dimensional reconfigurable hardware acceleration core chip according to claim 2, characterized in that: The DSP controller includes: a buffer area, a decoder, a configuration circuit module, a register group, a FSM state machine and a transmitter; The buffer is used to cache instructions sent on the AXI bus; The decoder is used to decode the instructions received by the three-dimensional reconfigurable hardware acceleration core; The configuration circuit module includes a read configuration circuit, a write configuration circuit and an interface circuit.

7. The three-dimensional reconfigurable hardware acceleration core chip according to claim 6, characterized in that: The register group includes a device register, a configuration register and a second status register; The device register is used to store the response mode information and the working mode information of the three-dimensional reconfigurable hardware acceleration core chip; The configuration register is used to store configuration information of the memory access resource controller and the DMA resource controller; The second status register is used to store the running status information of the controller set.

8. The three-dimensional reconfigurable hardware acceleration core chip according to claim 6, characterized in that: The FSM state machine is used to manage the register group, manage storage permissions, manage calculation sequences and detect data dependencies.

9. The three-dimensional reconfigurable hardware acceleration core chip according to claim 6, characterized in that: The transmitter includes a LEN instruction counter unit and a path selection unit; The LEN instruction counter unit is used to record the number of instructions sent by the device register, identify the address of the instruction, and send the address to the DSP scheduler; The path selection unit is used to select a distribution path for the configuration information of the configuration register, or a receiving path for the status information of the status register.

10. An algorithm task reconstruction method, applied to the three-dimensional reconfigurable hardware acceleration core chip as claimed in claim 1, characterized in that: The algorithm task reconstruction method comprises: The three-dimensional reconfigurable hardware acceleration core chip receives the device configuration information sent by the management core chip, and writes the device configuration information into the configuration register; Each controller in the controller set completes configuration according to the device configuration information and realizes reconstruction of the algorithm task.

11. The algorithm task reconstruction method according to claim 10, characterized in that: If the three-dimensional reconfigurable hardware acceleration core chip is the main processing device of the algorithm task, the three-dimensional reconfigurable hardware acceleration core chip receives the device configuration information sent by the management core chip and writes the device configuration information into the configuration register, including: The three-dimensional reconfigurable hardware acceleration core chip obtains the device configuration information by polling the control command area in the double-rate synchronous dynamic random access memory, and writes the device configuration information into the configuration register. The device configuration information is written into the control command area of ​​the double-rate synchronous dynamic random access memory by the management core chip through a cross switch matrix.

12. The algorithm task reconstruction method according to claim 10, characterized in that: If the three-dimensional reconfigurable hardware acceleration core chip is a slave processing device of the algorithm task, the three-dimensional reconfigurable hardware acceleration core chip receives device configuration information sent by the management core chip and writes the device configuration information into a configuration register, including: The three-dimensional reconfigurable hardware acceleration core chip receives the device configuration information sent by the management core chip through the crossbar switch matrix, and writes the device configuration information into the configuration register in sequence.

13. A processing device, characterized in that: The device is equipped with a management core chip and a three-dimensional reconfigurable hardware acceleration core chip as claimed in any one of claims 1 to 9.

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