Read-write conversion circuit, write driving circuit and memory

Abstract

The invention provides a read-write conversion circuit, a write driving circuit and a memory. The read-write conversion circuit comprises a reading circuit, the first input end and the second input end of the reading circuit are connected with a local signal line and a complementary local signal line respectively, and the first output end and the second output end of the reading circuit are connected with a global signal line and a complementary global signal line respectively; the first input end and the second input end of the write-in circuit are respectively connected with the global signal line and the complementary global signal line, and the first output end and the second output end of the write-in circuit are respectively connected with the local signal line and the complementary local signal line; wherein the first input end and the second input end of the write-in circuit receive the same data, and the first output end and the second output end of the write-in circuit output opposite data. According to the embodiment, the data writing speed can be increased.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a read-write conversion circuit, a write drive circuit and a memory capable of improving the read-write speed. Background Art

[0002] In DRAM memory, the data read and write path is mainly composed of read and write control circuits, read and write conversion circuits, and sense amplifiers.

[0003] When writing data, the write driver circuit in the read-write control circuit receives the data sent by the controller, sends the data to be written to the read-write conversion circuit, and then the read-write conversion circuit transmits the data to the sense amplifier, and then the sense amplifier amplifies the data to be written into the storage unit through the sense amplification function of the sense amplifier. When reading data, the sense amplifier operates to amplify the data stored in the storage unit to transmit it to the read-write conversion circuit, and the read-write conversion circuit transmits the data to the read buffer circuit in the read-write control circuit.

[0004] In the related art, the read-write conversion circuit is usually set to work in a differential double-ended working mode (transmitting complementary data through two signal lines) or a single-ended transmission mode (transmitting data through one signal line). The differential double-ended working mode has high power consumption, and the single-ended transmission mode is easily affected by noise. It is difficult for the read-write conversion circuit to achieve a balance between performance and power consumption.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] The purpose of the present disclosure is to provide a read-write conversion circuit, a write drive circuit and a memory, which are used to simultaneously improve the read-write speed of the read-write conversion circuit and reduce the read-write power consumption.

[0007] According to a first aspect of the present disclosure, a read-write conversion circuit is provided, comprising: a first read circuit, wherein a first input terminal and a second input terminal of the first read circuit are respectively connected to a local signal line and a complementary local signal line, and a first output terminal and a second output terminal of the first read circuit are respectively connected to a global signal line and a complementary global signal line; a first write circuit, wherein a first input terminal and a second input terminal of the first write circuit are respectively connected to a global signal line and a complementary global signal line, and a first output terminal and a second output terminal of the first write circuit are respectively connected to a local signal line and a complementary local signal line; wherein the first input terminal and the second input terminal of the first write circuit receive the same data, and the first output terminal and the second output terminal of the write circuit output opposite data.

[0008] In an exemplary embodiment of the present disclosure, the first write circuit includes a first write conversion circuit connected between a first input terminal and a first output terminal of the first write circuit, and a second write conversion circuit connected between a second input terminal and a second output terminal of the first write circuit, the first write conversion circuit is used to transmit data from a global signal line to a local signal line, and the second write conversion circuit is used to transmit inverted data of data from a complementary global signal line to a complementary local signal line.

[0009] In an exemplary embodiment of the present disclosure, a first write conversion circuit includes a first write transistor, a first end of the first write transistor is connected to a global signal line, a second end of the first write transistor is connected to a local signal line, and a control end of the first write transistor receives a write control signal; a second write conversion circuit includes a second write transistor and a third write transistor, a first end of the second write transistor is grounded, a control end is connected to a complementary global signal line, a first end of the third write transistor is connected to a second end of the second write transistor, a second end of the third write transistor is connected to a complementary local signal line, and a control end of the third write transistor receives a write control signal; the first write transistor, the second write transistor, and the third write transistor are all N-type transistors.

[0010] In an exemplary embodiment of the present disclosure, the first read circuit includes a first read conversion circuit connected between a first input terminal and a first output terminal of the first read circuit, a second read conversion circuit connected between a second input terminal and a second output terminal of the first read circuit, and a voltage source circuit connecting the first read conversion circuit and the second read conversion circuit, the first read conversion circuit and the second read conversion circuit have the same structure, the first read circuit is used to transmit data from a local signal line to a global signal line, and the second read circuit is used to transmit data from a complementary local signal line to a complementary global signal line.

[0011] In an exemplary embodiment of the present disclosure, a first read conversion circuit includes a first read transistor and a second read transistor, the control end of the first read transistor is connected to a local signal line, the first end of the first read transistor is connected to a voltage source circuit, the control end of the second read transistor receives a read control signal, the first end of the second read transistor is connected to the second end of the first read transistor, and the second end of the second read transistor is connected to a global signal line; the second read conversion circuit includes a third read transistor and a fourth read transistor, the control end of the third read transistor is connected to a complementary local signal line, the first end of the third read transistor is connected to the voltage source circuit, the control end of the fourth read transistor receives a read control signal, the first end of the fourth read transistor is connected to the second end of the third read transistor, and the second end of the fourth read transistor is connected to a complementary global signal line; the first read transistor, the second read transistor, the third read transistor, and the fourth read transistor are all N-type transistors.

[0012] According to a second aspect of the present disclosure, a write driver circuit is provided, connected to a read-write conversion circuit as described above, including a first write driver unit and a second write driver unit, the input ends of the first write driver unit and the second write driver unit being used to receive the same external input data, the output end of the first write driver unit being connected to a global signal line, the output end of the second write driver unit being connected to a complementary global signal line, and the output data of the first write driver unit and the second write driver unit being the same.

[0013] According to a third aspect of the present disclosure, a read-write conversion circuit is provided, comprising: a second read circuit, comprising a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first input terminal and the second input terminal of the second read circuit are respectively connected to a local signal line and a complementary local signal line, and the first output terminal and the second output terminal of the second read circuit are respectively connected to a global signal line and a complementary global signal line; a second write circuit, comprising a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first input terminal and the second input terminal of the second write circuit are respectively connected to the global signal line and the complementary global signal line, and the first output terminal and the second output terminal of the second write circuit are respectively connected to the local signal line line and a complementary local signal line; a local read-write control circuit, comprising a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first input terminal and the second input terminal of the local read-write control circuit are respectively connected to the local signal line and the complementary local signal line, and the first output terminal and the second output terminal of the local read-write control circuit are respectively connected to the bit line and the complementary bit line; wherein the first input terminal and the second input terminal of the second write circuit receive opposite data, and the first output terminal and the second output terminal of the second write circuit output the same data; the first input terminal and the second input terminal of the local read-write control circuit receive the same data, and the first output terminal and the second output terminal of the local read-write control circuit output opposite data.

[0014] In an exemplary embodiment of the present disclosure, the second read circuit includes a third read conversion module and a fourth read conversion module, the third read conversion module is connected between the global signal line and the local signal line, and is used to transfer the data of the local signal line to the global signal line; the fourth read conversion module is connected between the complementary global signal line and the complementary local signal line, and is used to transfer the data of the complementary local signal line to the complementary global signal line; the second write circuit includes a third write conversion circuit connected between the global signal line and the local signal line and a fourth write conversion circuit connected between the complementary global signal line and the complementary local signal line, and the third write conversion circuit is used to transfer the data of the global signal line to the complementary global signal line during the write operation. The fourth write conversion circuit is used to transfer the data of the complementary global signal line to the complementary local signal line when the write operation is performed; the local read-write control circuit includes a first read-write control circuit connected between the local signal line and the bit line and a second read-write control circuit connected between the complementary local signal line and the complementary bit line, the first read-write control circuit is used to transfer the data of the local signal line to the bit line when the write operation is performed, and transfer the data on the bit line to the local signal line when the read operation is performed; the second read-write control circuit is used to transfer the data of the complementary local signal line to the complementary bit line when the write operation is performed, and transfer the data on the complementary bit line to the complementary local signal line when the read operation is performed.

[0015] In an exemplary embodiment of the present disclosure, the third write conversion circuit includes a first write transistor, the first end of the first write transistor is connected to the global signal line, the second end is connected to the local signal line, and the control end receives a write control signal; the fourth write conversion circuit includes a data inverter and a third write transistor, the input end of the data inverter is connected to the complementary global signal line, the output end is connected to the first end of the third write transistor, the second end of the third write transistor is connected to the complementary local signal line, and the control end receives the write control signal.

[0016] In an exemplary embodiment of the present disclosure, the first read-write control circuit includes a sixth read transistor, a fourth write transistor, a fifth write transistor and a first column selection transistor, the first end of the sixth read transistor is connected to the local signal line, the second end is connected to the first end of the first column selection transistor, and the control end receives a read control signal; the gate of the fourth write transistor is connected to the local signal line, the source is grounded, and the drain is connected to the second end of the fifth write transistor; the first end of the fifth write transistor is connected to the first end of the first column selection transistor, and the control end receives a write control signal; the second end of the first column selection transistor is connected to the bit line, and the control end receives a column selection signal; the second read-write control circuit includes a second column selection transistor, the first end of the second column selection transistor is connected to the complementary local signal line, the second end is connected to the complementary bit line, and the control end receives the complementary column selection signal.

[0017] According to a fourth aspect of the present disclosure, a memory is provided, comprising a circuit as described in any one of the above items.

[0018] The disclosed embodiment of the invention uses a differential dual-terminal working mode in a read operation and uses two data lines to transmit the same data in a write operation, thereby improving the anti-noise capability of the read operation process, increasing the read speed and reducing the power consumption of the write operation. At the same time, it increases the conversion speed from write operation to read operation, thereby improving the overall performance of the memory.

[0019] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0021] Figure 1 is a schematic diagram of the structure of a read-write conversion circuit in an exemplary embodiment of the present disclosure.

[0022] Figure 2 Schematic diagram of a read-write conversion circuit in one embodiment of the present disclosure.

[0023] Figure 3 is a circuit diagram of a first writing circuit in one embodiment of the present disclosure.

[0024] Figure 4 is a circuit diagram of a second reading circuit in one embodiment of the present disclosure.

[0025] Figure 5A to Figure 5D is a schematic diagram of a circuit in which a local signal line LIO and a complementary local signal line LIO# are connected in an embodiment of the present disclosure.

[0026] Figure 6 Schematic diagram of a read-write conversion circuit in one embodiment of the present disclosure.

[0027] Figure 7 A schematic diagram of a write driver circuit provided in an embodiment of the present disclosure.

[0028] Figure 8 is a schematic diagram of another read-write conversion circuit provided in an exemplary embodiment of the present disclosure.

[0029] Fig. 9 is a circuit diagram of a read-write conversion circuit 800 in one embodiment. DETAILED DESCRIPTION

[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0031] In addition, the accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0032] The exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0033] Figure 1 is a schematic diagram of the structure of a read-write conversion circuit in an exemplary embodiment of the present disclosure.

[0034] refer to Figure 1 , the read-write conversion circuit 100 may include:

[0035] A first read circuit 11, wherein a first input terminal and a second input terminal of the first read circuit 11 are respectively connected to a local signal line LIO and a complementary local signal line LIO#, and a first output terminal and a second output terminal of the first read circuit 11 are respectively connected to a global signal line GIO and a complementary global signal line GIO#;

[0036] A first write circuit 12, wherein a first input terminal and a second input terminal of the first write circuit 12 are respectively connected to a global signal line GIO and a complementary global signal line GIO#, and a first output terminal and a second output terminal of the first write circuit 12 are respectively connected to a local signal line LIO and a complementary local signal line LIO#;

[0037] The first input terminal and the second input terminal of the first writing circuit 12 receive the same data, and the first output terminal and the second output terminal of the writing circuit output opposite data.

[0038] When the read-write conversion circuit works in the double-ended differential working mode, the local signal line LIO and the complementary local signal line LIO# simultaneously transmit complementary data with opposite phases, and the global signal line GIO and the complementary global signal line GIO# simultaneously transmit complementary data with opposite phases, which is conducive to eliminating common-mode noise. Small differences between signals can also be recognized and amplified by the sensitive amplifier, which is conducive to improving the signal transmission performance. However, during the data writing process, the data on the global signal line GIO and the complementary global signal line GIO# need to be frequently flipped (toggle) according to the input data, which consumes a lot of power.

[0039] When the read-write conversion circuit works in the single-ended working mode, data is transmitted only through the local signal line LIO and the global signal line GIO. During the write operation, the flip frequency of the signal transmission on the global signal line GIO can be reduced, and the power consumption can be reduced. However, the noise suppression capability is poor and the signal is easily interfered by noise.

[0040] In the embodiment of the present disclosure, the first data terminal and the second input terminal of the first write circuit 12 respectively receive the same second data D2 through the global signal line GIO and the complementary global signal line GIO#, and output the second data D2 and the inverted data D2# of the second data D2 to the local signal line LIO and the complementary local signal line LIO# through the first output terminal and the second output terminal.

[0041] During the write operation, the first write circuit 12 operates in a single-ended working mode, that is, two signal lines are used to transmit data of the same polarity at the same time to reduce the flipping frequency of the data transmission line. By adjusting the layout and wiring of the global signal line GIO and the complementary global signal line GIO#, the write speed can be increased and the write power consumption can be reduced. For example, the global signal line GIO and the complementary global signal line GIO# are directly arranged adjacent to each other. Since the data between the global signal line GIO and the complementary global signal line GIO# is the same, there is no crosstalk, the power consumption is low, and the data transmission speed is fast.

[0042] In addition, since the global signal line GIO and the complementary global signal line GIO# transmit the same phase signal during the write operation, when the write operation is converted to a read operation, the speed of implementing the first stage of pre-equalization operation (setting the global signal line GIO and the complementary global signal line GIO# to the same potential) will be faster, that is, the speed of converting the write operation to the read operation will be faster, and the read and write efficiency will be further improved.

[0043] Figure 2 Schematic diagram of a read-write conversion circuit in one embodiment of the present disclosure.

[0044] refer to Figure 2In one embodiment, the first read circuit 11 includes a first read conversion circuit 111 connected between a first input terminal and a first output terminal of the read circuit 11, and a second read conversion circuit 112 connected between a second input terminal and a second output terminal of the read circuit 11. The functions of the first read conversion circuit 111 and the second read conversion circuit 112 are the same.

[0045] The first write circuit 12 includes a first write conversion circuit 121 connected between the first input terminal and the first output terminal of the first write circuit 12, and a second write conversion circuit 122 connected between the second input terminal and the second output terminal of the first write circuit 12. The first write conversion circuit 121 is used to transmit input data, and the second write conversion circuit 122 is used to invert the input data and output it.

[0046] By setting two read conversion circuits with the same function, the first read circuit 11 can work in a double-ended differential mode and simultaneously differentially transmit two identical data, thereby increasing the data transmission rate. Compared with working in a single-ended transmission mode, the transmission speed is faster and the reliability is higher.

[0047] By setting up two write conversion circuits that receive the same data and send opposite data, the first write circuit 12 receives the same data, and the flipping state is consistent when the data is flipped, thereby achieving a faster data flipping speed, which is beneficial to reducing the power consumption caused by repeated data flipping and improving the data transmission speed.

[0048] This achieves a balance between high data transmission speed and low power consumption.

[0049] Figure 3 is a circuit diagram of a first writing circuit in one embodiment of the present disclosure.

[0050] refer to Figure 3 In one embodiment, the first write conversion circuit 121 includes a first write transistor MW1, a first end of the first write transistor MW1 is connected to the global signal line GIO, a second end of the first write transistor MW1 is connected to the local signal line LIO, and a control end of the first write transistor MW1 receives a write control signal WR.

[0051] The second write conversion circuit 122 includes a second write transistor MW2 and a third write transistor MW3, the first end of the second write transistor MW2 is grounded, the control end is connected to the complementary global signal line GIO#, the first end of the third write transistor MW3 is connected to the second end of the second write transistor MW2, the second end of the third write transistor MW3 is connected to the complementary local signal line LIO#, and the control end of the third write transistor MW3 receives a write control signal WR.

[0052] The first write transistor MW1, the second write transistor MW2, and the third write transistor MW3 are all N-type transistors. An amplifier circuit is connected between the local signal line LIO and the complementary local signal line LIO#. Before data is written, the local signal line LIO and the complementary local signal line LIO# are pre-equalized to a first equalization voltage (the first equalization voltage can be greater than the bit line equalization voltage, for example, the first equalization voltage is 1.05V and the bit line equalization voltage is 0.5V). After the write operation starts, when a voltage difference occurs between the local signal line LIO and the complementary local signal line LIO#, the amplifier circuit connected between the local signal line LIO and the complementary local signal line LIO# will amplify the voltages of the local signal line LIO and the complementary local signal line LIO# to the power supply voltage VDD and the ground voltage VSS, respectively, to represent data 1 and data 0.

[0053] exist Figure 3 In the illustrated embodiment, during a write operation, the write control signal WR is at a high level (enabled state), the first write transistor MW1 and the third write transistor MW3 are both in an on state, the global signal line GIO is connected to the local signal line LIO through the turned-on first write transistor MW1, and the complementary global signal line GIO# and the complementary local signal line LIO# are respectively connected to the gate and drain of the second write transistor MW2.

[0054] When the global signal line GIO and the complementary global signal line GIO# both transmit data 1, the local signal line LIO transmits data 1, the second write transistor MW2 is turned on, the complementary local signal line LIO# receives a low level signal through the second write transistor MW2, and the complementary local signal line LIO# transmits data 0.

[0055] When the global signal line GIO and the complementary global signal line GIO# both transmit data 0, the local signal line LIO transmits data 0, the second write transistor MW2 is turned off, and the complementary local signal line LIO# maintains the first equilibrium voltage representing a high level. The amplifier circuit connected between the local signal line LIO and the complementary local signal line LIO# will amplify the voltages of the local signal line LIO and the complementary local signal line LIO# to the ground voltage VSS and the power supply voltage VDD, respectively, to represent data 0 and data 1.

[0056] The complementary global signal line GIO# sets data 1 to the complementary local signal line LIO# faster (the default state of the complementary local signal line LIO# is the first equilibrium voltage), and sets data 0 slower (because the voltage needs to be adjusted and the adjustment process is affected by the switching speed and driving capability of the second write transistor MW2 and the third write transistor MW3).

[0057] Figure 3This is only an example of a method for inverting the data transmitted on the complementary global signal line GIO#. In another embodiment, the second write transistor MW2 can also be directly replaced by an inverter, the input end of the inverter is connected to the complementary global signal line GIO#, and the output end of the inverter is connected to the source of the third write transistor MW3, so that when the write control signal WR is at a high level (enabled state), the first write transistor MW1 and the third write transistor MW3 are both in the on state, the data on the complementary local signal line LIO# is always the inverted data (complementary data) of the complementary global signal line GIO#.

[0058] Regardless of the embodiment, transistors that are turned on by the write control signal WR are set on the global signal line GIO and the complementary global signal line GIO# to prevent the global signal line GIO and the complementary global signal line GIO# from transmitting data to the local signal line LIO and the complementary local signal line LIO# during non-write operations.

[0059] Those skilled in the art can set specific circuits of the first write conversion circuit 121 and the second write conversion circuit 122 according to the functional limitations of the first write conversion circuit 121 and the second write conversion circuit 122, and the present disclosure does not impose any special limitation on this.

[0060] Figure 4 is a circuit diagram of a first reading circuit in one embodiment of the present disclosure.

[0061] refer to Figure 4 In one embodiment, the first read conversion circuit 111 includes a first read transistor MR1 and a second read transistor MR2, the control end of the first read transistor MR1 is connected to the local signal line LIO, the first end of the first read transistor MR1 is connected to the voltage source circuit 113, the control end of the second read transistor MR2 receives a read control signal RD, the first end of the second read transistor MR2 is connected to the second end of the first read transistor MR1, and the second end of the second read transistor MR2 is connected to the global signal line GIO.

[0062] The second read conversion circuit 112 includes a third read transistor MR3 and a fourth read transistor MR4, the control end of the third read transistor MR3 is connected to the complementary local signal line LIO#, the first end of the third read transistor MR3 is connected to the voltage source circuit 113, the control end of the fourth read transistor MR4 receives the read control signal RD, the first end of the fourth read transistor MR4 is connected to the second end of the third read transistor MR3, and the second end of the fourth read transistor MR4 is connected to the complementary global signal line GIO#.

[0063] The first read transistor MR1 , the second read transistor MR2 , the third read transistor MR3 , and the fourth read transistor MR4 are all N-type transistors.

[0064] The voltage source circuit 113 includes a fifth read transistor MR5 , a first terminal of the fifth read transistor MR5 is grounded, a second terminal is connected to the first read conversion circuit 111 and the second read conversion circuit 112 , and a control terminal receives a read control signal RD.

[0065] During the read operation, the read control signal RD is at a high level (enabled state), the second read transistor MR2, the fourth read transistor MR4, and the fifth read transistor MR5 are all in the on state, the gate of the first read transistor MR1 is connected to the local signal line LIO, the source is grounded, and the drain is connected to the global signal line GIO; the gate of the third read transistor MR3 is connected to the complementary local signal line LIO#, the source is grounded, and the drain is connected to the complementary global signal line GIO#.

[0066] An amplifier circuit is connected between the global signal line GIO and the complementary global signal line GIO#. Before data reading, the global signal line GIO and the complementary global signal line GIO# are both set to the second equalization voltage. After data reading starts, when a voltage difference occurs between the global signal line GIO and the complementary global signal line GIO#, the amplifier circuit connected between the global signal line GIO and the complementary global signal line GIO# will amplify the voltages of the global signal line GIO and the complementary global signal line GIO# to the power supply voltage VDD and the ground voltage VSS, respectively, to represent data 1 and data 0.

[0067] When the local signal line LIO transmits data 1, the complementary local signal line LIO# transmits data 0. The first read transistor MR1 is turned on, and the global signal line GIO receives a low-level signal through the turned-on first read transistor MR1. The third read transistor MR3 is turned off, and the complementary global signal line GIO# maintains a second balanced voltage. The amplifier circuit connected between the global signal line GIO and the complementary global signal line GIO# will amplify the voltages of the global signal line GIO and the complementary global signal line GIO# to the ground voltage VSS and the power supply voltage VDD, respectively, to represent data 0 and data 1.

[0068] When the local signal line LIO transmits data 0, the complementary local signal line LIO# transmits data 1. The first read transistor MR1 is turned off, and the global signal line GIO maintains the second equilibrium voltage; the third read transistor MR3 is turned on, and the complementary global signal line GIO# receives a low-level signal through the turned-on third read transistor MR3. The amplifier circuit connected between the global signal line GIO and the complementary global signal line GIO# will amplify the voltages of the global signal line GIO and the complementary global signal line GIO# to the power supply voltage VDD and the ground voltage VSS, respectively, to represent data 1 and data 0.

[0069] It should be noted that the second equalization voltage can be either a high potential for representing data 1 or a low potential for representing data 0; at the same time, since the data transmitted by GIO is opposite to the data transmitted by LIO during the reading process, the data of the global signal line GIO and the complementary global signal line GIO# must be inverted subsequently to ensure that the data finally read out is correct.

[0070] In other embodiments, the first read circuit 11 may also be configured to have other forms. For example, only the first read conversion circuit 111 and the first read conversion circuit 112 are configured so that one end of the first read conversion circuit 111 and the first read conversion circuit 112 originally used to connect to the voltage source circuit 113 is directly grounded, and only the second read transistor MR2 is configured in the first read conversion circuit 111, and only the fourth read transistor MR4 is configured in the second read conversion circuit 112. Thus, when the second read transistor MR2 and the fourth read transistor MR4 are turned on by the read control signal RD, the local signal line LIO and the complementary local signal line LIO# transmit data directly to the global signal line GIO and the complementary global signal line GIO#, respectively.

[0071] Regardless of the embodiment, transistors that are turned on by the read control signal RD are set on the global signal line GIO and the complementary global signal line GIO# to prevent the local signal line LIO and the complementary local signal line LIO# from transmitting data to the global signal line GIO and the complementary global signal line GIO# during non-read operations.

[0072] Next, an amplifier circuit connected between the local signal line LIO and the complementary local signal line LIO#, and an amplifier circuit connected between the global signal line GIO and the complementary global signal line GIO# are described.

[0073] Figure 5A to Figure 5D is a schematic diagram of a circuit in which a local signal line LIO and a complementary local signal line LIO# are connected in an embodiment of the present disclosure.

[0074] refer to Figure 5A to Figure 5C The local signal line LIO and the complementary local signal line LIO# are simultaneously connected to the first amplifier circuit 51 and the second amplifier circuit 52, and the first amplifier circuit 51 and the second amplifier circuit 52 are both used to amplify the voltage difference between the local signal line LIO or the complementary local signal line LIO#.

[0075] In addition, an equalization control circuit 53 is connected between the local signal line LIO and the complementary local signal line LIO#. The equalization control circuit 53 is used to control the potentials of the local signal line LIO and the complementary local signal line LIO# to be equal to the first equalization voltage VP before data is read.

[0076] refer to Figure 5AThe first amplifier circuit 51 includes a first N-type transistor MN1, a second N-type transistor MN2, and a ground control transistor MN3. The first end of the first N-type transistor MN1 is connected to the local signal line LIO, the second end is connected to the first node NCS, and the control end is connected to the complementary local signal line LIO#; the first end of the second N-type transistor MN2 is connected to the complementary local signal line LIO#, the second end is connected to the first node NCS, and the control end is connected to the local signal line LIO; the first end of the ground control transistor MN3 is grounded, the second end is connected to the first node NCS, and the control end receives the read enable signal RdEn. The read enable signal RdEn can be the same as the read control signal RD, or it can be a little earlier than the read control signal RD.

[0077] refer to Figure 5B The second amplifier circuit 52 includes a first P-type transistor MP1, a second P-type transistor MP2, and a power control transistor MP3. The first end of the first P-type transistor MP1 is connected to the local signal line LIO, the second end is connected to the second node PCS, and the control end is connected to the complementary local signal line LIO#; the first end of the second P-type transistor MP2 is connected to the complementary local signal line LIO#, the second end is connected to the second node PCS, and the control end is connected to the local signal line LIO; the first end of the power control transistor MP3 is connected to the power supply voltage VDD, the second end is connected to the second node PCS, and the control end receives the complementary read enable signal RdEnN, which is the inverted signal of the read enable signal RdEn.

[0078] refer to Figure 5C The local signal line LIO and the complementary local signal line LIO# are simultaneously connected to the equalization control circuit 53. The equalization control circuit 53 includes a pre-equalization transistor EQ0, a first equalization transistor EQ1, and a second equalization transistor EQ2. The first end and the second end of the pre-equalization transistor EQ0 are respectively connected to the local signal line LIO and the complementary local signal line LIO#, and the control end receives the pre-equalization signal PREEQ; the first end of the first equalization transistor EQ1 is connected to the local signal line LIO, and the second end is connected to the first equalization voltage VP, and the control end receives the pre-equalization signal PREEQ; the first end of the second equalization transistor EQ2 is connected to the complementary local signal line LIO#, and the second end is connected to the first equalization voltage VP, and the control end receives the pre-equalization signal PREEQ.

[0079] refer to Figure 5D The local signal line LIO is connected to the bit line BLA through the first column selection transistor MY1, and the control end of the first column selection transistor MY1 receives the column selection signal CSL; the complementary local signal line LIO# is connected to the complementary bit line BLB through the second column selection transistor MY2, and the control end of the second column selection transistor MY2 receives the column selection signal CSL. The bit line BLA and the complementary bit line BLB are both connected to the sense amplifier SA and the storage unit (not shown).

[0080] The first amplifier circuit 51, the second amplifier circuit 52, and the equalization control circuit 53 can be arranged adjacent to each other or at different locations. It is only necessary to ensure that a set of local signal lines LIO and complementary local signal lines LIO# are connected to the first amplifier circuit 51, the second amplifier circuit 52, and the equalization control circuit 53 at the same time.

[0081] Before reading data, the bit line BLA and the complementary bit line BLB are controlled to be equal to the bit line equalization voltage. In the equalization control circuit 53, the pre-equalization signal PREEQ controls the pre-equalization transistor EQ0, the first equalization transistor EQ1 and the second equalization transistor EQ2 to be turned on, so that the local signal line LIO and the complementary local signal line LIO# are equal to the first equalization voltage VP.

[0082] When data reading begins, the transistor in the memory cell is turned on, and the storage capacitor in the memory cell exchanges charge with the bit line BLA or the complementary bit line BLB, causing a voltage difference between the bit line BLA and the complementary bit line BLB. The sense amplifier SA amplifies the voltage difference, so that the higher voltage of the bit line BLA and the complementary bit line BLB is amplified to the power supply voltage VDD, and the lower voltage is amplified to the ground voltage VSS, to represent data 1 and data 0.

[0083] Next, the column select signal CSL controls the bit line BLA and the complementary bit line BLB to transmit data to the local signal line LIO and the complementary local signal line LIO#, respectively, so that a voltage difference occurs between the local signal line LIO and the complementary local signal line LIO#.

[0084] When the local signal line LIO transmits data 1 and the complementary local signal line LIO# transmits data 0, the potential of the local signal line LIO is higher than the potential of the complementary local signal line LIO#. The power control transistor MP3 and the ground control transistor MN3 are both turned on, the second N-type transistor MN2 and the first P-type transistor MP1 are turned on first, the local signal line LIO is set to connect to the power supply voltage VDD and the complementary local signal line LIO# is grounded, and the first N-type transistor MN1 and the second P-type transistor MP2 are turned off, so that the potential of the local signal line LIO is equal to the power supply voltage VDD, and the potential of the complementary local signal line LIO# is equal to the ground potential VSS.

[0085] When the local signal line LIO transmits data 0 and the complementary local signal line LIO# transmits data 1, the potential of the local signal line LIO is lower than the potential of the complementary local signal line LIO#. The power control transistor MP3 and the ground control transistor MN3 are both turned on, the first N-type transistor MN1 and the second P-type transistor MP2 are turned on first, the local signal line LIO is set to be grounded, the complementary local signal line LIO# is connected to the power supply voltage VDD, and the second N-type transistor MN2 and the first P-type transistor MP1 are turned off, so that the potential of the local signal line LIO is equal to the ground potential VSS, and the potential of the complementary local signal line LIO# is equal to the power supply voltage VDD.

[0086] Before data is written, in the equalization control circuit 53, the pre-equalization signal PREEQ controls the pre-equalization transistor EQ0, the first equalization transistor EQ1 and the second equalization transistor EQ2 to turn on, so that the local signal line LIO and the complementary local signal line LIO# are both equal to the first equalization voltage VP.

[0087] During the data writing operation, the global signal line GIO and the complementary global signal line GIO# transmit data to the local signal line LIO and the complementary local signal line LIO# through the first write conversion circuit 121 and the second write conversion circuit 122, respectively, so that a voltage difference appears between the local signal line LIO and the complementary local signal line LIO#. According to the above principle, the first amplifier circuit 51 and the second amplifier circuit 52 amplify the voltage difference between the local signal line LIO and the complementary local signal line LIO#, so that the higher voltage of the local signal line LIO and the complementary local signal line LIO# is amplified to the power supply voltage VDD, and the lower voltage is amplified to the ground voltage VSS, so as to represent data 1 and data 0.

[0088] An amplifier circuit is also connected between the global signal line GIO and the complementary global signal line GIO# to amplify the voltage difference between the global signal line GIO and the complementary global signal line GIO#, so that the higher voltage of the global signal line GIO and the complementary global signal line GIO# is amplified to the power supply voltage VDD, and the lower voltage is amplified to the ground voltage VSS to represent data 1 and data 0.

[0089] The circuit connected between the global signal line GIO and the complementary global signal line GIO# operates on the same principle as the circuit connected between the local signal line LIO and the complementary local signal line LIO# (including the first amplifier circuit 51, the second amplifier circuit 52, and the equalization control circuit 53), which will not be described in detail in this disclosure.

[0090] Figure 6 Schematic diagram of a read-write conversion circuit in one embodiment of the present disclosure.

[0091] refer to Figure 6 , combined with Figure 3 , Figure 4 , Figure 5A-Figure 5C Embodiment, forming Figure 6 Circuit diagram shown.

[0092] During a write operation, when the global signal line GIO and the complementary global signal line GIO# both transmit data 1, the local signal line LIO and the complementary local signal line LIO# respectively receive data 1 and data 0. When the global signal line GIO and the complementary global signal line GIO# both transmit data 0, the local signal line LIO receives data 0, and the complementary local signal line LIO# still maintains the first balanced voltage VP, indicating that the complementary local signal line LIO# is equal to data 1.

[0093] During the read operation, when the local signal line LIO and the complementary local signal line LIO# transmit data 1 and data 0 respectively, the first read control transistor MR1, the second read control transistor MR2, and the fifth read control transistor MR5 are turned on, and the global signal line GIO receives a low-level signal. The complementary global signal line GIO# still maintains the second equilibrium voltage, so that the voltage of the global signal line GIO is lower than the voltage of the complementary global signal line GIO#. The amplifier circuit connected between the global signal line GIO and the complementary global signal line GIO# amplifies the voltage difference, sets the complementary global signal line GIO# to connect to the power supply voltage VDD, and enables the complementary global signal line GIO# to receive data 1.

[0094] When the local signal line LIO and the complementary local signal line LIO# transmit data 0 and data 1 respectively, the third read control transistor MR3, the fourth read control transistor MR4, and the fifth read control transistor MR5 are turned on, and the complementary global signal line GIO# receives data 0. The global signal line GIO still maintains the second equilibrium voltage, so that the voltage of the global signal line GIO is higher than the voltage of the complementary global signal line GIO#. The amplifier circuit connected between the global signal line GIO and the complementary global signal line GIO# amplifies the voltage difference, sets the global signal line GIO to connect to the power supply voltage VDD, and enables the global signal line GIO to receive data 1.

[0095] In the related art, during a write operation, the global signal line GIO and the complementary global signal line GIO# transmit complementary data. Therefore, in an exemplary embodiment of the present disclosure, the write drive circuit connecting the global signal line GIO and the complementary global signal line GIO# is also improved so that the global signal line GIO and the complementary global signal line GIO# transmit the same data during a write operation.

[0096] Figure 7 A schematic diagram of a write driver circuit provided in an embodiment of the present disclosure.

[0097] refer to Figure 7The write driver circuit 700 is connected to the read-write conversion circuit of any of the above embodiments through the global signal line GIO and the complementary global signal line GIO#, and includes a first write driver unit 71 and a second write driver unit 72. The input ends of the first write driver unit 71 and the second write driver unit 72 are used to receive the same external input data Data, the output end of the first write driver unit 71 is connected to the global signal line GIO, and the output end of the second write driver unit 72 is connected to the complementary global signal line GIO#. The output data Gdata of the first write driver unit 71 and the second write driver unit 72 are the same.

[0098] exist Figure 7 In the illustrated embodiment, the first write driver unit 71 and the second write driver unit 72 both include an inverter INV, a NAND gate NAND, an AND gate AND, a first NOR gate NOR1, a second NOR gate NOR2, a first output transistor M1, and a second output transistor M2.

[0099] The first input end of the AND gate AND receives external input data Data, and the second input end receives a write enable signal WREn. The input end of the inverter INV receives an equalization signal EQ. The two input ends of the first NOR gate NOR1 are respectively connected to the output end of the AND gate AND and the output end of the inverter INV. The first input end of the NAND gate NAND receives the equalization signal EQ, and the second input end receives the write enable signal WREn. The two input ends of the second NOR gate NOR2 receive the external input data Data and are connected to the output end of the NOR gate NAND. The output end of the first NOR gate NOR1 controls the first output transistor M1, and the output end of the second NOR gate NOR2 controls the second output transistor M2. The first output transistor M1 is a P-type transistor, the source of which is connected to the power supply voltage VDD, and the drain of which is connected to the global signal line GIO or the complementary global signal line GIO#. The second output transistor M2 is an N-type transistor, the source of which is grounded, and the drain of which is connected to the global signal line GIO or the complementary global signal line GIO#.

[0100] During a write operation, the write enable signal WREn is at a high level, and the equalization signal EQ is at a high level.

[0101] If the external input data Data is 1, the AND gate AND outputs data 1, the first NOR gate NOR1 outputs data 0, the first output transistor M1 is turned on, and the global signal line GIO and the complementary global signal line GIO# receive data Gdata = 1. At the same time, the NAND gate NAND outputs data 0, the second NOR gate NOR2 outputs data 0, and the second output transistor M2 is turned off.

[0102] If the external input data Data is 0, the AND gate AND outputs data 0, the first NOR gate NOR1 outputs data 1, and the first output transistor M1 is turned off. The NAND gate NAND outputs data 0, the second NOR gate NOR2 outputs data 1, the second output transistor M2 is turned on, and the global signal line GIO and the complementary global signal line GIO# receive data Gdata=0.

[0103] Since the circuit structures of the first write driver unit 71 and the second write driver unit 72 are completely the same, the first write driver unit 71 and the second write driver unit 72 receive the same external data and output the same data Gdata to the global signal line GIO and the complementary global signal line GIO#.

[0104] Figure 7 The circuit shown is only an example. In fact, as long as the circuit structure and function of the first write driver unit 71 and the second write driver unit 72 are set to be the same, the first write driver unit 71 and the second write driver unit 72 can receive the same external data and output the same data Gdata to the global signal line GIO and the complementary global signal line GIO#.

[0105] In another embodiment of the present disclosure, another read-write conversion circuit is provided.

[0106] Figure 8 is a schematic diagram of another read-write conversion circuit provided in an exemplary embodiment of the present disclosure.

[0107] refer to Figure 8 , the read-write conversion circuit 800 includes:

[0108] A second read circuit 81 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal and the second input terminal of the second read circuit 81 are respectively connected to the local signal line LIO and the complementary local signal line LIO#. The first output terminal and the second output terminal of the second read circuit 81 are respectively connected to the global signal line GIO and the complementary global signal line GIO#.

[0109] A second write circuit 82 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal and the second input terminal of the second write circuit 82 are respectively connected to the global signal line GIO and the complementary global signal line GIO#. The first output terminal and the second output terminal of the second write circuit 82 are respectively connected to the local signal line LIO and the complementary local signal line LIO#.

[0110] The local read / write control circuit 83 includes a first end, a second end, a third end, and a fourth end. The first end and the second end of the local read / write control circuit 83 are respectively connected to the local signal line LIO and the complementary local signal line LIO#. The third end and the fourth end of the local read / write control circuit 83 are respectively connected to the bit line BLA and the complementary bit line BLB.

[0111] Among them, the first input terminal and the second input terminal of the second write circuit 82 receive opposite data, and the first output terminal and the second output terminal of the second write circuit 82 output the same data; the first terminal and the second terminal of the local read-write control circuit 83 receive the same data, and the third terminal and the fourth terminal of the local read-write control circuit 83 output opposite data.

[0112] exist Figure 8 In the illustrated embodiment, the second read circuit 81 includes a third read conversion module 811 and a fourth read conversion module 812. The third read conversion module 811 is connected between the global signal line GIO and the local signal line LIO, and is used to transfer the data of the local signal line LIO to the global signal line GIO. The fourth read conversion module 812 is connected between the complementary global signal line GIO# and the complementary local signal line LIO#, and is used to transfer the data of the complementary local signal line LIO# to the complementary global signal line GIO#.

[0113] The third read conversion module 811 and the fourth read conversion module 812 have the same structure. When the data transmitted on the local signal line LIO and the complementary local signal line LIO# are different and inverted, the data transmitted to the global signal line GIO and the complementary global signal line GIO# through the third read conversion module 811 and the fourth read conversion module 812 are also different and inverted.

[0114] The circuit of the second reading circuit 81 can be Figure 2 The circuit structure of the first reading circuit 11 in the illustrated embodiments is completely the same, and the present disclosure does not impose any special limitation on this.

[0115] The second write circuit 82 includes a third write conversion circuit 821 connected between the global signal line GIO and the local signal line LIO and a fourth write conversion circuit 822 connected between the complementary global signal line GIO# and the complementary local signal line LIO#. The third write conversion circuit 821 is used to transfer the data of the global signal line GIO to the local signal line LIO during a write operation, and the fourth write conversion circuit 822 is used to transfer the inverted data of the complementary global signal line GIO# to the complementary local signal line LIO# during a write operation. The third write conversion circuit 821 and the fourth write conversion circuit 822 receive different and inverted data and output the same data.

[0116] The local read-write control circuit 83 includes a first read-write control circuit 831 connected between the local signal line LIO and the bit line BLA and a second read-write control circuit 832 connected between the complementary local signal line LIO# and the complementary bit line BLB. The first read-write control circuit 831 is used to transfer the inverted data of the local signal line LIO to the bit line BLA during a write operation, and to transfer the data on the bit line BLA to the local signal line LIO during a read operation; the second read-write control circuit 832 is used to transfer the data of the complementary local signal line LIO# to the complementary bit line BLB during a write operation, and to transfer the data on the complementary bit line BLB to the complementary local signal line LIO# during a read operation.

[0117] During a write operation, the first read-write control circuit 831 and the second read-write control circuit 832 receive the same data and output different and inverted data. During a read operation, the first read-write control circuit 831 and the second read-write control circuit 832 receive different and inverted data and output different and inverted data.

[0118] During a write operation, the same data is transmitted on the local signal line LIO and the complementary local signal line LIO#, which helps to reduce the conversion speed from the write operation to the read operation.

[0119] Fig. 9 is a circuit diagram of a read-write conversion circuit 800 in one embodiment.

[0120] refer to Fig. 9 In one embodiment, the third write conversion circuit 821 includes a first write transistor MW1, a first end of the first write transistor MW1 is connected to the global signal line GIO, a second end of the first write transistor MW1 is connected to the local signal line LIO, and a control end receives a write control signal WR.

[0121] The fourth write conversion circuit 822 includes an inverter INV0 and a third write transistor MW3, the input end of the inverter INV0 is connected to the complementary global signal line GIO#, the output end is connected to the first end of the third write transistor MW3, the second end of the third write transistor MW3 is connected to the complementary local signal line LIO#, and the control end receives the write control signal WR. The inverter INV0 can also be replaced by other elements or element combinations that can realize the signal inversion function, such as the aforementioned second write transistor MW2, and those skilled in the art can set it according to actual conditions.

[0122] The first write transistor MW1 and the third write transistor MW3 are both N-type transistors. In the write operation, the write control signal WR is at a high level, that is, in the enabled state, the local signal line LIO receives the data on the global signal line GIO, and the complementary local signal line LIO# receives the inverted data of the data on the complementary global signal line GIO#.

[0123] The first read-write control circuit 831 includes a sixth read transistor MR6 , fourth and fifth write transistors MW4 and MW5 , and a first column selection transistor MY1 .

[0124] Among them, the first end of the sixth read transistor MR6 is connected to the local signal line LIO, the second end is connected to the first end of the first column selection transistor MY1, and the control end receives the read control signal RD. The gate of the fourth write transistor MW4 is connected to the local signal line LIO, the source is grounded, and the drain is connected to the second end of the fifth write transistor MW5. The first end of the fifth write transistor MW5 is connected to the first end of the first column selection transistor MY1, and the control end receives the write control signal WR. The second end of the first column selection transistor MY1 is connected to the bit line BLA, and the control end receives the column selection signal CSL.

[0125] The second read / write control circuit 832 includes a second column selection transistor MY2 , a first end of the second column selection transistor MY2 is connected to the complementary local signal line LIO#, a second end is connected to the complementary bit line BLB, and a control end receives a column selection signal CSL.

[0126] In the write operation, the write control signal WR is high, the read control signal RD is low, the fifth write transistor MW5 is turned on, and the sixth read transistor MR6 is turned off. The first terminal of the first column selection transistor MY1 is set equal to the first equalization voltage or the bit line equalization voltage.

[0127] The data on the complementary global signal line GIO# is transmitted to the first end of the second column selection transistor MY2 through the inverter INV0 and the conductive third write transistor MW3. The data on the global signal line GIO is transmitted to the first end of the first column selection transistor MY1 through the conductive first write transistor MW1, the fourth write transistor MW4, and the conductive fifth write transistor MW5. The timing difference between the data received by the first column selection transistor MY1 and the second column selection transistor MY2 is small. When the column selection signal CSL is an enable signal, the time points at which the bit line BLA and the complementary bit line BLB receive data are close, and the data reception quality is high.

[0128] When data 1 is transmitted on both the local signal line LIO and the complementary local signal line LIO#, the fourth write transistor MW4 is turned on, the first end of the first column selection transistor MY1 receives data 0, and the first end of the second column selection transistor MY2 receives data 1. When the column selection signal CS is an enable signal, data 1 and data 0 are transmitted to the bit line BLA and the complementary bit line BLB through the first column selection transistor MY1 and the second column selection transistor MY2, respectively.

[0129] When data 0 is transmitted on both the local signal line LIO and the complementary local signal line LIO#, the fourth write transistor MW4 is turned off, the first end of the first column selection transistor MY1 is equal to the first equalization voltage or the bit line equalization voltage, and the first end of the second column selection transistor MY2 receives data 0. When the column selection signal CSL is an enable signal, the first equalization voltage and data 0 are transmitted to the bit line BLA and the complementary bit line BLB through the first column selection transistor MY1 and the second column selection transistor MY2, respectively. The sense amplifier connected to the bit line BLA and the complementary bit line BLB amplifies the voltage difference, sets the potential on the bit line BLA to the power supply voltage VDD, and receives data 1 on the bit line BLA.

[0130] When reading data, the write control signal WR is at a low level, the read control signal RD is at a high level, the fifth write transistor MW5 is turned off, and the sixth read transistor MR6 is turned on. When the column select signal CSL is an enable signal, the first column select transistor MY1 and the second column select transistor MY2 are turned on, and the local signal line LIO and the complementary local signal line LIO# receive the data on the bit line BLA and the complementary bit line BLB respectively through the turned-on first column select transistor MY1 and the turned-on second column select transistor MY2.

[0131] Fig. 9 The circuit shown is only an example. In other embodiments of the present disclosure, other circuit implementations may be provided to implement the second writing circuit 82 and the local read-write control circuit 83 .

[0132] In an exemplary embodiment of the present disclosure, a memory is further provided, comprising the circuit of any one of the above embodiments.

[0133] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0134] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. A read-write conversion circuit, characterized in that: include: a first reading circuit, wherein a first input terminal and a second input terminal of the first reading circuit are respectively connected to a local signal line and a complementary local signal line, and a first output terminal and a second output terminal of the first reading circuit are respectively connected to a global signal line and a complementary global signal line; a first write circuit, wherein the first input terminal and the second input terminal of the first write circuit are respectively connected to the global signal line and the complementary global signal line, and the first output terminal and the second output terminal of the first write circuit are respectively connected to the local signal line and the complementary local signal line; The first input terminal and the second input terminal of the first writing circuit receive the same data, and the first output terminal and the second output terminal of the writing circuit output opposite data.

2. The read-write conversion circuit according to claim 1, characterized in that: The first write circuit includes a first write conversion circuit connected between the first input terminal and the first output terminal of the first write circuit, and a second write conversion circuit connected between the second input terminal and the second output terminal of the first write circuit, the first write conversion circuit is used to transmit data from the global signal line to the local signal line, and the second write conversion circuit is used to transmit inverted data from the complementary global signal line to the complementary local signal line.

3. The read-write conversion circuit according to claim 2, characterized in that: The first write conversion circuit includes a first write transistor, a first end of the first write transistor is connected to the global signal line, a second end of the first write transistor is connected to the local signal line, and a control end of the first write transistor receives a write control signal; The second write conversion circuit comprises a second write transistor and a third write transistor, wherein the first end of the second write transistor is grounded, and the control end is connected to the complementary global signal line, the first end of the third write transistor is connected to the second end of the second write transistor, the second end of the third write transistor is connected to the complementary local signal line, and the control end of the third write transistor receives the write control signal; The first write transistor, the second write transistor, and the third write transistor are all N-type transistors.

4. The read-write conversion circuit according to any one of claims 1 to 3, characterized in that: The first read circuit includes a first read conversion circuit connected between the first input terminal and the first output terminal of the first read circuit, a second read conversion circuit connected between the second input terminal and the second output terminal of the first read circuit, and a voltage source circuit connecting the first read conversion circuit and the second read conversion circuit. The first read conversion circuit and the second read conversion circuit have the same structure. The first read circuit is used to transmit data from the local signal line to the global signal line, and the second read circuit is used to transmit data from the complementary local signal line to the complementary global signal line.

5. The read-write conversion circuit according to claim 4, characterized in that: The first read conversion circuit includes a first read transistor and a second read transistor, the control end of the first read transistor is connected to the local signal line, the first end of the first read transistor is connected to the voltage source circuit, the control end of the second read transistor receives a read control signal, the first end of the second read transistor is connected to the second end of the first read transistor, and the second end of the second read transistor is connected to the global signal line; The second read conversion circuit comprises a third read transistor and a fourth read transistor, the control end of the third read transistor is connected to the complementary local signal line, the first end of the third read transistor is connected to the voltage source circuit, the control end of the fourth read transistor receives a read control signal, the first end of the fourth read transistor is connected to the second end of the third read transistor, and the second end of the fourth read transistor is connected to the complementary global signal line; The first read transistor, the second read transistor, the third read transistor, and the fourth read transistor are all N-type transistors.

6. A write drive circuit, characterized in that: A read-write conversion circuit connected to any one of claims 1 to 5, comprising a first write driver unit and a second write driver unit, wherein the input ends of the first write driver unit and the second write driver unit are used to receive the same external input data, the output end of the first write driver unit is connected to a global signal line, the output end of the second write driver unit is connected to a complementary global signal line, and the output data of the first write driver unit and the second write driver unit are the same.

7. A read-write conversion circuit, characterized in that: include: A second reading circuit comprises a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first input terminal and the second input terminal of the second reading circuit are respectively connected to a local signal line and a complementary local signal line, and the first output terminal and the second output terminal of the second reading circuit are respectively connected to a global signal line and a complementary global signal line; A second write circuit comprises a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first input terminal and the second input terminal of the second write circuit are respectively connected to a global signal line and a complementary global signal line, and the first output terminal and the second output terminal of the second write circuit are respectively connected to a local signal line and a complementary local signal line; A local read-write control circuit comprises a first input terminal, a second input terminal, a first output terminal and a second output terminal, wherein the first input terminal and the second input terminal of the local read-write control circuit are respectively connected to a local signal line and a complementary local signal line, and the first output terminal and the second output terminal of the local read-write control circuit are respectively connected to a bit line and a complementary bit line; Among them, the first input terminal and the second input terminal of the second write circuit receive opposite data, and the first output terminal and the second output terminal of the second write circuit output the same data; the first input terminal and the second input terminal of the local read-write control circuit receive the same data, and the first output terminal and the second output terminal of the local read-write control circuit output opposite data.

8. The read-write conversion circuit according to claim 7, characterized in that: The second read circuit includes a third read conversion module and a fourth read conversion module, wherein the third read conversion module is connected between the global signal line and the local signal line, and is used to transfer data of the local signal line to the global signal line; the fourth read conversion module is connected between the complementary global signal line and the complementary local signal line, and is used to transfer data of the complementary local signal line to the complementary global signal line; The second write circuit includes a third write conversion circuit connected between the global signal line and the local signal line and a fourth write conversion circuit connected between the complementary global signal line and the complementary local signal line, wherein the third write conversion circuit is used to transfer data of the global signal line to the local signal line during a write operation, and the fourth write conversion circuit is used to transfer data of the complementary global signal line to the complementary local signal line during a write operation; The local read-write control circuit includes a first read-write control circuit connected between the local signal line and the bit line and a second read-write control circuit connected between the complementary local signal line and the complementary bit line. The first read-write control circuit is used to transfer the data of the local signal line to the bit line during a write operation, and to transfer the data on the bit line to the local signal line during a read operation; the second read-write control circuit is used to transfer the data of the complementary local signal line to the complementary bit line during a write operation, and to transfer the data on the complementary bit line to the complementary local signal line during a read operation.

9. The read-write conversion circuit according to claim 8, characterized in that: The third write conversion circuit includes a first write transistor, a first end of the first write transistor is connected to the global signal line, a second end is connected to the local signal line, and a control end receives a write control signal; The fourth write conversion circuit includes a data inverter and a third write transistor, the input end of the data inverter is connected to a complementary global signal line, the output end is connected to a first end of the third write transistor, the second end of the third write transistor is connected to a complementary local signal line, and the control end receives a write control signal.

10. The read-write conversion circuit according to claim 9, characterized in that: The first read-write control circuit includes a sixth read transistor, a fourth write transistor, a fifth write transistor and a first column selection transistor, wherein the first end of the sixth read transistor is connected to the local signal line, the second end is connected to the first end of the first column selection transistor, and the control end receives a read control signal; the gate of the fourth write transistor is connected to the local signal line, the source is grounded, and the drain is connected to the second end of the fifth write transistor; the first end of the fifth write transistor is connected to the first end of the first column selection transistor, and the control end receives a write control signal; the second end of the first column selection transistor is connected to the bit line, and the control end receives a column selection signal; The second read-write control circuit includes a second column selection transistor, a first end of the second column selection transistor is connected to a complementary local signal line, a second end is connected to a complementary bit line, and a control end receives a complementary column selection signal.

11. A memory comprising the circuit according to any one of claims 1 to 10.

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