PN junction gate gallium oxide-based MODFET device and preparation method thereof

Abstract

The invention discloses a PN junction gate gallium oxide-based MODFET device and a preparation method thereof, the PN junction gate gallium oxide-based MODFET device sequentially comprises a substrate, a channel layer, a spacing layer, a delta doping layer and a barrier layer, and further comprises a first ohmic contact region arranged on one side of the end surfaces of the spacing layer, the delta doping layer and the barrier layer; the second ohmic contact region is arranged on the other side of the end surfaces of the spacing layer, the delta doping layer and the barrier layer; the first ohmic contact region and the second ohmic contact region are higher than the upper surface of the barrier layer; the PN junction structure is arranged on a part of the surface of the barrier layer; the dielectric layer structure is arranged above the barrier layer, the PN junction structure, the first ohmic contact region and the second ohmic contact region in a crossing manner; a source electrode disposed on the first ohmic contact region; the drain electrode is arranged on the second ohmic contact region; the gate electrode is arranged on the PN junction structure and the dielectric layer structure, and the upper end of the gate electrode extends towards the two ends of the dielectric layer structure located above the PN junction structure to form a field plate structure. The reliability of the device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor power devices and manufacturing technology, and in particular to a PN junction gate gallium oxide-based MODFET device and a preparation method thereof. Background Art

[0002] β-phase gallium oxide (Ga 2 O 3 ) due to its wide bandgap (4.6-4.9 eV), high breakdown field (8 MV / cm) and high electron saturation velocity (1.8-2×10 7 cm / s) and has become one of the most promising materials for next-generation power devices. Due to the low mobility of gallium oxide, their channel mobility is limited. Modulation doped field effect transistors (MODFETs) are produced by δ-doping silicon in β-AlGa 2 O 3 / Ga 2 O 3 Modulated doped two-dimensional electron gas (2DEG) is generated at the heterojunction, which significantly improves the channel mobility. Due to the existence of 2DEG, MODFET is usually in a normally-on state, that is, a depletion-mode device, which is not conducive to the application of power devices. Enhancement-mode devices do not require additional negative gate electrode voltage to turn off the device, which can significantly reduce the static power consumption and switching loss in the off state of the circuit. And because gallium oxide devices have excellent performance under high power conditions, they are often used in application environments with high output power. These environments require normally-off operation for reasons such as safety and simplified driver circuits. Therefore, it is very important and meaningful to study and manufacture enhanced gallium oxide devices with excellent performance and reliability. As device design becomes more and more complex and the degree of integration becomes higher and higher, the advantages of enhancement-mode devices such as energy saving and simple design are becoming more and more prominent.

[0003] Since gallium oxide has not yet achieved effective P-type doping, the design of normally-off devices is currently mainly through the introduction of P-type materials or recessed gate structures. For normally-off devices with P-type gate electrode structures formed by P-type materials (such as P-type gallium nitride), when the metal / P-type gallium nitride Schottky junction is under a high electric field, the failure of the Schottky junction will cause a sharp gate electrode current. The reason is the generation of defects under the Schottky depletion region under high tunneling current and high electric field, resulting in a lower gate electrode breakdown voltage. For normally-off devices formed by designing recessed gate electrode structures, the etching process in the recessed gate technology may cause the material surface quality to degrade, which may cause device performance degradation, such as increasing gate electrode leakage current and reducing device reliability. As the depth of the recessed gate increases, the electric field peak in the area under the gate increases, which may lead to device degradation and gate electrode breakdown problems under high electric fields. The low gate electrode breakdown voltage of the device will limit the device gate electrode driving voltage, the gate electrode voltage swing is small, and the device application is limited. The existing means of realizing enhanced devices all have obvious defects, which seriously hinder the practical application of the devices and urgently need to be effectively solved. A breakthrough in this problem can greatly promote the gallium oxide devices to enter the practical application stage faster and more widely, and promote the rapid development of my country's new material semiconductor industry. Summary of the invention

[0004] In view of this, the object of the present invention is to provide a PN junction gate gallium oxide-based MODFET device, which is reliable to implement, can effectively reduce the gate electrode leakage current and improve the gate electrode breakdown voltage and device reliability.

[0005] In order to achieve the above technical objectives, the technical solution adopted by the present invention is:

[0006] A PN junction gate gallium oxide-based MODFET device comprises, from bottom to top, a substrate, a channel layer, a spacer layer, a delta doping layer and a barrier layer, and further comprises:

[0007] A first ohmic contact region is arranged on one side of the end surface of the spacer layer, the delta-doped layer and the barrier layer;

[0008] A second ohmic contact region is arranged on the other side of the end surface of the spacer layer, the delta-doped layer and the barrier layer; the height of the first ohmic contact region and the second ohmic contact region is higher than the upper surface of the barrier layer;

[0009] A PN junction structure is provided on a portion of the surface of the barrier layer;

[0010] A dielectric layer structure is arranged across the barrier layer, the PN junction structure, the first ohmic contact region and the second ohmic contact region;

[0011] A source electrode, disposed on the first ohmic contact region;

[0012] A drain electrode, disposed on the second ohmic contact region;

[0013] The gate electrode is arranged on the PN junction structure and the dielectric layer structure, and the metal on the upper end of the gate electrode extends to the two ends of the dielectric layer structure located above the PN junction structure to form a field plate structure.

[0014] Furthermore, the PN junction structure includes a P-type gallium nitride layer and an N-type gallium nitride layer, the P-type gallium nitride layer is arranged on a partial surface of the barrier layer, a middle groove is provided on the upper surface of the P-type gallium nitride layer, and the N-type gallium nitride layer is arranged in the middle groove on the upper surface of the P-type gallium nitride layer.

[0015] Furthermore, the dielectric layer structure includes a first dielectric layer and a second dielectric layer, the first dielectric layer is arranged on the upper surface of the first ohmic contact region and on the upper surface of the barrier layer between the right end of the first ohmic contact region and the left end surface of the PN junction structure; the second dielectric layer is arranged on the upper surface of the second ohmic contact region and on the upper surface of the barrier layer between the left end of the second ohmic contact region and the right end surface of the PN junction structure, the first dielectric layer and the second dielectric layer extend upward near the side of the PN junction structure, and cover the upper surface of the P-type gallium nitride layer of the PN junction structure.

[0016] Furthermore, the distance between the PN junction structure and the first ohmic contact region is smaller than the distance between the PN junction structure and the second ohmic contact region.

[0017] Furthermore, the widths of the substrate and the channel layer are equal, the widths of the spacer layer, the delta-doped layer and the barrier layer are equal, and the width of the channel layer is greater than the width of the spacer layer; the width of the upper end of the gate electrode is equal to the distance between the left and right edges of the dielectric layer structure located above the PN junction structure.

[0018] Furthermore, the substrate is a high-resistance or semi-insulating β-Ga 2 O 3 The doping element type includes any one of Mg, Fe, Zn, N and P; the doping concentration is 1×10 18 ~5×10 18 / cm -3 ;

[0019] The channel layer is unintentionally doped with β-Ga 2 O 3 Channel layer;

[0020] The spacer layer is N-type doped β-(AlGa) 2 O 3 The doping element type includes any one of Si, Sn and Ge, and the doping concentration is 1×10 18 ~5×10 18 / cm -3, Al component is 0.15~0.3;

[0021] The delta doped layer is N-type doped β-(AlGa) 2 O 3 , the doping element types include Si, and the doping concentration is 1×10 19 ~5×10 19 / cm -3 , Al component is 0.15~0.3;

[0022] The barrier layer is N-type doped β-(AlGa) 2 O 3 The doping element type includes any one of Si, Sn and Ge, and the doping concentration is 1×10 18 ~5×10 18 / cm -3 , Al component is 0.15~0.3;

[0023] The first ohmic contact region and the second ohmic contact region are both N-type heavily doped β-Ga 2 O 3 The doping element type includes any one of Si, Sn and Ge, and the doping concentration is about 1×10 20 ~5×10 20 cm -3 ;

[0024] The P-type gallium nitride layer in the PN junction structure is P-type doped, and the doping element type includes Mg, and the doping concentration is 1×10 18 ~5×10 19 / cm -3 The N-type gallium nitride layer is N-type doped, and the doping element type includes any one of Si, Sn and Ge, and the doping concentration is 1×10 18 ~2×10 19 / cm -3 ;

[0025] The dielectric layer structure is Al 2 O 3 、SiO 2 、Si 3 N 4 and HfO 2 Any one of the following is formed;

[0026] The source electrode and the drain electrode are both formed by stacking two metals in which any one of Ni, Ti and Al and Au are combined;

[0027] The gate electrode is formed by stacking two metals, Ni and Au, or stacking two metals, Ti and Au.

[0028] Furthermore, the thickness of the substrate is 250-600um;

[0029] The thickness of the channel layer is 150 to 360 nm;

[0030] The thickness of the spacer layer is 3 to 8 nm;

[0031] The thickness of the delta-doped layer is 1 to 2 nm;

[0032] The thickness of the barrier layer is 15 to 30 nm;

[0033] The thickness of the dielectric layer structure is 2 to 5 nm;

[0034] The thickness of the P-type gallium nitride layer in the PN junction structure is 20 to 100 nm, and the thickness of the N-type gallium nitride layer is 10 to 40 nm;

[0035] The thickness of the first ohmic contact region and the second ohmic contact region are both 50-100 nm.

[0036] The present invention also provides a method for preparing a PN junction gate gallium oxide-based MODFET device, which is reliable to implement and can effectively reduce gate electrode leakage current and improve gate electrode breakdown voltage and device reliability.

[0037] In order to achieve the above technical objectives, the technical solution adopted by the present invention is:

[0038] A method for preparing a PN junction gate gallium oxide-based MODFET device is prepared based on the above-mentioned PN junction gate gallium oxide-based MODFET device, and specifically comprises the following steps:

[0039] Step 1, pre-treating the substrate surface in a reaction chamber;

[0040] Step 2, homoepitaxially growing a channel layer on the upper surface of the substrate;

[0041] Step 3, heteroepitaxially growing a spacer layer on the upper surface of the channel layer;

[0042] Step 4, homoepitaxially growing a delta-doped layer and a barrier layer from bottom to top on the upper surface of the spacer layer;

[0043] Step 5, etching the two ends of the barrier layer, and continuing to etch the two ends of the delta-doped layer and the spacer layer in sequence along the etching direction until two first grooves are formed on the upper surface of the channel layer, and growing a first ohmic contact region on the first groove at the left end, and growing a second ohmic contact region on the first groove at the right end;

[0044] Step 6, graphically growing a PN junction structure in the middle of the upper surface of the barrier layer;

[0045] Step 7, depositing a dielectric layer structure on the surface of the barrier layer, the PN junction structure, the first ohmic contact region and the second ohmic contact region, and etching the left and right ends and the middle upper surface of the dielectric layer structure respectively to leave a second groove, a third groove and a fourth groove for depositing a source electrode, a drain electrode and a gate electrode;

[0046] Step 8, depositing a source electrode on the second groove, and depositing a drain electrode on the third groove;

[0047] Step 9: depositing a gate electrode on the fourth groove to form a field plate structure on the upper surface of the PN junction structure.

[0048] Furthermore, the step 6 is specifically as follows: the PN junction structure includes a P-type gallium nitride layer and an N-type gallium nitride layer, and the P-type gallium nitride layer is patterned and grown in the middle of the upper surface of the barrier layer, wherein the patterning method is to coat a photoresist on the surface of the P-type gallium nitride layer, expose and develop the photoresist to form a patterned photoresist, and use the patterned photoresist as a mask to etch the P-type gallium nitride layer to form a middle groove located in the middle; and an N-type gallium nitride layer is grown in the middle groove on the upper surface of the P-type gallium nitride layer, and the growth height of the N-type gallium nitride layer is flush with the upper surface of the P-type gallium nitride layer.

[0049] Furthermore, the method for pre-treating the substrate surface in step 1 is standard RCA cleaning: before starting growth, the substrate is heated to remove impurities adsorbed on the substrate; the epitaxial growth method adopts one of MOCVD, MBE and ALD.

[0050] By adopting the above technical solution, the present invention has the following beneficial effects compared with the prior art:

[0051] The present invention significantly improves the gate electrode breakdown voltage of the device and improves the gate electrode reliability of the device by inserting a PN junction structure with a field plate embedded between the gate electrode and the barrier layer. The P-type gallium nitride layer can deplete electrons and effectively block the 2DEG channel below. The N-type gallium nitride layer and the P-type gallium nitride layer form a PN junction to generate a built-in electric field to regulate the depletion layer. When the gate electrode is forward biased, the PN junction is reverse biased, depleting the 2DEG channel below, inhibiting the diffusion of carriers, and realizing the right bias of the threshold voltage. In addition, since the PN junction depletion region extends to the N side and the P side, the device exhibits a lower gate electrode leakage current, and the PN junction can withstand a higher reverse bias under the same peak electric field, thereby improving the gate electrode breakdown voltage of the device; but at the same time, electric field concentration still exists. By embedding the field plate structure, an additional potential control layer is introduced in the electric field concentration area of ​​the device to adjust the electric field distribution, which significantly reduces the edge electric field concentration under the gate electrode; at the same time, the built-in electric field in the reverse biased PN junction can deplete holes to avoid current crowding at the boundary between the passivation layer and the PN junction. The more uniform current distribution significantly increases the gate electrode breakdown voltage of the device and improves the gate electrode reliability of the device.

[0052] The present invention forms a delta-doped layer and a spacer layer by performing delta doping in the barrier layer, thereby effectively improving the carrier concentration at the channel layer; in addition, the dielectric layer above the barrier layer effectively reduces the defect state on the device surface, reduces the leakage current of the device, and alleviates the current collapse effect.

[0053] The present invention effectively realizes an enhancement-mode device, and on this basis, improves the gate electrode breakdown voltage of the device, increases the gate electrode voltage swing of the device, and improves the reliability and practicability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0055] Figure 1 It is a schematic structural diagram of a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present invention.

[0056] Figure 2a It is a schematic diagram of preparing a substrate in the process of preparing a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present invention.

[0057] Figure 2bIt is a schematic diagram of preparing a channel layer in the process of preparing a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present invention.

[0058] Figure 2c It is a schematic diagram of preparing a spacer layer during the preparation process of a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present invention.

[0059] Figure 2d It is a schematic diagram of preparing a delta-doped layer in the process of preparing a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present invention.

[0060] Figure 2e It is a schematic diagram of preparing a barrier layer in the process of preparing a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present invention.

[0061] Figure 2f The present invention provides a PN junction gate gallium oxide-based MODFET device provided in an embodiment of the present invention. 2 Schematic diagram of etching both ends of the barrier layer as a mask.

[0062] Figure 2g It is a schematic diagram of etching a first groove in a process of preparing a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present invention.

[0063] Figure 2h It is a schematic diagram of preparing a first ohmic contact region and a second ohmic contact region in a process of preparing a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present invention.

[0064] Figure 2i It is a schematic diagram of preparing a P-type gallium nitride layer in the process of preparing a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present invention.

[0065] Figure 2j It is a schematic diagram of etching a middle groove during the preparation process of a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present invention.

[0066] Figure 2k It is a schematic diagram of preparing an N-type gallium nitride layer in the process of preparing a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present invention.

[0067] Figure 2l It is a schematic diagram of etching a second groove, a third groove and a fourth groove in a dielectric layer during the preparation process of a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present invention.

[0068] Figure 2mIt is a schematic diagram of preparing a source electrode and a drain electrode in a process of preparing a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present invention.

[0069] Figure 2n It is a schematic diagram of preparing a gate electrode in the process of preparing a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present invention.

[0070] Description of the numbers in the figure:

[0071] 1-substrate, 2-channel layer, 3-spacer layer, 4-δ-doped layer, 5-barrier layer, 6-first ohmic contact region, 7-second ohmic contact region, 8-PN junction structure, 81-P-type gallium nitride layer, 82-N-type gallium nitride layer, 9-dielectric layer structure, 91-first dielectric layer, 92-second dielectric layer, 10-source electrode, 11-drain electrode, 12-gate electrode, 13-first groove, 14-second groove, 15-third groove, 16-fourth groove, 17-middle groove. DETAILED DESCRIPTION

[0072] The present invention will be further described in detail below in conjunction with the accompanying drawings and examples. It is particularly noted that the following examples are only used to illustrate the present invention, but are not intended to limit the scope of the present invention. Similarly, the following examples are only partial embodiments of the present invention rather than all embodiments, and all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present invention.

[0073] The invention discloses a PN junction gate gallium oxide-based MODFET device, which is reliable in implementation, can effectively reduce gate electrode leakage current and improve gate electrode breakdown voltage and device reliability. The device has a field plate embedded in the PN junction gate gallium oxide-based MODFET device.

[0074] See also Figure 1 The present invention provides a PN junction gate gallium oxide-based MODFET device, which comprises, from bottom to top, a substrate 1, a channel layer 2, a spacer layer 3, a delta-doped layer 4 and a barrier layer 5, wherein the widths of the substrate 1 and the channel layer 2 are equal, that is, the edges overlap; the widths of the spacer layer 3, the delta-doped layer 4 and the barrier layer 5 are equal, and the width of the channel layer 2 is greater than the width of the spacer layer 3; and further comprises:

[0075] A first ohmic contact region 6 is arranged on one side of the end surface of the spacer layer 3, the delta-doped layer 4 and the barrier layer 5;

[0076] A second ohmic contact region 7 is arranged on the other side of the end surface of the spacer layer 3, the delta-doped layer 4 and the barrier layer 5; the heights of the first ohmic contact region 6 and the second ohmic contact region 7 are higher than the upper surface of the barrier layer 5;

[0077] A PN junction structure 8, arranged on a portion of the surface of the barrier layer 5;

[0078] A dielectric layer structure 9 is arranged across the barrier layer 5, the PN junction structure 8, the first ohmic contact region 6 and the second ohmic contact region 7;

[0079] A source electrode 10, disposed on the first ohmic contact region 6;

[0080] A drain electrode 11 is arranged on the second ohmic contact region 7;

[0081] The gate electrode 12 is arranged on the PN junction structure 8 and the dielectric layer structure 9. The metal at the upper end of the gate electrode 12 extends to the two ends of the dielectric layer structure 9 located above the PN junction structure 8 to form a field plate structure. The field plate structure can be completed simultaneously with the preparation of the gate electrode 12; wherein the width of the upper end of the gate electrode 12 is equal to the distance between the left and right edges of the dielectric layer structure 9 located above the PN junction structure 8, that is, the edges overlap.

[0082] The specific functions of each structure of the device are:

[0083] Substrate 1:

[0084] The gallium oxide substrate 1 is the basis for the epitaxial growth of the channel layer 2 and provides the physical support required for crystal growth. The lattice matching and thermal expansion coefficient of the gallium oxide of the substrate 1 material are consistent with those of the epitaxial gallium oxide material forming the channel layer 2, which helps to achieve high-quality homogeneous epitaxy and promote its application in the field of power electronics.

[0085] Channel layer 2:

[0086] Channel layer 2 participates in the formation of heterojunction, Ga 2 O 3 A heterojunction is formed with AlGaO. Due to spontaneous polarization and piezoelectric polarization effects, a 2DEG with high electron concentration and high mobility is generated at the interface. At the same time, channel layer 2 is the transmission channel of the two-dimensional electron gas (2DEG), which is responsible for carrying the current flow in the device; the 2DEG concentration in channel layer 2 directly affects the threshold voltage of the device. By optimizing the parameters of channel layer 2, such as thickness and doping concentration, the density of 2DEG can be adjusted, thereby affecting the turn-on and turn-off characteristics of the device. The material and structural design of channel layer 2 have an important influence on the power handling capacity of the device. Ga 2 O 3 As an ultra-wide bandgap material, its high critical breakdown field strength helps to improve the power handling capability of the device.

[0087] Spacer layer 3:

[0088] The spacer layer 3 participates in the formation of the heterojunction, Ga 2 O 3A heterojunction is formed with AlGaO. In addition, the spacer layer 3 can reduce the influence of ion scattering on the mobility and concentration of 2DEG in the channel, thereby optimizing the performance of the device.

[0089] Delta doped layer 4:

[0090] The introduction of the delta-doped layer 4 can avoid the formation of undesirable parallel conductive paths in the channel layer 2, and thus can effectively increase the concentration of 2DEG formed at the heterojunction interface, thereby increasing the surface concentration and mobility of carriers and improving the conductive performance of the device.

[0091] Barrier layer 5:

[0092] The barrier layer 5 and the dielectric layer work together to help reduce the leakage current of the gate electrode 12 and improve the breakdown voltage. The quality of the barrier layer 5, especially the defects and trap states therein, will affect the current collapse effect of the device under dynamic working conditions. By optimizing the material and structure of the channel layer 2, the current collapse can be reduced and the dynamic performance of the device can be improved.

[0093] First ohmic contact area 6, second ohmic contact area 7:

[0094] The first ohmic contact region 6 and the second ohmic contact region 7 can reduce the barrier height between the semiconductor and the metal contact, improve the ohmic contact performance of the source and drain regions of the device, thereby achieving low-resistance ohmic contact and reducing the difficulty of the ohmic contact process of the source electrode 10 and the drain electrode 11.

[0095] PN junction structure 8:

[0096] P-type semiconductors are formed by doping intrinsic semiconductors with trivalent elements, which replace tetravalent elements in the semiconductor lattice and generate holes. N-type semiconductors are formed by doping pentavalent elements, which provide additional electrons in the lattice. When P-type and N-type semiconductors come into contact, due to the concentration gradient, free electrons in the N-type semiconductor diffuse toward the P-type semiconductor, while holes in the P-type semiconductor diffuse toward the N-type semiconductor. As electrons and holes diffuse, they recombine near the contact interface, resulting in a decrease in the charge carrier concentration in that region, forming a space charge region (also called a depletion region) where there are no free charge carriers. The formation of the space charge region results in a built-in electric field on both sides of the PN junction, which is directed from the N-type semiconductor to the P-type semiconductor, and its function is to hinder further diffusion processes. When a forward bias is applied to the PN junction (the P-type terminal is connected to the positive electrode and the N-type terminal is connected to the negative electrode), the built-in electric field is weakened, allowing more electrons and holes to be injected into each other's region, thereby increasing the forward current. On the contrary, when a reverse bias is applied (the P-type terminal is connected to the negative electrode and the N-type terminal is connected to the positive electrode), the built-in electric field is enhanced, which inhibits the diffusion of charge carriers and results in a very small reverse current.

[0097] P-type gallium nitride is grown on the barrier layer 5, and a thin N-type gallium nitride epitaxial layer is added on top of the P-type gallium nitride to form a PN junction as part of the gate electrode 12. The P-type gallium nitride layer 81 can deplete electrons and effectively block the 2DEG channel below, and the N-type gallium nitride layer 82 can form a PN junction with the P-type gallium nitride layer 81 to generate a built-in electric field to regulate the depletion layer. In this solution, the N-type gallium nitride layer 82 is in contact with the gate electrode 12. When the PN junction is reverse biased, the 2DEG channel below is depleted, the diffusion of carriers is suppressed, and the threshold voltage is right-biased. Moreover, since the PN junction depletion region extends to the N side and the P side, the device exhibits a lower gate electrode 12 leakage current, and the PN junction can withstand a higher reverse bias under the same peak electric field, thereby increasing the gate electrode 12 breakdown voltage of the device.

[0098] Dielectric layer structure 9:

[0099] The dielectric layer can reduce defect states on the device surface, reduce leakage current of the device, and increase the breakdown voltage of the device, thereby improving the electrical characteristics of the device. The passivation layer helps protect the device from environmental factors such as humidity and temperature changes, thereby improving the long-term stability and reliability of the device. In addition, the dielectric layer can enable the extended gate electrode 12 to form a field plate structure.

[0100] Source electrode 10, drain electrode 11:

[0101] The source electrode 10 and the drain electrode 11 are channels for current to enter and leave the semiconductor device. The stacked metal is used to form an ohmic contact and form a closed circuit through the channel layer 2 for current transmission.

[0102] Gate electrode 12:

[0103] The gate electrode 12 controls the current flow between the source electrode 10 and the drain electrode 11 through an electric field. The change of the gate electrode 12 voltage can adjust the formation and disappearance of the channel, thereby controlling the conductive state of the device. In an enhancement-type device, a forward voltage needs to be applied to the gate electrode 12 to induce and form a conductive channel. In a depletion-type device, the channel exists even if the gate electrode 12 voltage is zero, but the gate electrode 12 voltage can further adjust the conductivity of the channel.

[0104] Field plate structure:

[0105] The field plate structure can increase the breakdown voltage of the device by reducing the electric field at the edge of the gate electrode 12. Devices using the field plate structure can reduce the probability of current collapse, because the field plate structure can reduce the probability of electrons tunneling from the barrier layer 5 between the gate electrode 12 and the drain electrode 11 to the surface trap, hindering the formation of the virtual gate effect, weakening the virtual gate effect, and effectively suppressing the current collapse effect of the device.

[0106] The function of the field plate structure embedded in the PN junction structure 8 is as follows:

[0107] The addition of a PN junction under the gate electrode 12 can withstand a higher reverse bias under the same peak electric field, but at the same time, electric field concentration still exists. By embedding the field plate structure, the edge electric field peak under the gate electrode 12 is significantly reduced; at the same time, the built-in electric field in the reverse biased PN junction can deplete holes and prevent current from crowding at the boundary between the dielectric layer and the PN junction. A more uniform current distribution significantly increases the breakdown voltage of the gate electrode 12 of the device and improves the reliability of the gate electrode 12 of the device.

[0108] In this embodiment, the PN junction structure 8 includes a P-type gallium nitride layer 81 and an N-type gallium nitride layer 82, the P-type gallium nitride layer 81 is arranged on a partial surface of the barrier layer 5, the upper surface of the P-type gallium nitride layer 81 is provided with a middle groove 17, and the N-type gallium nitride layer 82 is arranged in the middle groove 17 on the upper surface of the P-type gallium nitride layer 81.

[0109] In this embodiment, the dielectric layer structure 9 includes a first dielectric layer 91 and a second dielectric layer 92. The first dielectric layer 91 is arranged on the upper surface of the first ohmic contact area 6 and on the upper surface of the barrier layer 5 between the right end of the first ohmic contact area 6 and the left end surface of the PN junction structure 8; the second dielectric layer 92 is arranged on the upper surface of the second ohmic contact area 7 and on the upper surface of the barrier layer 5 between the left end of the second ohmic contact area 7 and the right end surface of the PN junction structure 8. The first dielectric layer 91 and the second dielectric layer 92 extend upward near the side of the PN junction structure 8 and cover the upper surface of the P-type gallium nitride layer 81 of the PN junction structure 8.

[0110] In this embodiment, the spacing between the PN junction structure 8 and the first ohmic contact area 6 is smaller than the spacing between the PN junction structure 8 and the second ohmic contact area 7; the reason for this setting is: when the spacing between the gate electrode 12 above the PN junction structure 8 and the drain electrode 11 above the second ohmic contact area 7 is too close, a significant electric field concentration phenomenon will occur; making the spacing between the PN junction structure 8 and the first ohmic contact area 6 smaller than the spacing between it and the second ohmic contact area 7 is beneficial to alleviating the electric field concentration at the drain electrode 11 end and improving the voltage resistance performance of the device.

[0111] In this embodiment, the substrate 1 is a high-resistance or semi-insulating β-Ga 2 O 3 The doping element type includes any one of Mg, Fe, Zn, N and P; the doping concentration is 1×10 18 ~5×10 18 / cm -3 Among them, high resistance requires that the resistivity of substrate 1 exceeds 10 9 Ω·cm, high resistance or semi-insulating substrate 1 can effectively reduce leakage current, thereby improving the off-state leakage performance of the device;

[0112] The channel layer 2 is unintentionally doped with β-Ga 2 O 3 Channel layer 2;

[0113] The spacer layer 3 is N-type doped β-(AlGa) 2 O 3 The doping element type includes any one of Si, Sn and Ge, and the doping concentration is 1×10 18 ~5×10 18 / cm -3 , the selection of doping concentration within this range can balance the compromise between device on-resistance and breakdown voltage; the Al component is 0.15-0.3, and the 2DEG can be increased with the increase of Al component, but the breakdown voltage of the device will also be reduced;

[0114] The delta doped layer 4 is N-type doped β-(AlGa) 2 O 3 , the doping element types include Si, and the doping concentration is 1×10 19 ~5×10 19 / cm -3 , Al component is 0.15~0.3;

[0115] The barrier layer 5 is N-type doped β-(AlGa) 2 O 3 The doping element type includes any one of Si, Sn and Ge, and the doping concentration is 1×10 18 ~5×10 18 / cm -3 , Al component is 0.15~0.3;

[0116] The first ohmic contact region 6 and the second ohmic contact region 7 are both N-type heavily doped β-Ga 2 O 3 The doping element type includes any one of Si, Sn and Ge, and the doping concentration is 1×10 20 ~5×10 20 cm -3 , heavy doping within this concentration range can effectively reduce the difficulty of the device's ohmic contact process and reduce contact resistance. When the doping concentration is too high, the concentration of carriers in the semiconductor material will reach saturation, and the process difficulty will increase;

[0117] The dielectric layer structure 9 is Al 2 O 3 、SiO 2 、Si 3 N 4 and HfO 2Any one of the following is formed, wherein Al 2 O 3 、SiO 2 、Si 3 N 4 The process cost is low. As a passivation layer material, it can still provide sufficient insulation protection at a thin layer thickness and reduce the occurrence of leakage. 2 The dielectric constant is higher, with better insulation performance and thermal stability;

[0118] The P-type gallium nitride layer 81 in the PN junction structure 8 is P-type doped, and the doping element type includes Mg, and the doping concentration is 1×10 18 ~5×10 19 / cm -3 The reason for selecting this range is that: if the doping concentration of the P-type gallium nitride layer 81 is too high, it will affect the hole injection of the gate electrode 12, causing the current density of the channel layer 2 to decrease; if the doping concentration is too low, the blocking effect on electrons is insufficient, which may cause the normally-off type of the device to fail; the N-type gallium nitride layer 82 is N-type doped, and its doping element type includes any one of Si, Sn and Ge, and its doping concentration is 1×10 18 ~2×10 19 / cm -3 The reason for selecting this range is that when the doping concentration of the N-type gallium nitride layer 82 is too high, the device may also fail in the normally-off mode, while when the doping concentration is too low, the depletion effect of the PN junction structure 8 may be insufficient.

[0119] The source electrode 10 and the drain electrode 11 are both formed by stacking two metals of any one of Ni, Ti and Al and Au; for example, Ni and Au are stacked, or Ti and Au are stacked, or Al and Au are stacked. The reason for this selection is that metal Ni, Ti or Al generates compounds after annealing to form good ohmic contact performance, while metal Au provides stability and corrosion resistance.

[0120] The gate electrode 12 is formed by stacking two metals, Ni and Au, or stacking two metals, Ti and Au. The reason for this selection is that the stacking of two metals, Ni and Au, or the stacking of two metals, Ti and Au, can provide a better Schottky contact.

[0121] In this embodiment, the thickness of the substrate 1 is 250-600um. The reason for selecting this range is that the thickness of the substrate 1 directly affects the thermal conductivity of the power device. A thicker substrate 1 can improve thermal conductivity, thereby dissipating heat more effectively and improving device reliability. However, an overly thick substrate 1 will increase the resistance of the substrate 1 and affect the current transmission efficiency of the device. Therefore, as a preferred implementation option, preferably, the thickness of the substrate 1 is 250-600um.

[0122] The thickness of the channel layer 2 is 150 to 360 nm. The reason for selecting this range is that a thicker channel layer 2 can reduce the resistance of the device, thereby improving the current carrying capacity and reducing power consumption; but an overly thick channel layer 2 will increase the switching time of the device, thereby reducing the switching frequency, and a thicker channel layer 2 is more prone to defects, increasing the process time and cost. Therefore, as a preferred implementation option, preferably, the thickness of the channel layer 2 is 150 to 360 nm;

[0123] The thickness of the spacer layer 3 is 3 to 8 nm. The reason for selecting this range is that the thickness of the spacer layer 3 is determined by the distance of the δ-doped layer 4 from the two-dimensional electron gas interface. When the spacer layer 3 is thicker, the influence of the δ-doped layer 4 on the two-dimensional electron gas interface is reduced, and the increase in electron density and mobility is not significant. When the spacer layer 3 is thinner, the δ-doped layer 4 is too close to the interface, which will lead to uneven distribution of electric field intensity in the 2DEG region and increase carrier scattering. Therefore, as a better implementation choice, preferably, the thickness of the spacer layer 3 is 3 to 8 nm.

[0124] The thickness of the δ-doped layer 4 is 1-2 nm. The reason for selecting this range is that a thinner δ-doped layer 4 increases the electron density and mobility, and significantly increases the two-dimensional electron gas at the interface. However, if the δ-doped layer 4 is too thin, it may cause uneven doping effect, increase parasitic capacitance, and affect the switching speed and frequency response of the device. As a preferred implementation option, preferably, the thickness of the δ-doped layer 4 is 1-2 nm.

[0125] The thickness of the barrier layer 5 is 15 to 30 nm. The reason for selecting this range is that the increase in the thickness of the barrier layer 5 can increase the surface density of the 2DEG, but after exceeding a certain thickness, the surface density tends to be saturated; an overly thick barrier layer 5 will increase the parasitic capacitance of the device, which may have an adverse effect on the high-frequency characteristics. As a preferred implementation option, preferably, the thickness of the barrier layer 5 is 15 to 30 nm;

[0126] The thickness of the dielectric layer structure 9 is 2 to 5 nm. The reason for selecting this range is that a thicker dielectric layer can effectively reduce leakage current, but it will also reduce the control ability of the gate electrode 12, and cannot effectively control the current in the channel layer 2, thereby reducing the switching speed and performance of the device; a thinner dielectric layer may produce a higher leakage current at a high voltage, but it can still effectively store and transfer charge at a low voltage, thereby improving the signal response speed of the device. As a preferred implementation option, preferably, the thickness of the dielectric layer is 2 to 5 nm.

[0127] The thickness of the P-type gallium nitride layer 81 in the PN junction structure 8 is 20-100nm. The P-type gallium nitride layer 81 can effectively block electrons and increase the threshold voltage, but an overly thick P-type gallium nitride layer 81 will affect the injection of carriers; when the P-type gallium nitride layer 81 is thin, it cannot produce an effective depletion width with the N-type gallium nitride layer 82, so the selected thickness of the P-type gallium nitride layer 81 is 20-100nm. The thickness of the N-type gallium nitride layer 82 is 10-40nm. An overly thick N-type gallium nitride layer 82 will weaken the blocking effect of the P-type gallium nitride layer 81 on electrons; however, when the N-type gallium nitride layer 82 is thin, it cannot produce an effective depletion width with the P-type gallium nitride layer 81, so the selected thickness of the N-type gallium nitride layer 82 is 10-40nm.

[0128] The thickness of the first ohmic contact region 6 and the second ohmic contact region 7 are both 50 to 100 nm. The total thickness of the first ohmic contact region 6 and the second ohmic contact region 7 should be greater than the sum of the thicknesses of the spacer layer 3, the δ-doped layer 4 and the barrier layer 5 to reduce the leakage current in the channel layer 2. An excessively thick ohmic contact region will increase the distance between the source electrode 10, the drain electrode 11 and the channel layer 2, and reduce the modulation effect of the source electrode 10 and the drain electrode 11 on the channel layer 2.

[0129] like Figure 2a-2n As shown, the present invention also provides a method for preparing a PN junction gate gallium oxide-based MODFET device, which is prepared based on the above-mentioned PN junction gate gallium oxide-based MODFET device, and specifically includes the following steps:

[0130] Step 1, pre-treating the surface of substrate 1 in a reaction chamber; wherein the method for pre-treating the surface of substrate 1 is standard RCA cleaning: before starting growth, heating substrate 1 to remove impurities adsorbed on substrate 1;

[0131] Step 2, homoepitaxially growing a channel layer 2 on the upper surface of the substrate 1; the epitaxial growth method adopts one of MOCVD, MBE and ALD;

[0132] Step 3, heteroepitaxially growing a spacer layer 3 on the upper surface of the channel layer 2; the epitaxial growth method adopts one of MOCVD, MBE and ALD;

[0133] Step 4, homoepitaxially growing a delta-doped layer 4 and a barrier layer 5 on the upper surface of the spacer layer 3 from bottom to top; the epitaxial growth method adopts one of MOCVD, MBE and ALD;

[0134] Step 5, etching the two ends of the barrier layer 5, and continuing to etch the two ends of the delta-doped layer 4 and the spacer layer 3 in the etching direction, until two first grooves 13 are formed on the upper surface of the channel layer 2, and a first ohmic contact region 6 is grown on the first groove 13 at the left end, and a second ohmic contact region 7 is grown on the first groove 13 at the right end; the etching method is specifically as follows: first, a layer of SiO is deposited; 2 , using photolithography to make etching window patterns, and then using RIE equipment to perform SiO 2 Etching to form SiO 2 The mask and barrier layer 5 are etched by ICP or RIE to open holes;

[0135] Step 6, graphically growing a PN junction structure 8 in the middle of the upper surface of the barrier layer 5;

[0136] Step 7, depositing a dielectric layer structure 9 on the surface of the barrier layer 5, the PN junction structure 8, the first ohmic contact region 6 and the second ohmic contact region 7, using one of MOCVD, MBE and ALD as a growth method; and etching the left and right ends and the middle upper surface of the dielectric layer structure 9 respectively, leaving a second groove 14, a third groove 15 and a fourth groove 16 for depositing a source electrode 10, a drain electrode 11 and a gate electrode 12;

[0137] Step 8, depositing a source electrode 10 on the second groove 14, and depositing a drain electrode 11 on the third groove 15; the source electrode 10 and the drain electrode 11 are deposited by electron beam evaporation, and an annealing process is performed to form a good ohmic contact;

[0138] Step 9: depositing a gate electrode 12 on the fourth groove 16 to form a field plate structure on the upper surface of the PN junction structure 8; the gate electrode 12 is deposited by electron beam evaporation to form a good Schottky contact.

[0139] In this embodiment, step 6 is specifically as follows: the PN junction structure 8 includes a P-type gallium nitride layer 81 and an N-type gallium nitride layer 82, and the P-type gallium nitride layer 81 is patterned and grown in the middle of the upper surface of the barrier layer 5, and the patterning method is to coat a photoresist on the surface of the P-type gallium nitride layer 81, expose and develop the photoresist to form a patterned photoresist, and use the patterned photoresist as a mask to etch the P-type gallium nitride layer 81 to form a middle groove 17 located in the middle; and an N-type gallium nitride layer 82 is grown in the middle groove on the upper surface of the P-type gallium nitride layer 81, and the growth height of the N-type gallium nitride layer 82 is flush with the upper surface of the P-type gallium nitride layer 81.

[0140] The above descriptions are only some embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any equivalent device or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A PN junction gate gallium oxide based MODFET device, characterized in that: From bottom to top, it includes: substrate, channel layer, spacer layer, delta doping layer and barrier layer, and also includes: A first ohmic contact region is arranged on one side of the end surface of the spacer layer, the delta-doped layer and the barrier layer; A second ohmic contact region is arranged on the other side of the end surface of the spacer layer, the delta-doped layer and the barrier layer; the height of the first ohmic contact region and the second ohmic contact region is higher than the upper surface of the barrier layer; A PN junction structure is provided on a portion of the surface of the barrier layer; A dielectric layer structure is arranged across the barrier layer, the PN junction structure, the first ohmic contact region and the second ohmic contact region; A source electrode, disposed on the first ohmic contact region; A drain electrode, disposed on the second ohmic contact region; The gate electrode is arranged on the PN junction structure and the dielectric layer structure, and the metal on the upper end of the gate electrode extends to the two ends of the dielectric layer structure located above the PN junction structure to form a field plate structure.

2. A PN junction gate gallium oxide based MODFET device as claimed in claim 1, characterized in that: The PN junction structure includes a P-type gallium nitride layer and an N-type gallium nitride layer, the P-type gallium nitride layer is arranged on a partial surface of the barrier layer, a middle groove is arranged on the upper surface of the P-type gallium nitride layer, and the N-type gallium nitride layer is arranged in the middle groove on the upper surface of the P-type gallium nitride layer.

3. A PN junction gate gallium oxide based MODFET device as claimed in claim 2, characterized in that: The dielectric layer structure includes a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is arranged on the upper surface of the first ohmic contact region and on the upper surface of the barrier layer between the right end of the first ohmic contact region and the left end surface of the PN junction structure; the second dielectric layer is arranged on the upper surface of the second ohmic contact region and on the upper surface of the barrier layer between the left end of the second ohmic contact region and the right end surface of the PN junction structure, and the first dielectric layer and the second dielectric layer extend upward near the side of the PN junction structure and cover the upper surface of the P-type gallium nitride layer of the PN junction structure.

4. A PN junction gate gallium oxide based MODFET device as claimed in claim 1, characterized in that: The distance between the PN junction structure and the first ohmic contact region is smaller than the distance between the PN junction structure and the second ohmic contact region.

5. A PN junction gate gallium oxide based MODFET device as claimed in claim 1, characterized in that: The widths of the substrate and the channel layer are equal, the widths of the spacer layer, the delta-doped layer and the barrier layer are equal, and the width of the channel layer is greater than the width of the spacer layer; the width of the upper end of the gate electrode is equal to the distance between the left and right edges of the dielectric layer structure located above the PN junction structure.

6. A PN junction gate gallium oxide based MODFET device as claimed in claim 2, characterized in that: The substrate is high-resistance or semi-insulating β-Ga2O3, and the doping element type includes any one of Mg, Fe, Zn, N and P; the doping concentration is 1×10 18 ~5×10 18 / cm -3 ; The channel layer is an unintentionally doped β-Ga2O3 channel layer; The spacer layer is N-type doped β-(AlGa)2O3, and the doping element type includes any one of Si, Sn and Ge, and the doping concentration is 1×10 18 ~5×10 18 / cm -3 , Al component is 0.15~0.3; The δ-doped layer is N-type doped β-(AlGa)2O3, and its doping element types include Si, and its doping concentration is 1×10 19 ~5×10 19 / cm -3 , Al component is 0.15~0.3; The barrier layer is N-type doped β-(AlGa)2O3, and the doping element type includes any one of Si, Sn and Ge, and the doping concentration is 1×10 18 ~5×10 18 / cm -3 , Al component is 0.15~0.3; The first ohmic contact region and the second ohmic contact region are both N-type heavily doped β-Ga2O3, and the doping element type includes any one of Si, Sn and Ge, and the doping concentration is about 1×10 20 ~5×10 20 cm -3 ; The P-type gallium nitride layer in the PN junction structure is P-type doped, and the doping element type includes Mg, and the doping concentration is 1×10 18 ~5×10 19 / cm -3 The N-type gallium nitride layer is N-type doped, and the doping element type includes any one of Si, Sn and Ge, and the doping concentration is 1×10 18 ~2×10 19 / cm -3 ; The dielectric layer structure is formed by any one of Al2O3, SiO2, Si3N4 and HfO2; The source electrode and the drain electrode are both formed by stacking two metals in which any one of Ni, Ti and Al and Au are combined; The gate electrode is formed by stacking two metals, Ni and Au, or stacking two metals, Ti and Au.

7. A PN junction gate gallium oxide based MODFET device as claimed in claim 2, characterized in that: The thickness of the substrate is 250-600um; The thickness of the channel layer is 150 to 360 nm; The thickness of the spacer layer is 3 to 8 nm; The thickness of the delta-doped layer is 1 to 2 nm; The thickness of the barrier layer is 15 to 30 nm; The thickness of the dielectric layer structure is 2 to 5 nm; The thickness of the P-type gallium nitride layer in the PN junction structure is 20 to 100 nm, and the thickness of the N-type gallium nitride layer is 10 to 40 nm; The thickness of the first ohmic contact region and the second ohmic contact region are both 50-100 nm.

8. A method for preparing a PN junction gate gallium oxide-based MODFET device, characterized in that: The preparation method of a PN junction gate gallium oxide-based MODFET device according to any one of claims 1 to 7 specifically comprises the following steps: Step 1, pre-treating the substrate surface in a reaction chamber; Step 2, homoepitaxially growing a channel layer on the upper surface of the substrate; Step 3, heteroepitaxially growing a spacer layer on the upper surface of the channel layer; Step 4, homoepitaxially growing a delta-doped layer and a barrier layer from bottom to top on the upper surface of the spacer layer; Step 5, etching the two ends of the barrier layer, and continuing to etch the two ends of the delta-doped layer and the spacer layer in sequence along the etching direction until two first grooves are formed on the upper surface of the channel layer, and growing a first ohmic contact region on the first groove at the left end, and growing a second ohmic contact region on the first groove at the right end; Step 6, graphically growing a PN junction structure in the middle of the upper surface of the barrier layer; Step 7, depositing a dielectric layer structure on the surface of the barrier layer, the PN junction structure, the first ohmic contact region and the second ohmic contact region, and etching the left and right ends and the middle upper surface of the dielectric layer structure respectively to leave a second groove, a third groove and a fourth groove for depositing a source electrode, a drain electrode and a gate electrode; Step 8, depositing a source electrode on the second groove, and depositing a drain electrode on the third groove; Step 9: depositing a gate electrode on the fourth groove to form a field plate structure on the upper surface of the PN junction structure.

9. The method for preparing a PN junction gate gallium oxide-based MODFET device according to claim 8, characterized in that: The step 6 specifically comprises: the PN junction structure comprises a P-type gallium nitride layer and an N-type gallium nitride layer, and the P-type gallium nitride layer is patterned and grown in the middle of the upper surface of the barrier layer, wherein the patterning method comprises coating a photoresist on the surface of the P-type gallium nitride layer, exposing and developing the photoresist to form a patterned photoresist, and etching the P-type gallium nitride layer using the patterned photoresist as a mask to form a middle groove located in the middle; An N-type gallium nitride layer is grown in the middle groove on the upper surface of the P-type gallium nitride layer, and the growth height of the N-type gallium nitride layer is flush with the upper surface of the P-type gallium nitride layer.

10. The method for preparing a PN junction gate gallium oxide-based MODFET device according to claim 8, characterized in that: The method for pre-treating the substrate surface in step 1 is standard RCA cleaning: before starting growth, the substrate is heated to remove impurities adsorbed on the substrate; the epitaxial growth method adopts one of MOCVD, MBE and ALD.

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