Display device

Abstract

An embodiment of the present specification discloses a display device including: a display panel including a display area and a non-display area surrounding the display area; and a metal dam disposed in the non-display area to surround at least three surfaces of the display panel, in which the display panel includes: a substrate; the pixel driving circuit is arranged on the substrate; and a light emitting element driven by the pixel driving circuit, the metal dam may be spaced apart from an edge of the display panel by a predetermined distance, the metal dam may be formed of a plurality of metal layers connected through at least one hole, and the metal dam may include a first metal dam, a second metal dam, and a third metal dam, a first metal dam, a second metal dam, and a third metal dam are disposed in the non-display area while surrounding at least three surfaces of the display area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 2023-0103083, filed on August 7, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments relate to a display device using an inorganic light emitting diode as a light source. Background Art

[0004] Electroluminescent display devices include organic light emitting diode display devices in which organic light emitting diodes (hereinafter referred to as "OLEDs") are arranged and inorganic light emitting diode display devices (hereinafter referred to as "LED display devices") in which inorganic light emitting diodes (hereinafter referred to as "LEDs") are arranged.

[0005] Since the electroluminescent display device uses a self-luminous element to display an image, the electroluminescent display does not require a separate light source such as a backlight unit, and thus can be implemented in a thin and various forms.

[0006] The OLED display device requires a design for preventing penetration of oxygen and moisture, since the penetration of moisture and oxygen may cause an oxidation phenomenon between an organic light emitting layer and an electrode.

[0007] Recently, as an example of an LED display device, a micro LED display device in which a micro LED is arranged in a pixel has attracted attention as a next-generation display device. The micro LED may be an inorganic LED having a size of 100 μm or less. The micro LED may be manufactured by a separate semiconductor process, transferred to a pixel located on a display panel substrate of the display device, and arranged in a sub-pixel for each color.

[0008] Each micro-LED can be connected to an anode and a cathode to receive power. Summary of the invention

[0009] Embodiments are directed to providing a display device in which a crack phenomenon on an organic layer and delamination of a metal layer due to penetration of moisture and heat through an edge region of a display panel can be prevented.

[0010] The objects of the present disclosure are not limited to the above objects, and other objects not mentioned will be clearly understood by those skilled in the art from the following description.

[0011] A display device according to an embodiment of the present disclosure includes: a display panel, which includes a display area and a non-display area surrounding the display area; and a metal dam, which is arranged in the non-display area to surround at least three surfaces of the display panel, wherein the display panel includes a substrate, a pixel driving circuit arranged on the substrate, and a light-emitting element driven by the pixel driving circuit.

[0012] According to the present disclosure, parasitic capacitance generated in a region where a cathode electrode and a signal wiring overlap can be reduced, and an increase in resistance of the cathode electrode can be improved, thereby achieving low-power driving.

[0013] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a diagram showing a display device according to one embodiment of the present specification.

[0015] Figure 2 yes Figure 1 Magnified view of area A in the middle.

[0016] Figure 3 is a diagram showing a partial area of ​​a pixel.

[0017] Figure 4 is along Figure 3 Cross-sectional view along line II'.

[0018] Figure 5 is along Figure 3 Cross-sectional view along line II-II'.

[0019] Figure 6 is along Figure 3 Cross-sectional view along line III-III'.

[0020] Figure 7 is a cross-sectional view showing an example in which a main light emitting element and a sub light emitting element are electrically connected to a pixel driving circuit.

[0021] Figure 8 is a diagram illustrating a display device according to another embodiment of the present specification.

[0022] Fig. 9 is along Figure 8 Cross-sectional view along line IV-IV'.

[0023] Fig.10 is a diagram showing a state in which stress concentrates on the second electrode provided in the through hole.

[0024] Fig.11 It is shown Figure 8 FIG. 1 is a diagram of a first modified example of a display device.

[0025] Fig.12 It is shown Figure 8 FIG. 1 is a diagram of a second modified example of a display device.

[0026] FIG. 13A to FIG. 13F is a diagram illustrating a method of manufacturing a display device according to an embodiment of the present specification.

[0027] Fig.14 is a diagram showing a modified example of the second electrode.

[0028] Fig.15 is along Fig.14 Cross-sectional view along line V-V'.

[0029] Fig.16 is along Figure 1 Cross-sectional view along line VI-VI′.

[0030] Fig.17 is a plan view showing a display device according to one embodiment of the present disclosure.

[0031] Fig.18A , Fig.18B and Fig. 18C is along Fig.17 Cross-sectional view along line VII-VII'. DETAILED DESCRIPTION

[0032] The advantages and features of the present disclosure and the methods for achieving the advantages and features will become clear with reference to the embodiments described in detail below in conjunction with the accompanying drawings. The present disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms, and these embodiments are provided only to make the disclosure of the present disclosure complete and fully inform the technical personnel in the field to which the present disclosure belongs of the scope of the present disclosure, and the present disclosure is limited only by the scope of the attached claims.

[0033] Since the shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings used to describe the embodiments of the present disclosure are illustrative, the present disclosure is not limited to the contents shown. Throughout the specification, the same reference numerals indicate the same parts. In addition, when describing the present disclosure, when it is determined that the detailed description of the related known technology may unnecessarily obscure the main points of the present disclosure, its detailed description will be omitted.

[0034] When “including,” “comprising,” “having,” and “consisting of…” described in this specification are used, other components may be added unless “only” is used. When a component is expressed in the singular, it can be construed as plural components unless explicitly stated otherwise.

[0035] In interpreting the components, even when there is no separate explicit description, the components are interpreted as including an error tolerance.

[0036] When describing the position or interconnection relationship between two components, such as "on", "above", "below", "beside", "connected or coupled to", "crossing or intersecting", etc., unless the term "immediately" or "directly" is described, one or more other components may be inserted between the components.

[0037] When the terms "after", "subsequently", "then", "before", etc. are used to describe a time relationship, it may include non-sequential cases unless the terms "immediately" or "directly" are used.

[0038] In order to distinguish components, "first", "second", etc. may be used before the name of the component, but its function or structure is not limited by the ordinal number or the component name. For ease of description, the ordinal number of the name of the same component may be different between the embodiments.

[0039] The following embodiments may be partially or completely coupled or combined, and various technical interactions and drives are possible. The embodiments may be implemented independently of each other, and may be implemented together in an associated relationship.

[0040] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0041] A display device according to an embodiment of the present specification includes: a display panel including a display area for displaying an image or a display screen; and a pixel driving circuit for driving pixels of the display panel. The display area includes a pixel area where pixels are set. The pixel area includes a plurality of light-emitting areas. A light-emitting element is set in each of the light-emitting areas. The pixel driving circuit can be embedded in the display panel.

[0042] Figure 1 is a diagram showing a display device according to one embodiment of the present specification. Figure 2 yes Figure 1 Magnified view of area A in the middle. Figure 3 is a diagram showing a partial area of ​​a pixel.

[0043] Reference Figure 1 and Figure 2 , a display device 100 according to an embodiment of the present specification includes a display panel that visually displays an input image. The display panel may include a display area AA that displays an image and a non-display area NA that does not display an image. Various lines and driving circuits may be installed in the non-display area NA and a pad portion PAD to which an integrated circuit, a printed circuit, etc. are connected.

[0044] The plurality of light emitting elements 10 disposed in the display area AA and forming the pixel PXL may be micro inorganic light emitting elements. The inorganic light emitting elements may be grown on a silicon wafer and then attached to the display panel through a transfer process.

[0045] The transfer process of the light emitting element 10 may be performed for each pre-divided area. Figure 1 The display area AA is shown to be divided into nine transfer areas ST, but the size or number of divisions of the transfer area is not limited thereto. The transfer process may be performed sequentially or simultaneously on the first to ninth transfer areas ST. The blue light emitting element 10, the green light emitting element 10, and the red light emitting element 10 may each be sequentially transferred to the transfer area ST.

[0046] A data driving circuit or a gate driving circuit may be provided in the non-display area NA, and a line through which a control signal for controlling the driving circuit is provided may be provided. Here, the control signal may include various timing signals including a clock signal, an input data enable signal, and a synchronization signal, and may be received through the pad portion PAD.

[0047] The pixel PXL can be driven by a pixel driving circuit. The pixel driving circuit can drive multiple pixels by receiving a driving voltage, an image signal (digital signal), a synchronization signal synchronized with the image signal, etc. and outputting an anode voltage and a cathode voltage of the light-emitting element 10. The driving voltage (anode voltage) can be a high potential voltage EVDD. The cathode voltage can be a low potential voltage EVSS usually applied to the pixel. The anode voltage can be a voltage corresponding to the pixel data value of the image signal. The pixel driving circuit can be arranged in the non-display area NA or below the display area AA.

[0048] Each pixel in the pixel PXL may include a plurality of sub-pixels, each of which has a different color. For example, the plurality of pixels may include: a red sub-pixel in which a light-emitting element 10 for emitting light having a red wavelength is provided; a green sub-pixel in which a light-emitting element 10 for emitting light having a green wavelength is provided; and a blue sub-pixel in which a light-emitting element 10 for emitting light having a blue wavelength is provided. The plurality of pixels may also include a white pixel.

[0049] Reference Figure 2 and Figure 3, a plurality of pixels PXL may be continuously arranged in a first direction (X-axis direction) and a second direction (Y-axis direction). In the pixels of the display area AA, a plurality of sub-pixels of the same color may be arranged. For example, each of the plurality of pixels may include: a first red sub-pixel, in which a 1-1 light-emitting element 11a is used to emit light having a red wavelength; a second red sub-pixel, in which a 1-2 light-emitting element 11b is used to emit light having a red wavelength; a first green sub-pixel, in which a 2-1 light-emitting element 12a is used to emit light having a green wavelength; a second green sub-pixel, in which a 2-2 light-emitting element 12b is used to emit light having a green wavelength; a first blue sub-pixel, in which a 3-1 light-emitting element 13a is used to emit light having a blue wavelength; and a second blue sub-pixel, in which a 3-2 light-emitting element 13b is used to emit light having a blue wavelength. The 1-1 light emitting element 11a, the 2-1 light emitting element 12a, and the 3-1 light emitting element 13a may be interpreted as main light emitting elements, and the 1-2 light emitting element 11b, the 2-2 light emitting element 12b, and the 3-2 light emitting element 13b may be interpreted as sub light emitting elements.

[0050] A sub-pixel includes one or more light-emitting elements. In the case where a sub-pixel includes multiple light-emitting elements, when one light-emitting element fails, the brightness of the sub-pixel can be adjusted by increasing the brightness of the remaining light-emitting elements. However, the present disclosure is not necessarily limited thereto, and a sub-pixel may include only one light-emitting element.

[0051] A plurality of first electrodes 161 may be each disposed below the light emitting element 10, and may be selectively connected to a plurality of signal lines TL1 to TL6 through a connection portion 161a (also referred to herein as an extension portion 161a). A high potential voltage may be applied to the pixel driving circuit through the signal lines TL1 to TL6. The signal lines TL1 to TL6 and the first electrodes 161 may be formed as an integrated electrode pattern during an electrode patterning process.

[0052] For example, the first signal line TL1 may be connected to the anode of the first red sub-pixel, and the second signal line TL2 may be connected to the anode of the second red sub-pixel. The third signal line TL3 may be connected to the anode of the first green sub-pixel, and the fourth signal line TL4 may be connected to the anode of the second green sub-pixel. The fifth signal line TL5 may be connected to the anode of the first blue sub-pixel, and the sixth signal line TL6 may be connected to the anode of the second blue sub-pixel. When one sub-pixel includes only one light-emitting element, the number of signal lines TL may be reduced by half.

[0053] The second electrode 170 may be a cathode electrode that is disposed in each row and applies a cathode voltage to the light emitting elements 10 that are continuously disposed in the first direction (X-axis direction). A plurality of second electrodes 170 may be arranged to be spaced apart from each other in the second direction (Y-axis direction). A plurality of second electrodes 170 may be connected to the cathode voltage through the contact electrode 163. A plurality of second electrodes 170 may each be electrically connected to the contact electrode 163. However, the present disclosure is not limited thereto, and the second electrode 170 is not divided into a plurality of second electrodes, and may be formed as one electrode layer used as a common electrode.

[0054] Figure 4 is along Figure 3 Cross-sectional view along line II'. Figure 5 is along Figure 3 Cross-sectional view along line II-II'. Figure 6 is along Figure 3 Cross-sectional view along line III-III'. Figure 7 is a cross-sectional view showing an example in which two light emitting elements are connected to a pixel driving circuit.

[0055] Reference Figures 3 to 5 According to the present embodiment, the display device includes: a plurality of first electrodes 161 and a contact electrode 163 arranged on a substrate 110, a plurality of light emitting elements 10 arranged on the plurality of first electrodes 161, a first optical layer 141 arranged between the plurality of light emitting elements 10, and a second electrode 170 arranged on the plurality of light emitting elements 10.

[0056] The substrate 110 may be made of flexible plastic. For example, the substrate 110 may be formed as a single layer or multiple layers made of a material selected from polyimide, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyether sulfone, polyarylate, polysulfone, and cycloolefin copolymer, but is not limited thereto. For example, the substrate 110 may be a ceramic substrate or a glass substrate.

[0057] The pixel driving circuit 20 may be disposed in the display area AA on the substrate 110. The pixel driving circuit 20 may include a plurality of thin film transistors using an amorphous silicon semiconductor, a polysilicon semiconductor, or an oxide semiconductor.

[0058] The pixel driving circuit 20 may include at least one driving thin film transistor, at least one switching thin film transistor, and at least one storage capacitor. When the pixel driving circuit 20 includes a plurality of thin film transistors, the pixel driving circuit 20 may be formed on the substrate 110 by a process of manufacturing a thin film transistor (TFT). In an embodiment, the connection of the pixel driving circuit 20 may generally be referred to as being electrically connected to a plurality of thin film transistors of the light emitting element 10.

[0059] The pixel driving circuit 20 may be a driving driver manufactured on a single crystal semiconductor substrate 110 using a process for manufacturing a metal oxide silicon field effect transistor (MOSFET). The driving driver may include a plurality of pixel driving circuits and drive a plurality of sub-pixels. When the pixel driving circuit 20 is implemented as a driving driver, after an adhesive layer is provided on the substrate 110, the driving driver may be mounted on the adhesive layer by a transfer process.

[0060] A buffer layer 121 for covering the pixel driving circuit 20 may be disposed on the substrate 110. The buffer layer 121 may be made of an organic insulating material such as photosensitive acrylic or photosensitive polyimide, but is not limited thereto.

[0061] The buffer layer 121 may be formed by stacking silicon nitride (SiN x ) or silicon oxide (SiO 2 ) or multiple layers formed by stacking an organic insulating material and an inorganic insulating material.

[0062] The insulating layer 122 may be disposed on the buffer layer 121. The insulating layer 122 may be made of an organic insulating material such as photosensitive acrylic or photosensitive polyimide, but is not limited thereto. The connecting wires RT1 and RT2 may be disposed on the buffer layer 121. The connecting wires RT1 and RT2 may be connected to corresponding signal wires TL1 to TL6, or to the signal wires TL1 to TL6. The connecting wires RT1 and RT2 may include a plurality of line patterns disposed on different layers with one or more insulating layers interposed therebetween. The line patterns disposed on different layers may be electrically connected through contact holes passing through the insulating layers.

[0063] A plurality of bank patterns 130 may be provided on the insulating layer 122. At least one light emitting element 10 may be provided on each bank pattern 130. For example, a first light emitting element 11 may be provided on the first bank pattern 130, a second light emitting element 12 may be provided on the second bank pattern 130, and a third light emitting element 13 may be provided on the third bank pattern 130.

[0064] The bank pattern 130 may be made of an organic insulating material such as photosensitive photoacrylic or photosensitive polyimide, but is not limited thereto. The bank pattern 130 may guide the attachment position of the light emitting element 10 during the transfer process of the light emitting element 10. The bank pattern 130 may be omitted.

[0065] The solder pattern 162 may be disposed on the first electrode 161. The solder pattern 162 may be made of indium (In), tin (Sn), or an alloy thereof, but is not limited thereto.

[0066] A plurality of light emitting elements 10 may be mounted on the solder pattern 162, respectively. One pixel may include three colors of light emitting elements 10. The first light emitting element 11 may be a red light emitting element, the second light emitting element 12 may be a green light emitting element, and the third light emitting element 13 may be a blue light emitting element. Two light emitting elements may be mounted on each sub-pixel.

[0067] The first optical layer 141 may cover the plurality of light emitting elements 10 and the dam pattern 130. Therefore, the first optical layer 141 may cover the spaces between the plurality of light emitting elements 10 and the spaces between the dam patterns 130. The first optical layers 141 may extend in the first direction X and may be spaced apart from each other in the second direction Y to be separated between pixel rows.

[0068] The first optical layer 141 may include an organic insulating material in which fine metal particles such as titanium dioxide particles are dispersed. Light emitted from the plurality of light emitting elements 10 may be scattered by the fine metal particles dispersed in the first optical layer 141 and emitted to the outside.

[0069] The second electrode 170 may be disposed on the plurality of light emitting elements 10. The second electrode 170 may be commonly connected to the plurality of pixels PXL. The second electrode 170 may be a thin electrode that transmits light. The second electrode 170 may be a transparent electrode material such as indium tin oxide (ITO), but is not necessarily limited thereto.

[0070] The second electrodes 170 may extend in the first direction (X-axis direction) and may be spaced apart from each other in the second direction (Y-axis direction). The second electrode 170 may include: a first region 171 disposed on the upper surface of the light emitting element 10 and the upper surface of the first optical layer 141, a second region 172 contacting and electrically connected to the contact electrode 163, and a third region 173 disposed on the side surface of the first optical layer 141 and connecting the first region 171 to the second region 172.

[0071] In a plan view, the plurality of second electrodes 170 may each overlap the first optical layer 141 , and the second region 172 may cover an outer flat surface of the first optical layer 141 .

[0072] The second optical layer 142 may be an organic insulating material surrounding the periphery of the first optical layer 141. The second optical layer 142 may be disposed on the insulating layer 122 together with the first optical layer 141. The first optical layer 141 and the second optical layer 142 may include the same material (e.g., siloxane). For example, the first optical layer 141 may be siloxane containing titanium oxide (TiOx), and the second optical layer 142 may be siloxane not containing titanium oxide (TiOx). However, the present disclosure is not necessarily limited thereto, and the first optical layer 141 and the second optical layer 142 may be made of the same material, or may be made of different materials.

[0073] According to an embodiment, since second region 172 of second electrode 170 is entirely flatly formed and connected to contact electrode 163, stress does not excessively concentrate at a point where second region 172 is connected to contact electrode 163. Therefore, cracks in second electrode 170 may be effectively prevented from occurring.

[0074] The second optical layer 142 may cover the second region 172 and the third region 173 of the second electrode 170. The upper surface of the second optical layer 142 and the upper surface of the first region 171 of the second electrode 170 may be disposed on the same surface. In other words, the first optical layer 141 and the second optical layer 142 may serve as a planarization layer. Therefore, since there is no step on the surface on which the black matrix 190 is formed, the pattern of the black matrix 190 may be easily formed on the first optical layer 141 and the second optical layer 142. However, the present disclosure is not necessarily limited thereto, and the upper surfaces of the second optical layer 142 and the second electrode 170 may have different heights.

[0075] The black matrix 190 may be an organic insulating material to which a black pigment is added. The second electrode 170 may be in contact with the contact electrode 163 below the black matrix 190. Transmission holes 191 may be formed between patterns of the black matrix 190, and light emitted from the light emitting element 10 is emitted to the outside through the transmission holes 191. The black matrix 190 may solve the mixing problem of light emitted from adjacent light emitting elements 10 by the first optical layer 141.

[0076] The cover layer 180 may be an organic insulating material for covering the black matrix 190 and the second electrode 170. Figure 3 In the figure, the configuration of the black matrix 190 and the cover layer 180 is omitted.

[0077] The contact electrode 163 may be electrically connected to the first connection line RT1 disposed therebelow, and the first connection line RT1 may be connected to the pixel driving circuit 20. Therefore, a cathode voltage may be applied to the second electrode 170 through the contact electrode 163. The first electrode 161 may be electrically connected to the second connection line RT2. This will be described below.

[0078] Reference Figure 5 , the contact electrode 163 and the signal lines TL1 to TL6 may be disposed on the same surface. The pixel driving circuit 20 may be disposed below the contact electrode 163 and the signal lines TL1 to TL6. When the pixel driving circuit 20 is a driving driver, a plurality of driving drivers may be disposed in the display panel.

[0079] The passivation layer 133 may expose the contact electrode 160 to electrically connect the contact electrode 163 and the second electrode 170. In addition, the passivation layer 133 may insulate the signal lines TL2 to TL5 from the second electrode 170.

[0080] Reference Figure 6 The connection portion 161 a of the first electrode 161 may extend to one side surface 131 of the bank pattern 130 and may be electrically connected to a connection line RT2 disposed on the insulating layer 122 .

[0081] The first electrode 161, the connection portion 161a, the signal line TL and / or the connection lines RT1 and RT2 may include a single layer or multiple layers of metal layers formed of a material selected from titanium (Ti), molybdenum (Mo) and aluminum (Al). The first electrode 161, the connection portion 161a, the signal line TL and / or the connection lines RT1 and RT2 may be a multilayer structure including a first layer ML1, a second layer ML2, a third layer ML3 and a fourth layer ML4.

[0082] The first layer ML1 and the third layer ML3 may include titanium (Ti) or molybdenum (Mo). The second layer ML2 may include aluminum (Al). The fourth layer ML4 may include a transparent conductive oxide layer such as ITO or indium zinc oxide (IZO), which has high adhesion to the solder pattern 162 and also has corrosion resistance and acid resistance.

[0083] The first layer ML1 , the second layer ML2 , the third layer ML3 , and the fourth layer ML4 may be sequentially deposited and then patterned by performing a photolithography process and an etching process.

[0084] The passivation layer 133 may include an opening hole 133 a disposed on the first electrode 161 and the signal line TL and exposing the solder pattern 162 .

[0085] The light emitting element 10 may include a first conductive semiconductor layer 10-1, an active layer 10-2 disposed on the first conductive semiconductor layer 10-1, and a second conductive semiconductor layer 10-3 disposed on the active layer 10-2. The first driving electrode 15 may be disposed under the first conductive semiconductor layer 10-1, and the second driving electrode 14 may be disposed on the second conductive semiconductor layer 10-3.

[0086] The light emitting element 10 can be formed on a silicon wafer using a metal organic chemical vapor deposition (MOCVD) method, a chemical vapor deposition (CVD) method, a plasma enhanced chemical vapor deposition (PECVD) method, a molecular beam epitaxy (MBE) method, a hydride vapor phase epitaxy (HVPE) method, a sputtering method, or the like.

[0087] The first conductive semiconductor layer 10-1 may be implemented using a compound semiconductor such as a group III-V or group II-VI semiconductor and be doped with a first dopant. The first conductive semiconductor layer 10-1 may be made of a semiconductor having a composition formula of Al x1 In y1 Ga (1-x1-y1) The first conductive semiconductor layer 10-1 may be made of any one or more of semiconductor materials of N (0≤x1≤1, 0≤y1≤1, 0≤x1+y1≤1), AlGaAs, GaP, GaAs, GaAsP, and AlGaInP, but is not limited thereto. When the first dopant is an n-type dopant such as Si, Ge, Sn, Se, or Te, the first conductive semiconductor layer 10-1 may be an n-type nitride semiconductor layer. However, when the first dopant is a p-type dopant, the first conductive semiconductor layer 10-1 may be a p-type nitride semiconductor layer.

[0088] The active layer 10-2 is a layer where electrons (or holes) injected through the first conductive semiconductor layer 10-1 meet holes (or electrons) injected through the second conductive semiconductor layer 10-3. When the electrons and holes recombine and generate light with a corresponding wavelength, the active layer 10-2 may be converted to a low energy level.

[0089] The active layer 10-2 may have any one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure, and the structure of the active layer 10-2 is not limited thereto. The active layer 10-2 may generate light in a visible light wavelength band. For example, the active layer 10-2 may output light in any one wavelength band of a blue wavelength band, a green wavelength band, and a red wavelength band.

[0090] The second conductive semiconductor layer 10-3 may be disposed on the active layer 10-2. The second conductive semiconductor layer 10-3 may be implemented using a compound semiconductor such as a group III-V or group II-VI semiconductor, and the second conductive semiconductor layer 10-3 may be doped with a second dopant. The second conductive semiconductor layer 10-3 may be made of a semiconductor having a composition formula of Al x2 In y2 Ga (1-x2-y2)The second conductive semiconductor layer 10-3 may be made of any one or more of semiconductor materials of N (0≤x2≤1, 0≤y2≤1, 0≤x2+y2≤1), AlGaAs, GaP, GaAs, GaAsP and AlGaInP, but is not limited thereto. When the second dopant is a p-type dopant such as Mg, Zn, Ca, Sr or Ba, the second conductive semiconductor layer 10-3 doped with the second dopant may be a p-type semiconductor layer. When the second dopant is an n-type dopant, the second conductive semiconductor layer 10-3 may be an n-type nitride semiconductor layer.

[0091] The reflective layer 16 may be provided on the side surface and the lower surface of the light emitting element 10. The reflective layer 16 may have a structure in which a reflective material is dispersed in a resin layer, but is not necessarily limited thereto. For example, the reflective layer 16 may be formed as a reflector having any of various structures. The light emitted from the active layer 10-2 is reflected upward by the reflective layer 16, thereby improving the light extraction efficiency.

[0092] Although it has been described in the embodiment that the light emitting element 10 has a vertical structure in which the driving electrodes 14 and 15 are provided above and below the light emitting structure, the light emitting element 10 may have a lateral structure or a flip chip structure other than the vertical structure.

[0093] Reference Figure 7 , a main light emitting element 12a and a sub-light emitting element 12b of a sub-pixel may be disposed on the bank pattern 130. An example of the second light emitting element 12 will be described. The 1-1 electrode 161-1 connected to the main light emitting element 12a may extend to one side surface of the bank pattern 130, and may be electrically connected to the 2-1 connection line RT21 disposed thereunder. The 1-2 electrode 161-2 connected to the sub-light emitting element 12b may extend to the other side surface of the bank pattern 130, and may be electrically connected to the 2-2 connection line RT22 disposed thereunder.

[0094] The pixel driving circuit 20 may apply an anode voltage to the main light emitting element 12a through the 2-1 connection line RT21, and apply an anode voltage to the sub light emitting element 12b through the 2-2 connection line RT22. The pixel driving circuit 20 may apply a cathode voltage to the main light emitting element 12a and the sub light emitting element 12b through the first connection line RT1 and the second electrode 170.

[0095] The pixel driving circuit 20 can adjust the brightness by driving only the main light emitting element 12a, and can adjust the brightness by driving the main light emitting element 12a and the sub-light emitting element 12b at the same time. When the main light emitting element 12a becomes a dark spot, the brightness can be adjusted by driving only the sub-light emitting element 12b.

[0096] Figure 8is a diagram illustrating a display device according to another embodiment of the present specification. Fig. 9 is along Figure 8 Cross-sectional view along line IV-IV'. Fig.10 is a diagram showing a state in which stress is concentrated on a second electrode provided in a through hole;

[0097] Reference Figure 8 and Fig. 9 , the second electrode 170 may be electrically connected to the contact electrode 163 via a contact hole TH1 formed in the second optical layer 142. The second optical layer 142 may include a contact hole TH1 exposing the contact electrode 163. The second electrode 170 may be inserted into the contact hole TH1 of the second optical layer 142 and may contact an upper surface of the contact electrode 163. The contact hole TH1 may be formed in an outer region of the pixel.

[0098] Reference Fig.10 Since the second electrode 170 is relatively thin and the contact hole TH1 is formed deeper than the thickness of the second electrode 170, a stress concentration region BP1 may occur on the portion 170a of the second electrode 170 formed on the side surface portion of the contact hole TH1. Therefore, there may be a risk of cracks occurring in the portion 170a of the second electrode 170 formed near the contact hole TH1.

[0099] However, if Figure 4 As described, when the second electrode 170 in a flat and extended state is connected to the contact electrode 163 instead of forming the contact hole TH1, it is possible to prevent stress from being excessively applied to the second electrode 170. Therefore, it is possible to prevent cracks from occurring in the second electrode 170.

[0100] Fig.11 It is shown Figure 8 FIG. 1 is a diagram of a first modified example of a display device. Fig.12 It is shown Figure 8 FIG. 1 is a diagram of a second modified example of a display device.

[0101] Reference Fig.11 , the contact hole TH1 may be filled with a separate through electrode 164. The through electrode 164 may include various conductive materials that may fill the contact hole TH1. Since the second electrode 170 is disposed on the through electrode 164, the second electrode 170 is formed to be relatively flat, thereby preventing excessive stress from occurring.

[0102] Reference Fig.12 , the through electrode 164 may not completely fill the contact hole TH1, but only fill it to a predetermined height. With this structure, the depth of the second electrode 170 inserted into the contact hole TH1 can be relatively low. Therefore, the step of the second electrode 170 can be reduced, thereby reducing the probability of cracks.

[0103] FIG. 13A to FIG. 13F is a diagram illustrating a method of manufacturing a display device according to an embodiment of the present specification.

[0104] Reference Fig.13A , a pixel driving circuit 20 may be formed on the substrate 110, and a buffer layer 121 may be formed on the pixel driving circuit 20. The pixel driving circuit may drive a plurality of pixels by receiving a driving voltage, an image signal (digital signal), a synchronization signal synchronized with the image signal, etc., and outputting an anode voltage and a cathode voltage of the light emitting element 10. The pixel driving circuit 20 may be disposed in the non-display area NA and below the display area AA.

[0105] Subsequently, connection lines RT1, RT2, and RT22 may be formed on the buffer layer 121, and then the insulating layer 122 may be formed. The connection lines RT1, RT2, and RT22 may pass through the buffer layer 121 and may be electrically connected to the pixel driving circuit 20. In order to drive each pixel, the number of connection lines RT1, RT2, and RT22 and the stacking number of the connection lines RT1, RT21, and RT22 may be changed in any of various ways. Therefore, the stacking number of the connection lines RT1, RT2, and RT22 and the insulating layer 122 may be two or more layers.

[0106] A bank pattern 130 may be formed on the insulating layer 122 to select a transfer position of the light emitting element 10. The bank pattern 130 may be made of an organic insulating material such as photosensitive photoacrylic or photosensitive polyimide, but is not limited thereto. The bank pattern 130 may guide an attachment position of the light emitting element 10 during the transfer process of the light emitting element 10. However, the bank pattern 130 may be omitted.

[0107] An electrode material may be applied on the insulating layer 122 and the bank pattern 130, and then patterned to form a plurality of first electrodes 161 and a contact electrode 163. The plurality of first electrodes 161 are regions on which the light emitting element 10 is disposed, and the contact electrode 163 is a region electrically connected to the second electrode 170. Subsequently, a passivation layer 133 may be formed in electrode regions other than the regions on which the plurality of first electrodes 161 and the contact electrode 163 are formed.

[0108] A solder pattern 162 may be disposed on the first electrode 161. The solder pattern 162 may be made of indium (In), tin (Sn), or an alloy thereof, but is not limited thereto.

[0109] Reference Fig. 13B, a plurality of light emitting elements 10 may be transferred to the solder pattern 162, respectively. One pixel may include three colors of light emitting elements 10. The first light emitting element may be a red light emitting element, the second light emitting element may be a green light emitting element, and the third light emitting element may be a blue light emitting element. Two light emitting elements may be installed in each sub-pixel.

[0110] The transfer method is not particularly limited. In other words, the light emitting element 10 grown on the semiconductor growth substrate may be first transferred to the transfer substrate and then transferred to the panel substrate again, or the light emitting element 10 grown on the semiconductor growth substrate may be directly transferred to the panel substrate.

[0111] Reference Fig. 13C and Fig.13D , the first optical layer 141 may be formed on the entire substrate 110 and then patterned to expose the upper surfaces of the light emitting element 10 and the contact electrode 163. A portion of the first optical layer 141 other than a region sufficient to cover the light emitting element 10 and the dam pattern 130 may be removed. Thus, the first optical layer 141 may cover the spaces between the plurality of light emitting elements 10 and between the plurality of dam patterns 130. In this case, the upper surface of the light emitting element 10 may be exposed upward from the first optical layer 141.

[0112] The first optical layer 141 may include an organic insulating material in which fine metal particles such as titanium dioxide particles are dispersed. Light emitted from the light emitting element 10 may be scattered by the fine metal particles dispersed in the first optical layer 141 and emitted to the outside.

[0113] Reference Fig.13E , a second electrode 170 may be formed on the plurality of light emitting elements 10. The second electrode 170 may be generally connected to the plurality of pixels PXL. The second electrode 170 may be a thin metal electrode that transmits light. The second electrode 170 may be a transparent electrode material, such as ITO, but is not necessarily limited thereto.

[0114] The second electrode 170 may be divided to be disposed in each pixel row by patterning. The plurality of divided second electrodes 170 may be electrically connected to the contact electrode 163 .

[0115] Reference Fig.13F , the second optical layer 142 may be formed to surround the periphery of the first optical layer 141. In this process, the second optical layer 142 may cover a portion of the second electrode 170 connected to the contact electrode 163.

[0116] The second optical layer 142 may be disposed on the insulating layer 122 together with the first optical layer 141. The first optical layer 141 and the second optical layer 142 may include the same material (e.g., siloxane). For example, the first optical layer 141 may be siloxane containing titanium oxide (TiOx), and the second optical layer 142 may be siloxane not containing titanium oxide (TiOx).

[0117] Subsequently, a black matrix 190 may be formed on the second electrode 170 and the second optical layer 142 , and a capping layer 180 may be formed on the black matrix 190 .

[0118] Fig.14 is a diagram showing a modified example of the second electrode. Fig.15 is along Fig.14 Cross-sectional view along line V-V'.

[0119] Reference Fig.14 , a portion of the second electrode 170 may be removed so as not to overlap with the signal line TL in a plan view, so that one or more concave portions 170a and one or more convex portions 170b are alternately formed. Any one of the convex portions 170b may be connected to the contact electrode 163. In addition, a plurality of concave portions 170a and a plurality of convex portions 170b may be alternately formed. Any one of the convex portions 170b may be connected to the contact electrode 163. Although Fig.14 An embodiment is shown in which a plurality of convex portions 170 b are formed and one of the convex portions 170 b is connected to the contact electrode 163 , but convex portions 170 b other than the convex portion 170 b connected to the contact electrode 163 may also be selectively formed.

[0120] Reference Fig.15 , since only the passivation layer 133 having a small thickness is disposed between the signal line TL and the second electrode 170, and the capacitance is formed to be higher than that of other regions, there is a problem that interference occurs in the driving signal. Fig.14 and Fig.15 , the parasitic capacitance between the second electrode 170 and the signal line TL can be reduced by removing the portion of the second electrode 170 overlapping the signal line TL in the second region 172 disposed outside the first optical layer 141. In addition, the second electrode 170 can be formed in a portion where the signal line TL is not formed in the second region 172, thereby increasing the area of ​​the second electrode 170 to reduce resistance.

[0121] Fig.16 is along Figure 1 Cross-sectional view along line VI-VI'.

[0122] Reference Figure 1 and Fig.16, a plurality of signal lines LL may be disposed on the buffer layer 121 and the insulating layer 122 in the non-display area NA. A data driving signal, a gate driving signal, or a control signal for controlling a driving operation of a driving circuit may be provided to the plurality of signal lines LL. The non-display area NA may include an edge area EA adjacent to an edge of the panel substrate. The edge area EA is directly exposed to moisture, heat, and the like. When an organic layer (such as the buffer layer 121 and the insulating layer 122) and a metal layer (such as the plurality of signal lines LL disposed in the non-display area NA) included in the panel substrate are exposed to moisture and heat, cracks may occur in the organic layer or delamination of the metal layer may occur.

[0123] Fig.17 is a plan view of a display device according to an embodiment of the present disclosure.

[0124] Fig.18A , Fig.18B and Fig. 18C is along Fig.17 Cross-sectional view along line VII-VII'.

[0125] according to Fig.17 and 18A According to one embodiment of the present disclosure, a metal dam DAM may be provided in the non-display area NA to surround a signal line provided in the non-display area NA.

[0126] The metal dam DAM may be provided to surround at least three surfaces of the display area AA, but is not limited thereto. The metal dam DAM may be formed by the following process. At least one first hole H1 may be formed in the buffer layer 121 provided in the edge area EA.

[0127] A first metal dam DAM1 may be formed on the buffer layer 121 to cover the first hole H1. The insulating layer 122 may be provided to cover the buffer layer 121 and the first metal dam DAM1. At least one second hole H2 formed by removing the insulating layer 122 may be formed on the first metal dam DAM1. A second metal dam DAM2 may be formed on the insulating layer 122 to cover the second hole H2. The passivation layer 133 may be provided to cover the second metal dam DAM2 and the second hole H2. The passivation layer 133 may be formed to cover only a portion of the second metal dam DAM2. The second optical layer 142 may be provided on the passivation layer 133. The second optical layer 142 may be formed to contact a portion of the second metal dam DAM2. In the edge area EA, the height of the second optical layer 142 may be gradually reduced toward the edge area EA. A third metal dam DAM3 may be provided to cover the second optical layer 142. The third metal dam DAM3 may be formed to be directly connected to the second metal dam DAM2. At least a portion of the second optical layer 142 may be in contact with the second metal dam DAM2 and the third metal dam DAM3 at the same time. The cover layer 180 may be disposed on the third metal dam DAM3. The first hole H1 and the second hole H2 may not overlap each other. The holes H1 and H2 may be arranged in a zigzag shape. Although not shown in the figure, the display area AA and the non-display area NA may further include at least one organic layer on the buffer layer 121, and may further include at least one metal layer on each organic layer. Each of the organic layer and the metal layer may include a hole and a metal dam, and the hole and the metal dam may be connected to the buffer layer 121. Fig.17 and Fig.18A In one embodiment, the first hole H1 and the second hole H2 or the first metal dam DAM1 and the second metal dam DAM2 are formed in the same manner.

[0128] Fig.18B A display device according to one embodiment of the present disclosure is shown.

[0129] At least one first hole H1 may be formed in the buffer layer 121 in the edge area EA. The first metal dam DAM1 may be formed on the buffer layer 121 to cover the first hole H1. The insulating layer 122 may be provided to cover the buffer layer 121 and the first metal dam DAM1. At least one second hole H2 formed by removing the insulating layer 122 may be formed on the first metal dam DAM1. A portion of at least one of the second holes H2 may overlap with the at least one first hole H1. The second metal dam DAM2 may be formed on the insulating layer 122 to cover the second hole H2. The passivation layer 133 may be provided to cover the second metal dam DAM2 and the second hole H2. The passivation layer 133 may be formed to cover only a portion of the second metal dam DAM2. The second optical layer 142 may be provided on the passivation layer 133. The second optical layer 142 may be formed to contact a portion of the second metal dam DAM2. In the edge area EA, the height of the second optical layer 142 may gradually decrease toward the edge area EA. The third metal dam DAM3 may be provided to cover the second optical layer 142. The third metal dam DAM3 may be formed to be directly connected to the second metal dam DAM2. At least a portion of the second optical layer 142 may be in contact with the second metal dam DAM2 and the third metal dam DAM3 at the same time. Although not shown in the figure, the display area AA and the non-display area NA may further include at least one organic layer on the buffer layer 121, and may further include at least one metal layer on each organic layer. Each of the organic layer and the metal layer may include a hole and a metal dam, and the hole and the metal dam may be connected to the second metal dam DAM2. Fig.17 and Fig.18B In one embodiment, the first hole H1 and the second hole H2 or the first metal dam DAM1 and the second metal dam DAM2 are formed in the same manner.

[0130] Fig. 18C A display device according to one embodiment of the present disclosure is shown.

[0131] At least one first hole H1 may be formed in the buffer layer 121 in the edge area EA. The first metal dam DAM1 may be formed on the buffer layer 121 to cover the first hole H1. The insulating layer 122 may be provided to cover the buffer layer 121 and the first metal dam DAM1. At least one second hole H2 formed by removing the insulating layer 122 may be formed on the first metal dam DAM1. The entire hole area of ​​at least one of the second holes H2 may overlap with the at least one first hole H1. The second metal dam DAM2 may be formed on the insulating layer 122 to cover the second hole H2. The passivation layer 133 may be provided to cover the second metal dam DAM2 and the second hole H2. The passivation layer 133 may be formed to cover only a portion of the second metal dam DAM2. The second optical layer 142 may be provided on the passivation layer 133. The second optical layer 142 may be formed to contact a portion of the second metal dam DAM2. In the edge area EA, the height of the second optical layer 142 may gradually decrease toward the edge area EA. The third metal dam DAM3 may be provided to cover the second optical layer 142. The third metal dam DAM3 may be formed to be directly connected to the second metal dam DAM2. At least a portion of the second optical layer 142 may be in contact with the second metal dam DAM2 and the third metal dam DAM3 at the same time. Although not shown in the figure, the display area AA and the non-display area NA may further include at least one organic layer on the buffer layer 121, and may further include at least one metal layer on each organic layer. Each organic layer and metal layer may include a hole and a metal dam, and the hole and the metal dam may be connected to the second metal dam DAM2. Fig.17 and Fig. 18C In one embodiment, the first hole H1 and the second hole H2 or the first metal dam DAM1 and the second metal dam DAM2 are formed in the same manner.

[0132] When the first to third metal dams DAM1, DAM2 and DAM3 refer to Fig.18A , Fig.18B and Fig. 18C When configured as described, by blocking the path for substances (e.g., moisture) that cause a decrease in the reliability of the display panel to penetrate into the display panel, components susceptible to moisture damage, such as the light-emitting element 10 and the pixel driving circuit 20 disposed on the display panel, can be protected. In addition, the plurality of metal dams DAM1, DAM2, and DAM3 can block the path for crack expansion caused by moisture or heat. The first to third metal dams DAM1, DAM2, and DAM3 can be configured to be spaced a predetermined distance from the edge of the display panel. This is because when the plurality of metal dams DAM1, DAM2, and DAM3 are exposed to the air at the edge of the display panel, the metal dams DAM1, DAM2, and DAM3 may corrode, causing moisture penetration. When such as Fig.18A When the metal dam DAM is formed as shown, the area of ​​the metal dam DAM can be reduced, thereby realizing a display device with a thin frame. Fig.18B In the embodiment of the present invention, when a plurality of holes are formed on each organic layer, the penetration path of moisture can be increased, so it is difficult for moisture to penetrate into the display panel. Fig. 18C When the metal dam DAM is arranged to overlap with the hole arranged in each organic layer as in the embodiment of the present invention, the area of ​​the metal dam DAM can be reduced, thereby realizing a display device with a thin frame.

[0133] The display device according to the embodiments of the present specification can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, sliding devices, variable devices, electronic notebooks, electronic books, portable multimedia players (PMP), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation systems, vehicle display devices, cinema display devices, televisions, wallpaper devices, signage devices, gaming devices, laptop computers, monitors, cameras, video cameras, home appliances, etc. In addition, the display device according to one or more embodiments of the present specification can also be applied to organic light emitting lighting devices or inorganic light emitting lighting devices.

[0134] Since the contents of the specification describing the above technical problems, technical solutions and beneficial effects do not specify the essential features of the claims, the scope of the claims is not limited to the items described in the contents of this specification.

[0135] According to the present specification, parasitic capacitance generated in an overlapping region of a cathode and a signal line can be reduced, and an increase in cathode resistance can be reduced, thereby realizing low power consumption driving.

[0136] A display device according to various embodiments of the present disclosure may be described as follows.

[0137] A display device according to one embodiment of the present disclosure may include a display panel, the display panel including a display area and a non-display area surrounding the display area, and a metal dam arranged in the non-display area to surround at least three surfaces of the display panel, wherein the display panel includes a substrate, a pixel driving circuit arranged on the substrate, and a light-emitting element driven by the pixel driving circuit.

[0138] According to one embodiment of the present disclosure, the metal dam may be spaced apart from an edge of the display panel by a predetermined distance.

[0139] According to one embodiment of the present disclosure, the metal dam may be formed of a plurality of metal layers connected by at least one hole.

[0140] According to one embodiment of the present disclosure, the metal dam may include first, second, and third metal dams disposed in the non-display area while surrounding at least three surfaces of the display area.

[0141] According to one embodiment of the present disclosure, the display panel may also include: a substrate; a buffer layer arranged on the substrate; a first hole formed on the buffer layer in a non-display area; an insulating layer on the buffer layer; a second hole formed on the insulating layer in the non-display area; a passivation layer formed to cover the second hole; a first optical layer formed to cover the passivation layer; a first metal dam, which is arranged in the non-display area and surrounds at least three surfaces of the display area on the buffer layer, a second metal dam, which overlaps with the first metal dam on the insulating layer in a plan view; and a third metal dam, which overlaps with the first metal dam on the first optical layer in a plan view, and the first metal dam and the second metal dam are connected through the first hole.

[0142] According to one embodiment of the present disclosure, the first hole and the second hole may be disposed to overlap with each other.

[0143] According to one embodiment of the present disclosure, the first hole and the second hole may be arranged not to overlap each other.

[0144] According to one embodiment of the present disclosure, the second metal dam and the third metal dam may be partially connected.

[0145] According to one embodiment of the present disclosure, a passivation layer may be disposed between an outermost portion of the second metal dam and an outermost portion of the third metal dam.

[0146] The effects of the present specification are not limited to the above-mentioned effects, and other effects that are not mentioned can be clearly understood by those skilled in the art from the above-mentioned detailed description.

[0147] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present disclosure. Therefore, the implementation disclosed in the present disclosure is not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all aspects, rather than restrictive.

Claims

1. A display device, comprising: A display panel, the display panel comprising a display area and a non-display area surrounding the display area; as well as a metal dam arranged in the non-display area to surround at least three surfaces of the display area, Wherein, the display panel comprises: substrate; a pixel driving circuit disposed on the substrate; and A light emitting element driven by the pixel driving circuit.

2. The display device according to claim 1, wherein: The metal dam is spaced apart from an edge of the display panel by a predetermined distance.

3. The display device according to claim 1, wherein: The metal dam is formed of a plurality of metal layers connected by at least one hole.

4. The display device according to claim 1, wherein: The metal dam includes a first metal dam, a second metal dam, and a third metal dam, which are arranged in the non-display area and surround at least three surfaces of the display area.

5. The display device according to claim 4, wherein: The display panel further includes: the substrate; a buffer layer disposed on the substrate; a first hole formed in the buffer layer in the non-display area; an insulating layer on the buffer layer; a second hole formed in the insulating layer in the non-display area; forming a passivation layer to cover the second hole; forming an optical layer to cover the passivation layer; the first metal dam being arranged on the buffer layer in the non-display area and surrounding the at least three surfaces of the display area; the second metal dam being disposed on the insulating layer and overlapping the first metal dam in a plan view; and the third metal dam being disposed on the optical layer and overlapping the first metal dam in a plan view, and The first metal dam and the second metal dam are connected through the first hole.

6. The display device according to claim 5, wherein: The first hole and the second hole are arranged to overlap each other.

7. The display device according to claim 5, wherein: The first hole and the second hole are arranged not to overlap each other.

8. The display device according to claim 5, wherein: The second metal dam and the third metal dam are partially connected.

9. The display device according to claim 5, wherein: The passivation layer is disposed between an outermost portion of the second metal dam and an outermost portion of the third metal dam.

10. The display device according to claim 5, wherein: The height of the optical layer gradually decreases toward the edge region.

11. The display device according to claim 1, wherein: The display panel further includes: A plurality of first electrodes and contact electrodes are disposed on the substrate, wherein a plurality of light emitting elements are disposed on the plurality of first electrodes; a first optical layer disposed between the plurality of light emitting elements; and A second electrode disposed on the plurality of light emitting elements, The second electrode includes: a first region arranged on the upper surface of the light-emitting element and the upper surface of the first optical layer, a second region contacting the contact electrode and electrically connected to the contact electrode, and a third region arranged on the side surface of the first optical layer and connecting the first region to the second region.

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