Bus access method in integrated circuit, integrated circuit and electronic equipment

Abstract

The invention discloses a bus access method in an integrated circuit, the integrated circuit and electronic equipment, and relates to the technical field of integrated circuits, and the method comprises the following steps: generating a first access request through a first hardware unit in a first function security level domain; determining a first identifier of the first hardware unit based on the first access request; reading first configuration information corresponding to a second hardware unit in a second functional security level domain from the register, wherein the first configuration information comprises a second identifier of a target hardware unit of which the security level of the functional security level domain is higher than that of the second functional security level domain; determining the permission of the first hardware unit to access the second hardware unit based on the first identifier and the second identifier; the first access request is transmitted from the bus to the second hardware unit based on the right control. According to the technical scheme, transmission control can be carried out on the access requests among the hardware units in the different functional security level domains based on the security levels, and the requirement of the functional security level domain with the high security level for security is guaranteed.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a bus access method in an integrated circuit, an integrated circuit, and an electronic device. Background Art

[0002] System on chip (SoC), also known as integrated circuit, can include multiple hardware units, and different functions can be realized by these multiple hardware units. Based on the different security requirements of different functions, the integrated circuit can be divided into at least one functional safety level domain, wherein each functional safety level domain includes at least one hardware unit, and different functional safety level domains correspond to different security levels, which are used to characterize the security requirements of the functions realized by each hardware unit in the corresponding functional safety level domain. The higher the security level of the functional safety level domain, the higher the security requirements of the functions realized by each hardware unit in the functional safety level domain, and the lower the security level of the functional safety level domain, the lower the security requirements of the functions realized by each hardware unit in the functional safety level domain.

[0003] Hardware units in different functional safety level domains can access each other through the bus, thereby enabling communication between corresponding functional safety level domains. Summary of the invention

[0004] If a problem occurs in a hardware unit in a functional safety level domain with a lower security level, the hardware unit in the functional safety level domain with a lower security level can still transmit access requests to the hardware unit in the functional safety level domain with a higher security level through the bus. Therefore, the access request will cause the hardware unit in the functional safety level domain with a higher security level to fail to work properly, and thus fail to guarantee the security requirements of the functional safety level domain with a higher security level.

[0005] In order to solve the above technical problems, the present disclosure provides a bus access method in an integrated circuit, an integrated circuit and an electronic device, which can solve the problem that hardware units in a functional safety level domain with a higher safety level cannot work normally due to problems with hardware units in a functional safety level domain with a lower safety level.

[0006] According to a first aspect of the present disclosure, a bus access method in an integrated circuit is provided, comprising: generating a first access request through a first hardware unit in a first functional safety level domain; determining a first identifier of the first hardware unit based on the first access request; reading first configuration information corresponding to a second hardware unit in a second functional safety level domain from a register, the first configuration information comprising a second identifier of a target hardware unit whose security level in the functional safety level domain is higher than that in the second functional safety level domain; determining permission for the first hardware unit to access the second hardware unit based on the first identifier and the second identifier; and controlling transmission of the first access request from a bus to the second hardware unit based on permission for the first hardware unit to access the second hardware unit.

[0007] The second aspect of the present disclosure provides an integrated circuit, comprising: a controller; a first hardware unit, corresponding to a first functional safety level domain; a second hardware unit, corresponding to a second functional safety level domain; a register, storing first configuration information corresponding to the second hardware unit, the first configuration information comprising a second identifier of a target hardware unit whose security level in the functional safety level domain is higher than that in the second functional safety level domain; wherein the first hardware unit is used to generate a first access request; the controller is used to determine the first identifier of the first hardware unit based on the first access request; the controller is also used to read the first configuration information from the register; the controller is also used to determine the authority of the first hardware unit to access the second hardware unit based on the first identifier and the second identifier; the controller is also used to control the transmission of the first access request from a bus to the second hardware unit based on the authority of the first hardware unit to access the second hardware unit.

[0008] According to a third aspect of the present disclosure, a computer-readable storage medium is provided, wherein the storage medium stores a computer program for executing the bus access method in an integrated circuit provided in the first aspect.

[0009] The fourth aspect of the present disclosure provides an electronic device, which includes: a processor; a memory for storing processor executable instructions; a processor, configured to read executable instructions from the memory and execute the instructions to implement the bus access method in the integrated circuit provided in the first aspect above, or the electronic device includes the integrated circuit provided in the second aspect above.

[0010] A fifth aspect of the present disclosure provides a computer program product. When instructions in the computer program product are executed by a processor, the bus access method in the integrated circuit provided by the first aspect is executed.

[0011] Based on the bus access method in the integrated circuit provided by the present disclosure, when the first hardware unit in the first functional safety level domain transmits the first access request to the second hardware unit in the second functional safety level domain through the bus, the transmission of the first access request on the bus can be controlled based on the security levels of the first functional safety level domain and the second functional safety level domain. If a problem occurs in the hardware unit in the functional safety level domain with a lower security level in the first functional safety level domain and the second functional safety level domain, since the transmission of the first access request from the bus to the hardware unit in the functional safety level domain with a higher security level can be controlled, the first access request transmitted by the hardware unit in the functional safety level domain with a lower security level when a problem occurs can be controlled accordingly, thereby effectively ensuring the normal operation of the hardware unit in the functional safety level domain with a higher security level, and then ensuring the security requirements of the functional safety level domain with a higher security level. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic diagram of the architecture of an integrated circuit provided by an exemplary embodiment of the present disclosure;

[0013] Figure 2 is a schematic diagram of the architecture of an integrated circuit provided by another exemplary embodiment of the present disclosure;

[0014] Figure 3 is a schematic diagram of the architecture of an integrated circuit provided by another exemplary embodiment of the present disclosure;

[0015] Figure 4 is a flowchart of a bus access method provided by an exemplary embodiment of the present disclosure;

[0016] Figure 5 is a flowchart of a bus access method provided by another exemplary embodiment of the present disclosure;

[0017] Figure 6 is a flowchart of a bus access method provided by another exemplary embodiment of the present disclosure;

[0018] Figure 7 is a flowchart of a bus access method provided by yet another exemplary embodiment of the present disclosure;

[0019] Figure 8 It is a structural schematic diagram of an electronic device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] To explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. It should be understood that the present disclosure is not limited to the example embodiments.

[0021] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0022] Application Overview

[0023] System on chip (SoC), also known as integrated circuit, can include multiple hardware units, and different functions can be realized by these multiple hardware units. Based on the security requirements of different functions, the integrated circuit can be divided into at least one functional safety level domain, wherein each functional safety level domain includes at least one hardware unit, and different functional safety level domains correspond to different security levels, which are used to characterize the security requirements of the functions realized by each hardware unit in the corresponding functional safety level domain. For example, the higher the security level of the functional safety level domain, the higher the security requirements of the functions realized by each hardware unit in the functional safety level domain, and the lower the security level of the functional safety level domain, the lower the security requirements of the functions realized by each hardware unit in the functional safety level domain.

[0024] In some examples, the hardware units included in the integrated circuit can be used to implement vehicle-related functions. For the integrated circuit, the functional safety level domain can be divided based on the road vehicle-functional safety standard (such as ISO 26262). The safety levels of the functional safety level domain can include the quality management (Quality Management, QM) level and the vehicle safety integrity level (Automobile Safely Integrity Level, ASIL), where the QM level is lower than the ASI L level, and the ASI L levels from low to high may include ASI LA, ASI LB, ASI LC, and ASI LD.

[0025] Figure 1 Schematic diagram of the architecture of an integrated circuit provided by an exemplary embodiment of the present disclosure.

[0026] like Figure 1As shown, the integrated circuit may include a first hardware unit 11 and a second hardware unit 12. The first hardware unit 11 may realize a first function, such as a function of displaying information on a display screen of a vehicle, and the second hardware unit 12 may realize a second function, such as a function of emergency braking of a vehicle. Based on the safety requirements of the first function and the second function, the functional safety level domains are divided for the integrated circuit. If the first function and the second function have different safety requirements, the integrated circuit may be divided into a first functional safety level domain 13 and a second functional safety level domain 14. The hardware unit in the first functional safety level domain 13 includes the first hardware unit 11, and the hardware unit 14 in the second functional safety level domain includes the second hardware unit 12. The safety levels of the first functional safety level domain 13 and the second functional safety level domain 14 may be the same or different. The safety level of the first functional safety level domain 13 matches the safety requirements of the first function, and the safety level of the second functional safety level domain 14 matches the safety requirements of the second function. For ease of description, the following is an exemplary description of different safety levels of different functional safety level domains.

[0027] The hardware units in different functional safety level domains can access each other through the bus, thereby enabling communication between the corresponding functional safety level domains. Figure 1 As shown, the first hardware unit 11 and the second hardware unit 12 can access each other through the bus 15, so that communication between the first functional safety level domain 13 and the second functional safety level domain 14 can be achieved.

[0028] However, based on the above architecture, when hardware units in functional safety level domains with different safety levels access each other, once a hardware unit in a functional safety level domain fails, in addition to causing other hardware units in the functional safety level domain to fail, the failure will cause the bus to fail, which may in turn cause hardware units in another functional safety level domain that shares the bus to fail, especially once a hardware unit in a functional safety level domain with a lower safety level fails, it will cause hardware units in a functional safety level domain with a higher safety level to fail, resulting in the spread of the failure. For example, if the safety level of the first functional safety level domain 13 is lower than the safety level of the second functional safety level domain 14, when the first hardware unit 11 accesses the second hardware unit 12, once the first hardware unit 11 fails, such as the first hardware unit 11 cannot respond to the access request of the second hardware unit 12 for a long time, the first hardware unit 11 is hung, which will cause the second hardware unit 12 to hang.

[0029] In order to solve the above technical problems, the embodiments of the present disclosure provide a bus access device and a bus access method in an integrated circuit.

[0030] The device may include: a controller; a first hardware unit corresponding to a first functional safety level domain; a second hardware unit corresponding to a second functional safety level domain; a register storing first configuration information corresponding to the second hardware unit, the first configuration information including a second identifier of a target hardware unit whose security level in the functional safety level domain is higher than that in the second functional safety level domain; wherein the first hardware unit is used to generate a first access request; the controller is used to determine the first identifier of the first hardware unit based on the first access request; the controller is also used to read the first configuration information from the register; the controller is also used to determine the authority of the first hardware unit to access the second hardware unit based on the first identifier and the second identifier; the controller is also used to control the transmission of the first access request from the bus to the second hardware unit based on the authority of the first hardware unit to access the second hardware unit.

[0031] The method includes generating a first access request through a first hardware unit in a first functional safety level domain; determining a first identifier of the first hardware unit based on the first access request; reading first configuration information corresponding to a second hardware unit in a second functional safety level domain from a register, the first configuration information including a second identifier of a target hardware unit whose functional safety level domain has a higher security level than a second functional safety level domain; determining the authority of the first hardware unit to access the second hardware unit based on the first identifier and the second identifier, that is, the high-low relationship between the security level of the first functional safety level domain where the first hardware unit is located and the security level of the second functional safety level domain where the second hardware unit is located; and controlling the transmission of the first access request from the bus to the second hardware unit based on the authority, which is equivalent to controlling the transmission of the first access request from the bus to the second hardware unit based on the high-low relationship between the security level of the first functional safety level domain and the security level of the second functional safety level domain. If a problem occurs in a hardware unit in a functional safety level domain with a lower security level in the first functional safety level domain and the second functional safety level domain, since it is possible to control the transmission of the first access request from the bus to the hardware unit in the functional safety level domain with a higher security level, the first access request transmitted by the hardware unit in the functional safety level domain with a lower security level when the problem occurs can be controlled accordingly, thereby effectively ensuring the normal operation of the hardware unit in the functional safety level domain with a higher security level, and further ensuring the security requirements of the functional safety level domain with a higher security level.

[0032] The bus access device and bus access method in the present disclosure are further described below in conjunction with the accompanying drawings.

[0033] Exemplary Systems

[0034] Figure 2 is a schematic diagram of the architecture of an integrated circuit provided by another exemplary embodiment of the present disclosure.

[0035] like Figure 2 As shown, the integrated circuit may include N functional safety level domains, such as the first functional safety level domain 21, the second functional safety level domain 22, and so on until the Nth functional safety level domain 2n. Each functional safety level domain includes at least one hardware unit, and the hardware unit included in the first functional safety level domain 21 is referred to as the first hardware unit, and the hardware unit included in the second functional safety level domain 22 is referred to as the second hardware unit, and so on. The first functional safety level domain 21 may include the first hardware unit 211, the first hardware unit 212 to the first hardware unit 21n, the second functional safety level domain 22 may include the second hardware unit 221, the first hardware unit 222 to the second hardware unit 22n, and so on, the Nth functional safety level domain 2n may include the Nth hardware unit 2n1, the Nth hardware unit 2n2 to the Nth hardware unit 2nn.

[0036] The hardware units in each functional safety level domain can access each other through bus 201, so as to realize the communication between the corresponding functional safety level domains. Among them, the hardware unit can initiate access to other hardware units as a host (master), and the hardware unit can also be accessed by other hardware units as a slave (sl ave). The hardware unit includes a host interface and a slave interface, and is respectively connected to bus 201 through the host interface and the slave interface. The hardware unit as the host can transmit the access request to bus 201 through the host interface, and transmit it to the slave interface of the hardware unit as the slave through bus 201.

[0037] like Figure 2 As shown, the integrated circuit also includes at least one controller, which can be used to control access requests transmitted between hardware units. The at least one controller corresponds to the hardware unit, wherein each hardware unit corresponds to at least one controller group, and each controller group includes at least one controller. The controller group corresponding to the first hardware unit is called the first controller group, the controller group corresponding to the second hardware unit is called the second controller group, and so on. Figure 2 As shown, the first hardware unit 211 to the first hardware unit 21n correspond to the first controller group 2111 to the first controller group 21n1 respectively, the second hardware unit 221 to the second hardware unit 22n correspond to the second controller group 2211 to the second controller group 22n1 respectively... the Nth hardware unit 2n1 to the Nth hardware unit 2nn correspond to the Nth controller group 2n11 to the Nth controller group 2nn1 respectively.

[0038] In some embodiments, the controller group may control the transmission of the access request on the bus 201 based on at least one processing mechanism. The at least one processing mechanism is used to prevent the hardware units in the functional safety level domain with a low safety level from affecting the hardware units in the functional safety level domain with a high safety level. The controllers in the controller group correspond to the processing mechanisms, and different controllers correspond to different processing mechanisms. The controllers control the transmission of the access request on the bus 201 based on the corresponding processing mechanisms.

[0039] The mechanism type of the processing mechanism has a corresponding relationship with different stages of the access request being transmitted on the bus 201, wherein the stage of the access request being transmitted from the host to the bus 201 corresponds to the first mechanism type, and the stage of the access request being transmitted from the bus 201 to the slave corresponds to the second mechanism type. Based on the mechanism type of the processing mechanism, the controller can be divided into controllers on different sides. The controller corresponding to the processing mechanism of the first mechanism type is the controller on the host side, and the controller corresponding to the processing mechanism of the second mechanism type is the controller on the slave side.

[0040] The hardware unit may transmit the access request to the corresponding host-side controller through the host interface, and the host-side controller transmits the access request to the bus 201. The access request may be transmitted to the slave-side controller through the bus 201, and the slave-side controller transmits the access request to the slave interface of the corresponding hardware unit.

[0041] In some examples, the at least one processing mechanism may include one or more processing mechanisms of a firewall mechanism, a bandwidth limitation (Bandwidth_Limit, BW_Limit) mechanism, a hang detection mechanism, and a hang protection mechanism. Among them, the bandwidth limitation mechanism and the hang detection mechanism are processing mechanisms of the first mechanism type, and the firewall mechanism and the hang protection mechanism are processing mechanisms of the second mechanism type.

[0042] Figure 3 FIG. 4 is a schematic diagram of an integrated circuit architecture provided by another exemplary embodiment of the present disclosure.

[0043] In some embodiments, if the controller group is configured to control the transmission of access requests on the bus 201 based on a firewall mechanism, a bandwidth limitation mechanism, a hang detection mechanism, and a hang protection mechanism, such as Figure 3 As shown in the above Figure 2On the basis of the illustrated architecture, the first controller group 2111 corresponding to the first hardware unit 211 and the second controller group 2211 corresponding to the second hardware unit 221 are used as an illustration. The first controller group 2111 and the second controller group 2211 respectively include four controllers, which can be hardware modules, such as a firewall module, a bandwidth limitation module, a deadlock detection module, and a deadlock protection module. Among them, the firewall module corresponds to the firewall mechanism, the bandwidth limitation module corresponds to the bandwidth limitation mechanism, the deadlock detection module corresponds to the deadlock detection mechanism, and the deadlock protection module corresponds to the deadlock protection mechanism. The bandwidth limitation module and the deadlock detection module are controllers on the host side, and the firewall module and the deadlock protection module are controllers on the slave side.

[0044] Understandably, Figure 3 The connection relationship between the hardware unit and the controller in the corresponding controller group, and between the controllers in the controller group is only shown for example, and the embodiments of the present disclosure do not limit this. For example, for the controller on the host side, the host can access the bus 201 through the deadlock detection module and the bandwidth limitation module in sequence; for the controller on the slave side, the slave can access the bus 201 through the firewall module and the deadlock protection module in sequence.

[0045] like Figure 2 As shown, the integrated circuit also includes a register 202, and the configuration information of the hardware unit can be pre-stored in the register 202. The configuration information of the hardware unit may include unmodifiable configuration information and modifiable configuration information. Among them, the modifiable configuration information may include configuration information related to the security level. For example, the configuration information related to the security level can be flexibly changed based on the change of the security level of the functional safety level domain corresponding to the hardware unit.

[0046] In some examples, the configuration information of the hardware unit may include first configuration information, and the first configuration information may include an identifier of a target hardware unit, and the security level of the functional safety level domain corresponding to the target hardware unit is higher than the security level of the functional safety level domain corresponding to the hardware unit. Exemplarily, the identifier of the target hardware unit may be an identifier (ID).

[0047] In some examples, the configuration information of the hardware unit may further include second configuration information, and the second configuration information may include permission information for the target hardware unit to access an address region, wherein the address region corresponds to the hardware unit.

[0048] In some embodiments, when hardware units in different functional safety level domains access each other, the controller group corresponding to the hardware unit can read the first configuration information and the second configuration information corresponding to the hardware unit from the corresponding register 202, and determine the access rights between the hardware units based on these configuration information, and then control the transmission of the access request on the bus based on the determined rights. Since the first configuration information and the second configuration information are related to the security level, it is equivalent to determining the access rights between the hardware units based on the security level. Accordingly, controlling the transmission of the access request on the bus based on the determined rights is equivalent to controlling the transmission of the access request on the bus based on the security level. If a problem occurs in the hardware unit in the functional safety level domain with a lower security level, it may cause a problem on the bus. Since the transmission of the first access request from the bus to the hardware unit in the functional safety level domain with a higher security level can be controlled, the first access request transmitted by the hardware unit in the functional safety level domain with a lower security level when a problem occurs can be controlled accordingly, so that the normal operation of the hardware unit in the functional safety level domain with a higher security level can be effectively guaranteed, thereby ensuring the security requirements of the functional safety level domain with a higher security level.

[0049] Exemplary Methods

[0050] Figure 4 1 is a flow chart of a bus access method provided by an exemplary embodiment of the present disclosure. This embodiment can be applied to an electronic device, which may include Figure 2 or Figure 3 In this embodiment, the access process between the first hardware unit 211 in the first functional safety level domain 21 and the second hardware unit 221 in the second functional safety level domain 22 is taken as an example to illustrate the bus access method in the integrated circuit. It can be understood that the bus access method in the integrated circuit can be applied to Figure 2 or Figure 3 Access between any hardware units in any functional safety level domain in the shown integrated circuit.

[0051] like Figure 4 As shown, the method includes the following steps 41 to 45.

[0052] Step 41: Generate a first access request through a first hardware unit in a first functional safety level domain.

[0053] If the first hardware unit 211 needs to access the second hardware unit 221 , the first hardware unit 211 generates a first access request as a host.

[0054] In some examples, the first access request may include a command issued to the second hardware unit 221, data transmitted to the second hardware unit 221, etc.

[0055] In some examples, the first access request may carry an identifier of the first hardware unit 211 (hereinafter, the identifier of the first hardware unit 211 will be referred to as the “first identifier”).

[0056] In some examples, the first access request may also carry information of the object requested to be accessed, such as the identifier of the second hardware unit 221 (hereinafter, the identifier of the second hardware unit 221 is referred to as the “third identifier”), the address requested to be accessed, and the like.

[0057] The first access request is transmitted from the first hardware unit 211 to the second hardware unit 221. Exemplarily, the first access request is transmitted from the host interface of the first hardware unit 211 to the controller on the host side of the first controller group 2111 corresponding to the first hardware unit 211, and then the first access request is transmitted from the controller on the host side to the bus 201; the first access request is transmitted from the bus 201 to the controller on the slave side of the second controller group 2211 corresponding to the second hardware unit 221, and then the first access request is transmitted from the controller on the slave side to the slave interface of the second hardware unit 221.

[0058] Steps 402 to 404 may be performed by a controller having an authentication function in a controller on the host side of the first controller group 2111 or a controller on the slave side of the second controller group 2211. Exemplarily, the firewall module in the controller on the slave side of the second controller group 2211 has an authentication function, and the first access request may be authenticated by the firewall module corresponding to the second hardware unit 221. The following embodiments are described by taking the firewall module corresponding to the second hardware unit 221 authenticating the first access request as an example.

[0059] Step 42: Based on the first access request, determine a first identifier of the first hardware unit.

[0060] Exemplarily, if the first access request carries the first identifier of the first hardware unit 211 , the firewall module corresponding to the second hardware unit 221 may determine the first identifier from the first access request.

[0061] Step 43: Read first configuration information corresponding to the second hardware unit in the second functional safety level domain from the register.

[0062] Exemplarily, if the first access request carries the third identifier of the second hardware unit 221, the firewall module corresponding to the second hardware unit 221 can determine the third identifier from the first access request. The firewall module corresponding to the second hardware unit 221 can read the configuration information corresponding to all the hardware units in the integrated circuit from the register 202, wherein the configuration information corresponding to each hardware unit has an index relationship with the corresponding hardware unit. For example, the index relationship can be an index relationship between the identifier of the hardware unit and the configuration information. The firewall module corresponding to the second hardware unit 221 can determine the configuration information corresponding to the second hardware unit 221 from the configuration information corresponding to all the hardware units based on the index relationship. Further, the firewall module corresponding to the second hardware unit 221 can determine the first configuration information corresponding to the second hardware unit 221 from the configuration information corresponding to the second hardware unit 221.

[0063] Among them, the first configuration information includes a second identifier of a target hardware unit whose security level of the functional safety level domain is higher than the security level of the second functional safety level domain 22. It can also be said that the target hardware unit has the authority to access the second hardware unit 221. It can be understood that a hardware unit whose security level of the functional safety level domain is lower than or equal to the security level of the second functional safety level domain 22 does not have the authority to access the second hardware unit 221. It can be seen that the high-low relationship between the security levels of the functional safety level domains corresponding to each hardware unit can be characterized by the access permissions between the hardware units.

[0064] Step 44: Based on the first identifier and the second identifier, determine the permission of the first hardware unit to access the second hardware unit.

[0065] The firewall module corresponding to the second hardware unit 221 can determine the authority of the first hardware unit 211 to access the second hardware unit 221 based on the first identifier and the second identifier, that is, can determine the relationship between the security levels of the first functional security level domain 21 corresponding to the first hardware unit 211 and the second functional security level domain 22 corresponding to the second hardware unit 221.

[0066] Exemplarily, if the first hardware unit 211 has permission to access the second hardware unit 221, it can be determined that the security level domain of the first functional security level domain 21 is higher than the security level of the second functional security level domain 22; if the first hardware unit 211 has permission to access the second hardware unit 221, it can be determined that the security level domain of the first functional security level domain 21 is lower than or equal to the security level of the second functional security level domain 22.

[0067] In some examples, the firewall module corresponding to the second hardware unit 221 can write the permission of the first hardware unit 211 to access the second hardware unit 221 into register 202, and the controllers in the first controller group 2111 and the second controller group 2211 can read the permission of the first hardware unit 211 to access the second hardware unit 221 from register 202.

[0068] In some examples, the firewall module corresponding to the second hardware unit 221 may transmit the permission of the first hardware unit 211 to access the second hardware unit 221 to the controllers in the first controller group 2111 and the second controller group 2211 .

[0069] Step 45: Based on the permission of the first hardware unit to access the second hardware unit, control the transmission of the first access request from the bus to the second hardware unit.

[0070] Exemplarily, based on the permission of the first hardware unit 211 to access the second hardware unit 221 being access permission, that is, based on the security level of the first functional safety level domain 21 corresponding to the first hardware unit 211 being higher than the security level of the second functional safety level domain 22 corresponding to the second hardware unit 221, the first access request can be transmitted from the bus 201 to the second hardware unit 221 through the controller on the host side in the first controller group 2111 and the controller on the slave side in the second controller group 2211 to avoid the influence of the second hardware unit 221 on the first hardware unit 211.

[0071] Based on the fact that the permission for the first hardware unit 211 to access the second hardware unit 221 is no access permission, that is, based on the fact that the security level of the first functional safety level domain 21 corresponding to the first hardware unit 211 is lower than or equal to the security level of the second functional safety level domain 22 corresponding to the second hardware unit 221, the first access request can be transmitted from the bus 201 to the second hardware unit 221 through the controller on the host side in the first controller group 2111 and the controller on the slave side in the second controller group 2211 to avoid the influence of the first hardware unit 211 on the second hardware unit 221.

[0072] In the bus access method in an integrated circuit provided by the embodiment of the present disclosure, when the first hardware unit 211 in the first functional safety level domain 21 accesses the second hardware unit 221 in the second functional safety level domain 22, based on the permission of the first hardware unit 211 to access the second hardware unit 221, that is, based on the security level relationship between the first functional safety level domain 21 corresponding to the first hardware unit 211 and the second functional safety level domain 22 corresponding to the second hardware unit 221, the first access request can be controlled to be transmitted from the bus 201 to the second hardware unit 221 through at least one controller of the host side controller in the first controller group 2111 corresponding to the first hardware unit 211 and the slave side controller in the second controller group 2211 corresponding to the second hardware unit 221, thereby avoiding the problem of the bus 201 caused by the hardware unit in the functional safety level domain with a lower security level, which affects the hardware unit in the functional safety level domain with a higher security level, thereby ensuring the security requirements of the functional safety level domain with a higher security level.

[0073] Figure 5 is a flowchart of a bus access method provided by another exemplary embodiment of the present disclosure.

[0074] In some embodiments, Figure 5 As shown in the above Figure 4 Based on the illustrated embodiment, the above step 44 may include step 441 and step 442.

[0075] Step 441: Determine the inclusion relationship between the second identifier and the first identifier.

[0076] The inclusion relationship between the second identifier and the first identifier includes that the second identifier includes the first identifier and the second identifier does not include the first identifier.

[0077] Exemplarily, if the target hardware unit corresponding to the second hardware unit 221 includes the first hardware unit 211 to the first hardware unit 21n, the first configuration information corresponding to the second hardware unit 221 includes the second identifiers corresponding to the first hardware unit 211 to the first hardware unit 21n, such as 211 to 21n. Accordingly, it can be determined that the inclusion relationship between the second identifier and the first identifier is that the second identifier includes the first identifier.

[0078] Exemplarily, if the target hardware unit corresponding to the second hardware unit 221 does not include the first hardware unit 211 to the first hardware unit 21n, the first configuration information corresponding to the second hardware unit 221 does not include the second identifier corresponding to the first hardware unit 211 to the first hardware unit 21n. Accordingly, it can be determined that the inclusion relationship between the second identifier and the first identifier is that the second identifier does not include the first identifier.

[0079] Step 442: Based on the inclusion relationship, determine the permission of the first hardware unit to access the second hardware unit.

[0080] If the second identifier includes the first identifier, it can be determined that the first hardware unit 211 has access rights to the second hardware unit 221. If the second identifier does not include the first identifier, it can be determined that the first hardware unit 211 has no access rights to the second hardware unit 221.

[0081] The bus access method in the integrated circuit provided by the embodiment of the present disclosure can quickly determine the permission of the first hardware unit 211 to access the second hardware unit 221 by determining the inclusion relationship between the first identifier of the first hardware unit 211 and the second identifier of the target hardware unit corresponding to the second hardware unit 221, thereby improving the efficiency of controlling the transmission of the first access request from the bus 201 to the second hardware unit 221.

[0082] Figure 6 It is a flowchart of a bus access method provided by yet another exemplary embodiment of the present disclosure.

[0083] In some embodiments, Figure 6 As shown in the above Figure 5 Based on the illustrated embodiment, the above step 442 may include steps 4421 to 4424.

[0084] Step 4421: If the inclusion relationship is that the second identifier includes the first identifier, read the second configuration information corresponding to the second hardware unit from the register.

[0085] If the inclusion relationship is that the second identifier includes the first identifier, it can be determined that the first hardware unit 211 has the authority to access the second hardware unit 221 .

[0086] In order to facilitate the management of the accessible space of the second hardware unit 221, such as to facilitate the rapid and accurate writing / reading of data from the accessible space of the second hardware unit 221, the accessible space of the second hardware unit 221 can be divided into at least one subspace, and the target hardware unit corresponding to the second hardware unit 221 can be restricted from accessing the at least one subspace. Based on this, the second configuration information can be pre-configured for the second hardware unit 221, and the second configuration information includes the permission information of the target hardware unit corresponding to the second hardware unit 221 to access the address area. The address area corresponds to the second hardware unit 221, and includes the addresses of each subspace in the accessible space of the second hardware unit 221. In some cases, the address area can also be referred to as an address range.

[0087] In some examples, the permission information may include the permission of the target hardware unit to access each address in the address area, for example, whether the target hardware unit has permission to access the address; if the target hardware unit has permission to access the address, the access type (such as write access, read access, etc.) that the target hardware unit can access to the address, etc.

[0088] In some examples, after the firewall module corresponding to the second hardware unit 221 reads the configuration information corresponding to the second hardware unit 221 from the register 202 , the second configuration information corresponding to the second hardware unit 221 can be determined from the configuration information corresponding to the second hardware unit 221 .

[0089] Step 4422: Determine the permission information of the target hardware unit to access the address area from the second configuration information.

[0090] The firewall module corresponding to the second hardware unit 221 can determine the authority of each target hardware unit to access the address area of ​​the second hardware unit 221 from the content included in the second configuration information corresponding to the second hardware unit 221 .

[0091] Step 4423: Based on the permission information, determine the permission of the first hardware unit to access each address in the address area.

[0092] The firewall module corresponding to the second hardware unit 221 can determine the permission information corresponding to the first hardware unit 211 from the permission information corresponding to each target hardware unit, and based on the permission information corresponding to the first hardware unit 211, determine the permission of the first hardware unit 211 to access each address in the address area corresponding to the second hardware unit 221.

[0093] Exemplarily, the address area corresponding to the second hardware unit 221 includes address 2a, address 2b, and address 2c, and the second configuration information corresponding to the second hardware unit 221 includes permission information corresponding to the first hardware unit 211, and the permission information may include that the first hardware unit 211 has permission to access address 2a, but does not have permission to access address 2b and address 2c. Based on the permission information, the firewall module corresponding to the second hardware unit 221 may determine the permission of the first hardware unit 211 to access address 2a, address 2b, and address 2c.

[0094] Step 4424: Based on the permission of the first hardware unit to access each address in the address area, determine the permission of the first hardware unit to access the second hardware unit.

[0095] The permission for the first hardware unit 211 to access the second hardware unit 221 is to have permission to access the second hardware unit 221 and have access rights to at least one address in the address area corresponding to the second hardware unit 221, but have no access rights to other addresses in the address area.

[0096] The bus access method in an integrated circuit provided by the embodiment of the present disclosure can effectively limit the accessible space allowed to be accessed by the host when the hardware unit acts as a slave, by pre-configuring the second configuration information for the hardware unit, thereby facilitating more accurate and detailed management of the accessible space of each hardware unit.

[0097] Figure 7 It is a flowchart of a bus access method provided by yet another exemplary embodiment of the present disclosure.

[0098] In some embodiments, Figure 7 As shown in the above Figure 4 Based on the illustrated embodiment, the above step 45 may include steps 451 to 453.

[0099] Step 451: Based on the permission of the first hardware unit to access the second hardware unit, determine a processing mechanism for transmitting a first access request from the bus to the second hardware unit.

[0100] Each processing mechanism is mainly used to avoid the influence of hardware units in a functional safety level domain with a low security level on hardware units in a functional safety level domain with a high security level, especially to avoid the influence of hardware units in a functional safety level domain with a low security level on hardware units in a functional safety level domain with a high security level when problems occur. Based on this, based on the permission of the first hardware unit 211 to access the second hardware unit 221, that is, based on the high and low relationship between the security levels of the first functional safety level domain 21 and the second functional safety level domain 22, the processing mechanism for controlling the transmission of the first access request can be determined.

[0101] Among them, in response to the first hardware unit 211 having no access permission to the second hardware unit 221, that is, the security level of the first functional safety level domain 21 is lower than or equal to the security level of the second functional safety level domain 22, in order to avoid the influence of the first hardware unit 211 on the second hardware unit 221, a first processing mechanism for transmitting the first access request from the bus 201 to the second hardware unit 221 can be determined.

[0102] In some examples, the first processing mechanism may include one or more of a firewall mechanism and a bandwidth limiting mechanism.

[0103] In response to the first hardware unit 211 having access permission to the second hardware unit 221, that is, the security level of the first functional safety level domain 21 is higher than the security level of the second functional safety level domain 22, in order to avoid the influence of the second hardware unit 221 on the first hardware unit 211, a second processing mechanism for transmitting the first access request from the bus 201 to the second hardware unit 221 can be determined.

[0104] In some examples, the second processing mechanism may include one or more of a hang detection mechanism and a hang protection mechanism.

[0105] Step 452: Based on the processing mechanism, determine the target controller to which the first access request needs to be transmitted via the bus.

[0106] The mechanism type corresponding to the processing mechanism can be determined. For example, if the processing mechanism is a firewall mechanism, it can be determined that the firewall mechanism corresponds to the second mechanism type. For another example, if the processing mechanism is a bandwidth limitation mechanism, it can be determined that the bandwidth limitation mechanism corresponds to the first mechanism type.

[0107] Based on the mechanism type corresponding to the processing mechanism, the target controller that needs to transmit the first access request through the bus 201 can be determined, that is, the target controller used to control the transmission of the first access request through the bus 201. Specifically, based on the processing mechanism corresponding to the first mechanism type, the target controller can be determined to be a controller in the first controller group 2111 corresponding to the first hardware unit 211 for executing the processing mechanism; based on the processing mechanism corresponding to the second mechanism type, the target controller can be determined to be a controller in the second controller group 2211 corresponding to the second hardware unit 221 for executing the processing mechanism.

[0108] In some examples, based on the first processing mechanism, the first controller may be determined to be a target controller that needs to transmit the first access request via the bus. Based on the first processing mechanism, a corresponding mechanism type may be determined, and based on the mechanism type corresponding to the first processing mechanism, a target controller for executing the first processing mechanism may be determined.

[0109] Exemplarily, if the first processing mechanism includes a firewall mechanism and a bandwidth limitation mechanism, it can be determined that the first controller corresponding to the firewall mechanism is the firewall module corresponding to the second hardware unit 221, and the first controller corresponding to the bandwidth limitation mechanism is the bandwidth limitation module corresponding to the first hardware unit 211.

[0110] In some examples, based on the second processing mechanism, the second controller may be determined as a target controller that needs to transmit the first access request via the bus. Based on the second processing mechanism, a corresponding mechanism type may be determined, and based on the mechanism type corresponding to the second processing mechanism, a target controller for executing the second processing mechanism may be determined.

[0111] Exemplarily, if the second processing mechanism includes a hang detection mechanism and a hang protection mechanism, it can be determined that the second controller corresponding to the hang detection mechanism is the hang detection module corresponding to the first hardware unit 211, and the second controller corresponding to the hang protection mechanism is the hang protection module corresponding to the second hardware unit 221.

[0112] Step 453: Control the transmission of the first access request from the bus to the hardware unit corresponding to the target controller.

[0113] The target controller controls the transmission of the first access request from the bus 201 to the hardware unit corresponding to the target controller based on the corresponding processing mechanism.

[0114] For example, if the target controller is a bandwidth limitation module corresponding to the first hardware unit 211, the hardware unit corresponding to the target controller is the second hardware unit 221; if the target controller is a deadlock detection module corresponding to the first hardware unit 211, the hardware unit corresponding to the target controller is the second hardware unit 221; if the target controller is a firewall module corresponding to the second hardware unit 221, the hardware unit corresponding to the target controller is the second hardware unit 221; if the target controller is a deadlock protection module corresponding to the second hardware unit 221, the hardware unit corresponding to the target controller is the first hardware unit 211.

[0115] The bus access method in the integrated circuit provided by the embodiment of the present disclosure can accurately determine the processing mechanism required for controlling the transmission of the first access request based on the permission of the first hardware unit 211 to access the second hardware unit 221, and then accurately determine the target controller that needs to execute the processing mechanism, and control the transmission of the first access request through the target controller. Therefore, on the basis of effectively avoiding the influence of the hardware units in the functional safety level domain with a lower security level on the hardware units in the functional safety level domain with a higher security level, non-target controllers other than the target controller will not participate in controlling the transmission of the first access request. Therefore, the non-target controller will not interfere with the transmission of the first access request, and the power consumption generated can also be reduced.

[0116] The following describes how the target controller controls the transmission of the first access request from the bus to the hardware unit corresponding to the target controller based on the corresponding processing mechanism.

[0117] In some embodiments, the processing mechanism is a first processing mechanism, such as a firewall mechanism, and the target controller is a firewall module corresponding to the second hardware unit 221 .

[0118] Accordingly, the method of controlling the transmission of the first access request from the bus 201 to the hardware unit corresponding to the target controller may include: intercepting the transmission of the first access request from the bus to the hardware unit corresponding to the first controller.

[0119] Exemplarily, the first access request is transmitted from the bus 201 to the firewall module corresponding to the second hardware unit 221 , and the firewall module intercepts the first access request to prevent the first access request from continuing to be transmitted to the second hardware unit 221 .

[0120] In some examples, the firewall module corresponding to the second hardware unit 221 can generate response information based on the first access request, such as a response error, and the first hardware unit 211 can determine that it does not have permission to access the second hardware unit 221 based on the response information.

[0121] In some examples, the firewall module corresponding to the second hardware unit 221 can process the data corresponding to the first access request based on the request type corresponding to the first access request. If the request type corresponding to the first access request is a read data request, the firewall module can generate a preset value, such as a value of 0; if the request type corresponding to the first access request is a write data request, the firewall module can discard the write data corresponding to the first access request.

[0122] In some examples, the firewall module corresponding to the second hardware unit 221 may generate an interrupt signal corresponding to the first access request, and the interrupt signal is used to indicate interruption of the access of the first hardware unit 211 to the second hardware unit 221. Accordingly, a record of interruption of the access of the first hardware unit 211 to the second hardware unit 221 may be written into the register 202, and the record may be queried and processed, such as clearing, shielding, etc.

[0123] The bus access method in the integrated circuit provided by the embodiment of the present disclosure can effectively restrict the access of the hardware units in the functional safety level domain of the low security level to the hardware units in the functional safety level domain of the high security level by intercepting the access request transmitted by the hardware units in the functional safety level domain of the low security level to the hardware units in the functional safety level domain of the high security level. Therefore, if there is a problem with the hardware units in the functional safety level domain of the low security level, the hardware units in the functional safety level domain of the high security level can still work normally.

[0124] In some embodiments, the processing mechanism is a first processing mechanism, such as a bandwidth limiting mechanism, and the target controller is a bandwidth limiting module corresponding to the first hardware unit 211 .

[0125] Correspondingly, the method of controlling the transmission of the first access request from the bus to the hardware unit corresponding to the target controller may include: determining the first bandwidth threshold corresponding to the first hardware unit 211 based on the security level of the first functional safety level domain 21; based on the first bandwidth threshold, controlling the transmission of the first access request from the bus 201 to the hardware unit corresponding to the first controller.

[0126] The register 202 may pre-configure the correspondence between each security level and the bandwidth threshold, and the bandwidth threshold represents the maximum value of the bus bandwidth that each hardware module in the functional safety level domain of the corresponding security level can use when accessing the bus. The bandwidth limitation module corresponding to the first hardware unit 211 may read the correspondence from the register 202, and determine the first bandwidth threshold corresponding to the first hardware unit 211 based on the security level of the first functional safety level domain 21. Subsequently, the bandwidth limitation module corresponding to the first hardware unit 211 may determine the bus bandwidth currently used by the first hardware unit 211, such as the first bandwidth.

[0127] In some examples, the bandwidth thresholds corresponding to different security levels can be determined based on the security level and the bus bandwidth. For example, the higher the security level, the higher the proportion of the corresponding bus bandwidth, and the lower the security level, the lower the proportion of the corresponding bus bandwidth. Therefore, the bandwidth threshold corresponding to the security level is the product of the proportion of the bus bandwidth corresponding to the security level and the bus bandwidth. It can be understood that, when the bus bandwidth is constant, the higher the security level, the higher the corresponding bandwidth threshold, and the lower the security level, the lower the corresponding bandwidth threshold.

[0128] Correspondingly, the higher the security level, the higher the corresponding bandwidth threshold, which ensures that the hardware units in the functional safety level domain with a high security level can use more bus bandwidth; the lower the security level, the lower the corresponding bandwidth threshold, which prevents the hardware units in the functional safety level domain with a low security level from occupying too much bus bandwidth, so as to free up more bus bandwidth for the hardware units in the functional safety level domain with a high security level.

[0129] In some examples, the bandwidth limiting module can determine the bus transmission bandwidth corresponding to the access request of the first hardware unit 211 to complete the transmission within a preset unit time. Among them, the bus transmission bandwidth corresponding to the read channel and the write channel of the first hardware unit 211 within the preset unit time can be determined, and the sum of the bus transmission bandwidths corresponding to the read channel and the write channel can be calculated. By calculating the ratio of the bus transmission bandwidth corresponding to the access request of the first hardware unit 211 to complete the transmission within the preset unit time to the preset unit time, the first bandwidth corresponding to the first hardware unit 211 can be obtained.

[0130] The bandwidth limiting module controls the transmission of the first access request from the bus 201 to the hardware unit corresponding to the first controller based on the first bandwidth and the first bandwidth threshold. The first controller is the bandwidth limiting module, and the hardware unit corresponding to the bandwidth limiting module is the second hardware unit 221 .

[0131] Among them, if the first bandwidth is less than the first bandwidth threshold, the bandwidth limitation module does not limit the transmission of the first access request; if the first bandwidth is greater than or equal to the first bandwidth threshold, the bandwidth limitation module limits the transmission of the first access request, for example, intercepting the transmission of the first access request to the bus 201, or reducing the number of first access requests transmitted to the bus 201 per unit time, thereby reducing the occupation of the bus bandwidth by the first hardware unit 211.

[0132] The bus access method in an integrated circuit provided by the embodiment of the present disclosure effectively limits the bus bandwidth occupied by hardware units in a functional safety level domain with a low security level by allocating different bandwidth thresholds to different security levels and controlling the bus bandwidth occupied by access requests transmitted by hardware units to not exceed the corresponding bandwidth thresholds, thereby reducing the encroachment of the bus bandwidth by hardware units in a functional safety level domain with a low security level and ensuring that hardware units in a functional safety level domain with a high security level can use more bus bandwidth.

[0133] In some embodiments, the processing mechanism is a second processing mechanism, such as a hang detection mechanism, and the target controller is a hang detection module corresponding to the first hardware unit 211 .

[0134] Correspondingly, the method of controlling the transmission of the first access request from the bus 201 to the hardware unit corresponding to the target controller may include: determining the target access request whose response has timed out in the first access request; generating an interrupt signal corresponding to the target access request, which interrupt signal can be used to indicate the interrupt processing of the target access request; based on the interrupt signal, controlling the transmission of the first access request from the bus 201 to the hardware unit corresponding to the second controller.

[0135] The hang detection module corresponding to the first hardware unit 211 can read the duration threshold from the register 202, and monitor each first access request based on the duration threshold. If the response information of the second hardware unit 221 to the first access request is detected within the duration threshold, the first access request is a normal access request. If the response information of the second hardware unit 221 to the first access request is not detected within the duration threshold, the first access request is a target access request with a timeout response.

[0136] The deadlock detection module can count the first access requests that have not been responded to through a counter, wherein when the first hardware unit generates a first access request, the value of the counter is increased by 1, and after a first access request is responded to, the value of the counter is reduced by 1, and when the value of the counter is 0, it indicates that there is no first access request that has not been responded to at present, and when the value of the counter is not 0, it indicates that there is a first access request that has not been responded to at present. If the value of the counter is not 0 when the duration threshold is reached, it indicates that there is a first access request that has not been responded to, and the first access request that has not been responded to is the target access request.

[0137] In some examples, the hang detection module may determine the first access request corresponding to the same second hardware unit 221 , and perform timeout monitoring on the first access request corresponding to the same second hardware unit 221 .

[0138] Among them, the hanging detection module can perform independent timeout monitoring on each first access request. The hanging detection module creates a corresponding timer for each first access request. If the hanging detection module fails to detect a response from the second hardware unit 221 to the corresponding first access request before the duration of the timer reaches a duration threshold, it is determined that the first access request response has timed out and is a target access request.

[0139] Alternatively, the deadlock detection module may monitor the timeout of the first access request corresponding to the same channel type as a whole, wherein the channel type of the data channel between the first hardware unit 211 and the second hardware unit 221 may include a write channel, a read channel and an auxiliary channel (Auxiliary Channel, AC). The first access request corresponding to the write channel may be monitored as a whole, and the first access request corresponding to the read channel may be monitored as a whole. When the first access request is monitored as a whole, a corresponding timer is created for the corresponding channel. The timer starts counting from the first time when the value of the counter is not 0, and the timer restarts counting each time any first access request on the channel is detected to be responded to. If the deadlock detection module does not detect that any first access request on the corresponding channel is responded to before the timer reaches the time threshold, it is determined that the response of the first access request corresponding to the channel has timed out and is a target access request. Corresponding to the first access request of the auxiliary channel, the deadlock detection module performs independent timeout monitoring on each first access request, which is not described here.

[0140] In some examples, the hang detection module may perform timeout monitoring on first access requests corresponding to the same channel type as a whole, wherein the first access requests corresponding to the same channel type may include first access requests corresponding to different second hardware units 221 .

[0141] Among them, the first access request corresponding to the write channel can be monitored as a whole, the first access request corresponding to the read channel can be monitored as a whole, and the first access request corresponding to the auxiliary channel can be monitored as a whole. When the first access request is monitored as a whole, a corresponding timer is created for the corresponding channel. The timer starts timing from the first time the value of the counter is not 0. After each detection of a response to any first access request on the channel, the timer restarts timing. If the deadlock detection module does not detect that any first access request on the corresponding channel has been responded to before the timer reaches the time threshold, it is determined that the response to the first access request corresponding to the channel has timed out and is a target access request.

[0142] If the hang detection module determines that there is a target access request, it can be determined that the first hardware unit 211 is in a hang state. Then, the hang detection module corresponding to the first hardware unit 211 interrupts the processing of the target access request based on the interrupt signal to interrupt the first hardware unit 211's access to the second hardware unit 221.

[0143] In some examples, the hang detection module may write a record of generating an interrupt signal into register 202, and other hardware units may read the corresponding record from register 202 when accessing the first hardware unit 211, thereby avoiding accessing the first hardware unit 211 in a hang state.

[0144] The bus access method in an integrated circuit provided by the embodiment of the present disclosure determines whether the first hardware unit 211 is in a hung state by detecting a target access request with a timed-out response in a first access request, and issues an alarm when it is determined that the first hardware unit 211 is in a hung state, such as generating an interrupt signal, writing a record of generating the interrupt signal in the register 202, etc., so that when a hardware unit in a functional safety level domain with a high safety level needs to access the first hardware unit 211, it can be determined that the first hardware unit 211 is in a hung state, and further access to the first hardware unit 211 can be avoided, thereby avoiding the impact of access to the first hardware unit 211 on itself.

[0145] In some embodiments, the processing mechanism is a second processing mechanism, such as a deadlock protection mechanism, and the target controller is a deadlock protection module corresponding to the second hardware unit 221 .

[0146] Correspondingly, the method of controlling the transmission of the first access request from bus 201 to the hardware unit corresponding to the target controller may include: determining the target access request whose response has timed out in the first access request; generating response information for the target access request; and controlling the transmission of the response information from bus 201 to the hardware unit corresponding to the second controller.

[0147] The deadlock protection modules corresponding to the second hardware unit 221 respectively perform timeout monitoring on the first access requests corresponding to the same channel type.

[0148] In some examples, the deadlock protection module monitors each first access request for timeout according to the transmission order of each first access request, and after monitoring the first target access request, all first access requests whose transmission order is after the first target access request can be determined as target access requests.

[0149] In some examples, during the process of determining the target access request, the deadlock protection module monitors corresponding items in the first access request through a monitoring policy corresponding to the request type to determine the error type that causes the response timeout.

[0150] Exemplarily, for the read command request in the first access request, the monitored items may include whether the handshake of each command channel is successful, whether the handshake of the read last data signal (RLAST) corresponding to each command is successful, and whether the number of successfully transmitted read data (RDATA) meets the requirements of the current command.

[0151] Exemplarily, for the write command request in the first access request, the monitored items may include whether the handshake of each command channel is successful, whether the handshake returned by the write response signal (BRESP) corresponding to each command is successful, and whether the number of successfully transmitted write data (WDATA) meets the requirements of the current command.

[0152] In some examples, the deadlock protection module may write information corresponding to the first target access request, such as the request type, error type, etc., into register 202 .

[0153] In some examples, the deadlock protection module may determine a corresponding response mechanism based on a request type and an error type corresponding to a target access request, and generate response information based on the response mechanism.

[0154] Exemplarily, for the read command request in the first access request, the corresponding response mechanism can be determined based on the error type corresponding to the read command request. The response mechanism can include constructing a read address ready signal (ARREADY) to complete the reception of the corresponding command; constructing a less-sent read data / read data valid signal (RVALID) and returning all-0 read data; constructing a read last data signal / read response signal (RRESP) and returning a response error; discarding more-sent read data; discarding any signal of downstream multiple transmissions, and making corresponding records.

[0155] Exemplarily, for the write command request in the first access request, the corresponding response mechanism can be determined based on the error type corresponding to the write command request. The response mechanism can include constructing a write address ready signal (AWREADY) to complete the reception of the corresponding command; constructing a write address ready signal to complete the reception of write data and discarding the write data; constructing a write response valid signal (BVALID) / write response signal corresponding to the under-sent write data and returning a response error; constructing a write response valid signal / write response signal and returning a response error; discarding any signal of downstream multiple transmission and making corresponding records.

[0156] In some examples, the information of the first target access request can be read from register 202, and the request type of the first target access request can be determined based on the information. Since other target access requests corresponding to the same channel type as the first target access request correspond to the same request type as the first target access request, the request types of other target access requests can be quickly determined based on the request type of the first target access request. For non-first target access requests, a response mechanism can be determined based on the request type, and response information can be generated based on the response mechanism.

[0157] Exemplarily, for a non-first target access request whose request type is a read command request, the response mechanism may include constructing a read address ready signal reception, and returning read data of all 0s and a response error.

[0158] Exemplarily, for a non-first target access request whose request type is a write command request, the response mechanism may include constructing a write address ready signal reception, discarding all received write data, and returning a response error.

[0159] The hardware unit corresponding to the deadlock protection module is the first hardware unit 211. The deadlock protection module controls the transmission of response information from the bus 201 to the first hardware unit 211, so that when the second hardware unit 221 is in a deadlock state, the response information constructed by the deadlock protection module is sent to the first hardware unit 211 to end the access of the first hardware unit 211 to the second hardware unit 221, thereby avoiding the deadlock of the first hardware unit 211.

[0160] The bus access method in an integrated circuit provided by the embodiment of the present disclosure can, after determining that the response of the hardware unit in the functional safety level domain of the low security level to the access request of the hardware unit in the functional safety level domain of the high security level has timed out, end the current access by constructing a response message and transmitting the response message to the hardware unit in the functional safety level domain of the high security level. In this way, when the hardware unit in the functional safety level domain of the low security level is in a hung state, the hardware unit in the functional safety level domain of the high security level can still get a response and can still work normally.

[0161] Exemplary Electronic Devices

[0162] Figure 8 It is a structural schematic diagram of an electronic device provided by an exemplary embodiment of the present disclosure.

[0163] like Figure 8 As shown, the electronic device includes an integrated circuit 81, which may be Figure 2 or Figure 3 The integrated circuit 81 includes at least one processor 811 and a memory 812 .

[0164] The processor 811 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0165] The memory 812 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 811 may execute one or more computer program instructions to implement the desired functions of the electronic device. The bus access method and / or other desired functions of the various embodiments of the present disclosure described above.

[0166] In one example, the electronic device may further include: an input device 82 and an output device 83, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0167] Of course, to simplify, Figure 8 Only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device may further include any other appropriate components.

[0168] Exemplary computer program products and computer-readable storage media

[0169] In addition to the above-mentioned methods and devices, embodiments of the present disclosure may also provide a computer program product, including computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the bus access method of various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section.

[0170] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0171] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, the processor executes the steps of the bus access method of various embodiments of the present disclosure described in the above “Exemplary Method” section.

[0172] Computer readable storage media can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium is, for example, but not limited to, a system, device or device including electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0173] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and cannot be considered as necessary for each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, rather than limitation, and the above details do not limit the present disclosure to being implemented by adopting the above specific details.

[0174] Those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present disclosure claims and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A bus access method in an integrated circuit, comprising: generating a first access request by a first hardware unit in a first functional safety level domain; Determining a first identifier of the first hardware unit based on the first access request; Reading first configuration information corresponding to a second hardware unit in a second functional safety level domain from a register, wherein the first configuration information includes a second identifier of a target hardware unit whose functional safety level domain has a higher security level than the second functional safety level domain; Determining permission for the first hardware unit to access the second hardware unit based on the first identifier and the second identifier; Based on the permission of the first hardware unit to access the second hardware unit, control the transmission of the first access request from a bus to the second hardware unit.

2. The bus access method in an integrated circuit according to claim 1, wherein: The determining, based on the first identifier and the second identifier, permission for the first hardware unit to access the second hardware unit includes: Determine a containment relationship between the second identifier and the first identifier; Based on the inclusion relationship, permission for the first hardware unit to access the second hardware unit is determined.

3. The bus access method in an integrated circuit according to claim 2, wherein: The determining, based on the inclusion relationship, the permission for the first hardware unit to access the second hardware unit includes: If the inclusion relationship indicates that the second identifier includes the first identifier, second configuration information corresponding to the second hardware unit is read from the register; Determining permission information of the target hardware unit to access an address region from the second configuration information, wherein the address region corresponds to the second hardware unit; Based on the permission information, determining the permission of the first hardware unit to access each address in the address area; Based on the permission of the first hardware unit to access each address in the address area, the permission of the first hardware unit to access the second hardware unit is determined.

4. The bus access method in an integrated circuit according to any one of claims 1 to 3, wherein: The controlling the transmission of the first access request from a bus to the second hardware unit based on the permission of the first hardware unit to access the second hardware unit comprises: Based on the permission of the first hardware unit to access the second hardware unit, determining a processing mechanism for transmitting the first access request from the bus to the second hardware unit; Based on the processing mechanism, determining a target controller to which the first access request needs to be transmitted via the bus; Controlling transmission of the first access request from the bus to a hardware unit corresponding to the target controller.

5. The bus access method in an integrated circuit according to claim 4, wherein: The determining, based on the permission of the first hardware unit to access the second hardware unit, a processing mechanism for transmitting the first access request from the bus to the second hardware unit comprises: In response to the permission of the first hardware unit to access the second hardware unit being no access permission, determining a first processing mechanism for transmitting the first access request from the bus to the second hardware unit; Alternatively, in response to the first hardware unit having access rights to the second hardware unit, a second processing mechanism for transmitting the first access request from the bus to the second hardware unit is determined.

6. The bus access method in an integrated circuit according to claim 4, wherein: The determining, based on the processing mechanism, a target controller that needs to transmit the first access request through the bus includes: Based on the first processing mechanism, determining that the first controller is a target controller that needs to transmit the first access request through the bus; Alternatively, based on the second processing mechanism, it is determined that the second controller is a target controller that needs to transmit the first access request through the bus.

7. The bus access method in an integrated circuit according to claim 6, wherein: The controlling the transmission of the first access request from the bus to a hardware unit corresponding to the target controller includes: The first access request is intercepted and transmitted from the bus to a hardware unit corresponding to the first controller.

8. The bus access method in an integrated circuit according to claim 4, wherein: The controlling the transmission of the first access request from the bus to a hardware unit corresponding to the target controller includes: Determining a first bandwidth threshold corresponding to the first hardware unit based on the security level of the first functional safety level domain; Based on the first bandwidth threshold, control is performed to transmit the first access request from the bus to a hardware unit corresponding to the first controller.

9. The bus access method in an integrated circuit according to claim 4, wherein: The controlling the transmission of the first access request from the bus to a hardware unit corresponding to the target controller includes: Determine a target access request whose response has timed out in the first access request; generating an interrupt signal corresponding to the target access request; Based on the interrupt signal, control is performed to transmit the interrupt signal from the bus to a hardware unit corresponding to the second controller.

10. The bus access method in an integrated circuit according to claim 4, wherein: The controlling the transmission of the first access request from the bus to a hardware unit corresponding to the target controller includes: Determine a target access request whose response has timed out in the first access request; Generate response information of the target access request; Controlling the transmission of the response information from the bus to a hardware unit corresponding to the second controller.

11. An integrated circuit comprising: Controller; A first hardware unit corresponding to a first functional safety level domain; A second hardware unit corresponding to a second functional safety level domain; a register storing first configuration information corresponding to the second hardware unit, the first configuration information including a second identifier of a target hardware unit having a safety level of a functional safety level domain higher than a safety level of the second functional safety level domain; in, The first hardware unit is used to generate a first access request; The controller is used to determine a first identifier of the first hardware unit based on the first access request; The controller is further configured to read the first configuration information from the register; The controller is further configured to determine the permission of the first hardware unit to access the second hardware unit based on the first identifier and the second identifier; The controller is further configured to control transmission of the first access request from the bus to the second hardware unit based on permission of the first hardware unit to access the second hardware unit.

12. A computer-readable storage medium storing a computer program, wherein the computer program is used to execute the bus access method in an integrated circuit according to any one of claims 1 to 10.

13. An electronic device, comprising: processor; a memory for storing instructions executable by the processor; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the bus access method in the integrated circuit according to any one of claims 1 to 10; or, The electronic device comprises the integrated circuit as claimed in claim 11.

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