Level conversion circuit, memory and electronic equipment

Abstract

The invention discloses a level conversion circuit, a memory and electronic equipment, the level conversion circuit comprises a pull-down module, an output module and a clamping module connected between the pull-down module and the output module, and the clamping module is connected between the pull-down module and the output module. According to the technical scheme, the clamping module can reduce the withstand voltage value of the pull-down module according to the bias voltage, so that the withstand voltage value required by the pull-down module is reduced, the pull-down module is facilitated to adopt a low-voltage device with a lower withstand voltage value, and compared with the pull-down module adopting a high-voltage device with a higher withstand voltage value, the occupied area of the pull-down module is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a level conversion circuit, a memory, and an electronic device. Background Art

[0002] There are many types of level conversion circuits. One type of level conversion circuit has a static power consumption close to zero, and is therefore often used in large-scale applications.

[0003] However, the level conversion circuit with nearly zero static power consumption usually has a large pull-down network to ensure normal operation, which will introduce excessive area overhead. Summary of the invention

[0004] The present application provides a level conversion circuit, a memory and an electronic device to alleviate the technical problem that a pull-down module occupies a large area.

[0005] In a first aspect, the present application provides a level conversion circuit, which includes a pull-down module, an output module, and a clamping module connected between the pull-down module and the output module; the clamping module is used to reduce the withstand voltage value of the pull-down module according to a bias voltage.

[0006] In a second aspect, the present application provides a memory, which includes the above-mentioned level conversion circuit.

[0007] In a third aspect, the present application provides an electronic device, which includes a device body and the above-mentioned level conversion circuit arranged in the device body, or the electronic device includes the above-mentioned memory.

[0008] The level conversion circuit, memory and electronic device provided in the present application can connect a clamping module between the pull-down module and the output module, so that the clamping module can reduce the withstand voltage of the pull-down module according to the bias voltage, thereby reducing the withstand voltage required for the pull-down module, which is conducive to the pull-down module using low-voltage devices with lower withstand voltage values. Compared with the pull-down module using high-voltage devices with higher withstand voltage values, this reduces the occupied area of ​​the pull-down module. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0010] Figure 1 A first circuit schematic diagram of a level conversion circuit provided in an embodiment of the present application.

[0011] Figure 2 A second circuit schematic diagram of the level conversion circuit provided in an embodiment of the present application.

[0012] Figure 3 A timing diagram of a level conversion circuit without a pull-up module provided in an embodiment of the present application.

[0013] Figure 4 A timing diagram of a pull-up module in a level conversion circuit provided in an embodiment of the present application.

[0014] Figure 5 A timing diagram of a level conversion circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0015] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0016] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0017] In large-capacity memory arrays and large-scale mixed-analog circuits, a very large number of level conversion circuits are required to realize low-voltage logic control of high-voltage analog parts for circuit operation. One type of level conversion circuit has a static power consumption close to zero, so it is often used in large-scale applications.

[0018] Among them, the level conversion circuit includes a connected pull-up network (output module) and a pull-down network (pull-down module). The output end of the pull-up network has a full high-voltage swing (VDDH), so the pull-down network must use high-voltage devices, and the input signal (IN / INB) connected to the pull-down network has a full low-voltage swing (VDDL). Therefore, the ability of the pull-down network is weaker than that of the pull-up network. In order to ensure that the potential of the output end of the pull-up network can be reliably pulled down, it is usually necessary to increase the size of the pull-down network to be large enough to ensure that the level conversion circuit can be successfully flipped.

[0019] In addition, if the power consumption of the low-voltage part is further reduced by lowering the power supply voltage (VDDL) of the low-voltage control logic, the input pair tube in the pull-down network will enter the subthreshold region, and its pull-down capability will be weaker. In order to ensure normal operation, a larger input pair tube is required, which will further increase the area overhead and worsen the delay and power consumption.

[0020] This embodiment provides a level conversion circuit. Figures 1 to 5 ,like Figure 1 and Figure 2 As shown, the level conversion circuit includes a pull-down module 10, an output module 20, and a clamping module 30 connected between the pull-down module 10 and the output module 20; the clamping module 30 is used to reduce the withstand voltage value of the pull-down module 10 according to the bias voltage VB_LS.

[0021] It can be understood that the level conversion circuit provided in the present application, by connecting the clamping module 30 between the pull-down module 10 and the output module 20, can enable the clamping module 30 to reduce the withstand voltage of the pull-down module 10 according to the bias voltage VB_LS, thereby reducing the withstand voltage required by the pull-down module 10, which is conducive to the pull-down module 10 using low-voltage devices with lower withstand voltage values. Compared with the pull-down module 10 using high-voltage devices with higher withstand voltage values, this reduces the occupied area of ​​the pull-down module 10.

[0022] It should be noted that the bias voltage VB_LS may be less than or equal to a preset voltage.

[0023] In some embodiments, such as Figure 1 and Figure 2 As shown, the clamping module 30 includes a first transistor MN5 and a second transistor MN6, the first electrode of the first transistor MN5 is connected to the first end of the pull-down module 10, the second electrode of the first transistor MN5 is connected to the first end of the output module 20, and the control electrode of the first transistor MN5 is connected to the bias voltage VB_LS; the first electrode of the second transistor MN6 is connected to the second end of the pull-down module 10, the second electrode of the second transistor MN6 is connected to the second end of the output module 20, and the control electrode of the second transistor MN6 is connected to the control electrode of the first transistor MN5.

[0024] It should be noted that the channel type of the first transistor MN5 can be the same as the channel type of the second transistor MN6, for example, both are N-channel field effect transistors or bipolar junction transistors. The first electrode can be one of the source and the drain, the second electrode can be the other of the source and the drain, and the control electrode can be the gate. In other embodiments, the first electrode can be one of the collector and the emitter, the second electrode can be the other of the collector and the emitter, and the control electrode can be the base. Among them, the preset voltage is related to the threshold voltage of the first transistor MN5 or the threshold voltage of the second transistor MN6.

[0025] Among them, the first transistor MN5 and the second transistor MN6 can be high-voltage devices. Since the first transistor MN5 and the second transistor MN6 do not need to have strong pull-down or pull-up capabilities, the first transistor MN5 and the second transistor MN6 can be configured to have a smaller size to reduce the overall occupied area of ​​the level conversion circuit.

[0026] In some embodiments, such as Figure 1 and Figure 2 As shown, the pull-down module 10 includes a third transistor MN1 and a fourth transistor MN2, the first electrode of the third transistor MN1 is connected to the first electrode of the first transistor MN5, the second electrode of the third transistor MN1 is connected to the ground terminal GND, and the control electrode of the third transistor MN1 is connected to the first input signal IN; the first electrode of the fourth transistor MN2 is connected to the first electrode of the second transistor MN6, the second electrode of the fourth transistor MN2 is connected to the ground terminal GND, and the control electrode of the fourth transistor MN2 is connected to the second input signal INB.

[0027] It should be noted that the thickness of the gate oxide layer of the first transistor MN5 is greater than the thickness of the gate oxide layer of the third transistor MN1, or the thickness of the gate oxide layer of the second transistor MN6 is greater than the thickness of the gate oxide layer of the third transistor MN1; the thickness of the gate oxide layer of the first transistor MN5 is greater than the thickness of the gate oxide layer of the fourth transistor MN2, or the thickness of the gate oxide layer of the second transistor MN6 is greater than the thickness of the gate oxide layer of the fourth transistor MN2. This reduces the size and / or area of ​​the pull-down module 10.

[0028] That is, the third transistor MN1 and the fourth transistor MN2 are low-voltage devices with a withstand voltage range of the first power supply voltage VDDL. The use of low-voltage devices can reduce the size and area of ​​the pull-down module 10.

[0029] The channel type of the third transistor MN1 may be the same as the channel type of the fourth transistor MN2 , for example, both are N-channel field effect transistors or bipolar junction transistors.

[0030] Since the first transistor MN5 and the second transistor MN6 in the clamping module 30 can clamp the potential of the first electrode of the third transistor MN1 and the potential of the first electrode of the fourth transistor MN2 to a lower potential when they are turned on, the withstand voltage values ​​of the third transistor MN1 and the fourth transistor MN2 are reduced, so that the third transistor MN1 and the fourth transistor MN2 can both use low-voltage devices. Compared with high-voltage devices, low-voltage devices have lower threshold voltages, smaller gate lengths, and stronger driving capabilities. Therefore, low-voltage devices can be used in the input pair of transistors of the pull-down module 10, namely the third transistor MN1 and the fourth transistor MN2, so that stronger pull-down capabilities can be obtained with a smaller area, and the size and / or area of ​​the pull-down module 10 can be significantly reduced.

[0031] In some embodiments, such as Figure 1 and Figure 2 As shown, the level conversion circuit further includes a first inverter 40, an input end of the first inverter 40 is connected to the first input signal IN, an output end of the first inverter 40 outputs a second input signal INB, and a power supply end of the first inverter 40 is connected to the first power supply voltage VDDL.

[0032] It should be noted that since the third transistor MN1 and the fourth transistor MN2 can both be low-voltage devices, the threshold voltages of the third transistor MN1 and the fourth transistor MN2 are lower, which allows the present application to use a first power supply voltage VDDL with a lower logic level, further reducing power consumption.

[0033] The voltage swings of the first input signal IN and the second input signal INB are both the first power supply voltage VDDL. The bias voltage VB_LS is less than or equal to the sum of the first power supply voltage VDDL and the threshold voltage of the first transistor MN5; or the bias voltage VB_LS is less than or equal to the sum of the first power supply voltage VDDL and the threshold voltage of the second transistor MN6.

[0034] In some embodiments, such as Figure 1 and Figure 2 As shown, the output module 20 includes a fifth transistor MP1 and a sixth transistor MP2, the first electrode of the fifth transistor MP1 is connected to the second power supply voltage VDDH, the control electrode of the fifth transistor MP1 is connected to the second electrode of the second transistor MN6, and the second electrode of the fifth transistor MP1 is connected to the second electrode of the first transistor MN5; the first electrode of the sixth transistor MP2 is connected to the first electrode of the fifth transistor MP1, the control electrode of the sixth transistor MP2 is connected to the second electrode of the first transistor MN5, and the second electrode of the sixth transistor MP2 is connected to the second electrode of the second transistor MN6.

[0035] It should be noted that the second power supply voltage VDDH is greater than the first power supply voltage VDDL. The second power supply voltage VDDH can supply power to the high voltage domain, and the first power supply voltage VDDL can supply power to the low voltage domain.

[0036] The channel type of the fifth transistor MP1 may be the same as the channel type of the sixth transistor MP2 , for example, both are P-channel field effect transistors or bipolar junction transistors.

[0037] In some embodiments, such as Figure 2 As shown, the output module 20 also includes a second inverter 21, the input end of the second inverter 21 is connected to the second electrode of the fifth transistor MP1 or the second electrode of the sixth transistor MP2, the output end of the second inverter 21 is used to output the level conversion signal OUT, and the power supply end of the second inverter 21 is connected to the second power supply voltage VDDH.

[0038] It should be noted that the output module 20 can also output a corresponding signal from the second electrode of the fifth transistor MP1 or the second electrode of the sixth transistor MP2.

[0039] In some embodiments, such as Figure 2 As shown, the level conversion circuit also includes a pull-up module 50, which is connected to the pull-down module 10 and the clamping module 30, and is used to raise the potential at the connection between the pull-down module 10 and the clamping module 30 to the first power supply voltage VDDL according to at least one of the first input signal IN and the second input signal INB.

[0040] It should be noted that the pull-up module 50 can reduce the charging voltage swing of the second electrode of the fifth transistor MP1 and / or the second electrode of the sixth transistor MP2, shorten the charging time, and accelerate the potential flipping speed of the second electrode of the fifth transistor MP1 and / or the second electrode of the sixth transistor MP2, thereby reducing the delay of the level conversion.

[0041] In some embodiments, such as Figure 2 As shown, the pull-up module 50 includes a first pull-up unit 51 and a second pull-up unit 52. The first pull-up unit 51 is used to raise the potential of the first electrode of the third transistor MN1 to the first power supply voltage VDDL according to the second input signal INB; the second pull-up unit 52 is used to raise the potential of the first electrode of the fourth transistor MN2 to the first power supply voltage VDDL according to the first input signal IN.

[0042] It should be noted that the first pull-up unit 51 can accelerate the potential flipping speed of the second electrode of the fifth transistor MP1 through the first transistor MN5, thereby accelerating the potential flipping speed of the second electrode of the sixth transistor MP2, thereby reducing the delay of level conversion.

[0043] Similarly, the second pull-up unit 52 can accelerate the potential flipping speed of the second electrode of the sixth transistor MP2 through the second transistor MN6, thereby accelerating the potential flipping speed of the second electrode of the fifth transistor MP1, thereby reducing the delay of level conversion.

[0044] In some embodiments, such as Figure 2 As shown, the first pull-up unit 51 includes a seventh transistor MN3, a first electrode of the seventh transistor MN3 is connected to the first power supply voltage VDDL, a second electrode of the seventh transistor MN3 is connected to the first electrode of the third transistor MN1, and a control electrode of the seventh transistor MN3 is connected to the second input signal INB.

[0045] It should be noted that the seventh transistor MN3 can be an N-channel field effect transistor or a bipolar junction transistor. When the second input signal INB is at a high potential, the seventh transistor MN3 is turned on and can pull up the potential of the first electrode of the third transistor MN1 to the first power supply voltage VDDL.

[0046] In some embodiments, such as Figure 2 As shown, the second pull-up unit 52 includes an eighth transistor MN4, a first electrode of the eighth transistor MN4 is connected to the first power supply voltage VDDL, a second electrode of the eighth transistor MN4 is connected to the first electrode of the fourth transistor MN2, and a control electrode of the eighth transistor MN4 is connected to the first input signal IN.

[0047] It should be noted that the eighth transistor MN4 can be an N-channel field effect transistor or a bipolar junction transistor. When the first input signal IN is at a high potential, the eighth transistor MN4 is turned on and can pull up the potential of the first electrode of the fourth transistor MN2 to the first power supply voltage VDDL.

[0048] In order to solve the withstand voltage problem introduced by the use of low-voltage devices in the pull-down module 10, the bias voltage VB_LS generated by the peripheral circuit is used to uniformly bias the inserted clamp module 30, and the bias voltage VB_LS is adjusted to a suitable value to ensure that the first node Q3 and the second node Q4 have no withstand voltage problem. Since the specific voltage of the bias voltage VB_LS is closely related to the withstand voltage, the voltage range of the bias voltage VB_LS is analyzed as follows:

[0049] The first node Q3 and the second node Q4 are used as the connection points between the high voltage network and the low voltage network. To ensure the reliable withstand voltage of the low voltage side device, the voltage of the first node Q3 and the second node Q4 should not be higher than the first power supply voltage VDDL. At the same time, the first power supply voltage VDDL and the bias voltage VB_LS differ by the gate-source voltage difference (V GS-MN5 / 6 ), based on which the calculation formula 1-1 is established as follows:

[0050] V Q3 / 4 =VB_LS-V GS-MN5 / 6 <VDDL (1-1)

[0051] Among them, V Q3 / 4 represents the potential of the first node Q3 or the potential of the second node Q4. VB_LS represents the potential of the bias voltage VB_LS. VDDL represents the potential of the first power supply voltage VDDL.

[0052] After transformation, we can get formula 1-2 as follows:

[0053] VB_LS <VDDL+V GS-MN5 / 6 (1-2)

[0054] When the first transistor MN5 and the second transistor MN6 are turned on, the gate-source voltage difference of the first transistor MN5 or the second transistor MN6 is greater than their respective threshold voltages (V THN-H ). Through V THN-H Substitute V in formula 1-2 GS-MN5 / 6 , we can get the following calculation formula 1-3:

[0055] VB_LS <VDDL+V THN-H (1-3)

[0056] Therefore, VB_LS should be lower than VDDL and V THN-H The sum of the two values ​​can ensure that the low-voltage components in the pull-down module 10 have no withstand voltage problem. In order to minimize the delay, VB_LS should be set as high as possible. Therefore, under the premise of meeting the withstand voltage, VB_LS is set to VDDL+V THN-H .

[0057] Figure 3 and Figure 4 It shows the level inversion process of the third node Q1 and the fourth node Q2 when the rising edge of the first input signal IN comes.

[0058] exist Figure 3 and Figure 4 In the embodiment, no matter there is the pull-up module 50 or not, the level flipping process of the fourth node Q2 can be divided into two steps, namely step 1 and step 2.

[0059] Step 1: After the rising edge of the first input signal IN arrives, the voltage drop of the third node Q1 is V THP-H , but failed to turn on the sixth transistor MP2. THP-H is the threshold voltage of the fifth transistor MP1 or the threshold voltage of the sixth transistor MP2.

[0060] Step 2: The voltage of the third node Q1 continues to drop, so that the sixth transistor MP2 is turned on.

[0061] When the pull-up module 50 does not exist, as Figure 3 As shown: during step 1, the sixth transistor MP2 is turned off, and the voltage of the fourth node Q2 will maintain the previous zero level state; during step 2, the sixth transistor MP2 is turned on, and the second power supply voltage VDDH will charge the fourth node Q2 from 0 to the second power supply voltage VDDH through the turned-on sixth transistor MP2, so that during step 2, the charging voltage swing of the fourth node Q2 is the second power supply voltage VDDH.

[0062] When the pull-up module 50 exists, as Figure 4 As shown in step 1, the sixth transistor MP2 is turned off, but the first power supply voltage VDDL is charged to the fourth node Q2 to (VB_LS-V THN-H ); During step 2, the second power supply voltage VDDH will turn on the fourth node Q2 from (VB_LS-V THN-H ) is charged to the second power supply voltage VDDH, so during step 2, the charging voltage swing of the fourth node Q2 is (VDDH-VB_LS+V THN-H ).

[0063] Obviously, the presence of the pull-up module 50 reduces the charging voltage swing of the fourth node Q2 during step 2, thereby reducing the charging time and accelerating the level flipping of the fourth node Q2, which will further reduce the level flipping time of the third node Q1 through the fifth transistor MP1, thereby reducing the delay of the level conversion.

[0064] The specific working process of this application is as follows Figure 5 As shown below:

[0065] The voltage changes of the symmetrical nodes in the left and right branches of the level conversion circuit are complementary, so here only the rising edge of the first input signal IN is used as an example for explanation. After the rising edge of the first input signal IN arrives, the first node Q3 and the second node Q4 respond first, and the potential of the first node Q3 is pulled to the ground through the third transistor MN1, and the voltage of the third node Q1 begins to drop. At the same time, the first power supply voltage VDDL charges the second node Q4 and the fourth node Q2 to the first power supply voltage VDDL through the eighth transistor MN4 and the second transistor MN6.

[0066] Then, the voltage of the third node Q1 continues to drop, and after the sixth transistor MP2 starts to be turned on, the second power supply voltage VDDH starts to charge the fourth node Q2 through the sixth transistor MP2, and the voltage of the fourth node Q2 continues to rise.

[0067] Subsequently, in the cross-coupled positive feedback structure formed by the fifth transistor MP1 and the sixth transistor MP2, the voltage of the third node Q1 and the voltage of the fourth node Q2 are further amplified to the ground and the second power supply voltage VDDH respectively, and the level conversion signal OUT is the reverse output of the voltage of the third node Q1.

[0068] In some embodiments, the present application provides a memory comprising the above-mentioned level conversion circuit.

[0069] It can be understood that since the memory provided in the present application includes the above-mentioned level conversion circuit, it is also possible to connect the clamping module 30 between the pull-down module 10 and the output module 20, so that the clamping module 30 can reduce the withstand voltage of the pull-down module 10 according to the bias voltage VB_LS, thereby reducing the withstand voltage required by the pull-down module 10, which is conducive to the pull-down module 10 using low-voltage devices with lower withstand voltage values. Compared with the pull-down module 10 using high-voltage devices with higher withstand voltage values, this reduces the occupied area of ​​the pull-down module 10.

[0070] In some of the embodiments, the present application provides an electronic device, which includes a device body and the above-mentioned level conversion circuit arranged in the device body, or the electronic device includes the above-mentioned memory.

[0071] It can be understood that since the electronic device provided in the present application includes the above-mentioned level conversion circuit or memory, it is also possible to connect the clamping module 30 between the pull-down module 10 and the output module 20, so that the clamping module 30 can reduce the withstand voltage of the pull-down module 10 according to the bias voltage VB_LS, thereby reducing the withstand voltage required by the pull-down module 10, which is conducive to the pull-down module 10 using low-voltage devices with lower withstand voltage values. Compared with the pull-down module 10 using high-voltage devices with higher withstand voltage values, this reduces the occupied area of ​​the pull-down module 10.

[0072] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0073] The level conversion circuit, memory and electronic device provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A level conversion circuit, characterized in that: The level conversion circuit comprises a pull-down module (10), an output module (20), and a clamping module (30) connected between the pull-down module (10) and the output module (20); The clamping module (30) is used to reduce the withstand voltage value of the pull-down module (10) according to the bias voltage (VB_LS).

2. The level conversion circuit according to claim 1, characterized in that: The clamping module (30) comprises: a first transistor (MN5), wherein a first electrode of the first transistor (MN5) is connected to a first end of the pull-down module (10), a second electrode of the first transistor (MN5) is connected to a first end of the output module (20), and a control electrode of the first transistor (MN5) is connected to the bias voltage (VB_LS); A second transistor (MN6), wherein a first electrode of the second transistor (MN6) is connected to a second end of the pull-down module (10), a second electrode of the second transistor (MN6) is connected to a second end of the output module (20), and a control electrode of the second transistor (MN6) is connected to a control electrode of the first transistor (MN5).

3. The level conversion circuit according to claim 2, characterized in that: The pull-down module (10) comprises: a third transistor (MN1), wherein a first electrode of the third transistor (MN1) is connected to a first electrode of the first transistor (MN5), a second electrode of the third transistor (MN1) is connected to a ground terminal (GND), and a control electrode of the third transistor (MN1) is connected to a first input signal (IN); a fourth transistor (MN2), wherein a first electrode of the fourth transistor (MN2) is connected to a first electrode of the second transistor (MN6), a second electrode of the fourth transistor (MN2) is connected to the ground terminal (GND), and a control electrode of the fourth transistor (MN2) is connected to a second input signal (INB); wherein the thickness of the gate oxide layer of the first transistor (MN5) is greater than the thickness of the gate oxide layer of the third transistor (MN1), or the thickness of the gate oxide layer of the second transistor (MN6) is greater than the thickness of the gate oxide layer of the third transistor (MN1); The thickness of the gate oxide layer of the first transistor (MN5) is greater than the thickness of the gate oxide layer of the fourth transistor (MN2), or the thickness of the gate oxide layer of the second transistor (MN6) is greater than the thickness of the gate oxide layer of the fourth transistor (MN2).

4. The level conversion circuit according to claim 3, characterized in that: The level conversion circuit further comprises a first inverter (40), an input end of the first inverter (40) is connected to the first input signal (IN), an output end of the first inverter (40) outputs the second input signal (INB), and a power supply end of the first inverter (40) is connected to a first power supply voltage (VDDL); The bias voltage (VB_LS) is less than or equal to the sum of the first power supply voltage (VDDL) and the threshold voltage of the first transistor (MN5), or the bias voltage (VB_LS) is less than or equal to the sum of the first power supply voltage (VDDL) and the threshold voltage of the second transistor (MN6).

5. The level conversion circuit according to claim 4, characterized in that: The output module (20) comprises: a fifth transistor (MP1), wherein a first electrode of the fifth transistor (MP1) is connected to a second power supply voltage (VDDH), a control electrode of the fifth transistor (MP1) is connected to a second electrode of the second transistor (MN6), and a second electrode of the fifth transistor (MP1) is connected to a second electrode of the first transistor (MN5); a sixth transistor (MP2), wherein a first electrode of the sixth transistor (MP2) is connected to a first electrode of the fifth transistor (MP1), a control electrode of the sixth transistor (MP2) is connected to a second electrode of the first transistor (MN5), and a second electrode of the sixth transistor (MP2) is connected to a second electrode of the second transistor (MN6); The second power supply voltage (VDDH) is greater than the first power supply voltage (VDDL).

6. The level conversion circuit according to claim 5, characterized in that: The output module (20) further comprises a second inverter (21), an input end of the second inverter (21) being connected to the second electrode of the fifth transistor (MP1) or the second electrode of the sixth transistor (MP2), an output end of the second inverter (21) being used to output a level conversion signal (OUT), and a power supply end of the second inverter (21) being connected to the second power supply voltage (VDDH).

7. The level conversion circuit according to claim 3, characterized in that: The level conversion circuit further comprises a pull-up module (50), the pull-up module (50) being connected to the pull-down module (10) and the clamping module (30), and being used for raising the potential at the connection point between the pull-down module (10) and the clamping module (30) to a first power supply voltage (VDDL) according to at least one of a first input signal (IN) and a second input signal (INB).

8. The level conversion circuit according to claim 7, characterized in that: The pull-up module (50) comprises: A first pull-up unit (51), the first pull-up unit (51) being used for raising the potential of the first electrode of the third transistor (MN1) to the first power supply voltage (VDDL) according to the second input signal (INB); A second pull-up unit (52), the second pull-up unit (52) is used to raise the potential of the first electrode of the fourth transistor (MN2) to the first power supply voltage (VDDL) according to the first input signal (IN).

9. The level conversion circuit according to claim 8, characterized in that: The first pull-up unit (51) comprises a seventh transistor (MN3), a first electrode of the seventh transistor (MN3) is connected to the first power supply voltage (VDDL), a second electrode of the seventh transistor (MN3) is connected to the first electrode of the third transistor (MN1), and a control electrode of the seventh transistor (MN3) is connected to the second input signal (INB); The second pull-up unit (52) comprises an eighth transistor (MN4), a first electrode of the eighth transistor (MN4) is connected to the first power supply voltage (VDDL), a second electrode of the eighth transistor (MN4) is connected to the first electrode of the fourth transistor (MN2), and a control electrode of the eighth transistor (MN4) is connected to the first input signal (IN).

10. A memory, characterized in that: The memory comprises the level conversion circuit according to any one of claims 1 to 9.

11. An electronic device, characterized in that: The electronic device comprises a device body and a level conversion circuit as claimed in any one of claims 1 to 9 arranged in the device body, or the electronic device comprises a memory as claimed in claim 10.

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