Piezoelectric heterogeneous substrate, preparation method and semiconductor device

Abstract

The invention discloses a piezoelectric heterogeneous substrate, a preparation method and a semiconductor device, the piezoelectric heterogeneous substrate comprises a substrate layer, a dielectric layer, a patterned electrode layer and a piezoelectric film layer, the dielectric layer is located between the substrate layer and the piezoelectric film layer, the patterned electrode layer is located in the dielectric layer, and one side of the patterned electrode layer is exposed to the dielectric layer and is electrically connected with the piezoelectric film layer; the piezoelectric thin film layer is provided with a first surface and a second surface which are deviated from each other, the first surface is an original exposed surface of the piezoelectric heterogeneous substrate for forming the piezoelectric thin film layer, the first surface is positioned on one side, deviated from the substrate layer, of the piezoelectric thin film layer, and the second surface is formed by thinning one side, deviated from the original exposed surface, of the piezoelectric wafer substrate. The sacrificial protection structure is adopted to form the piezoelectric thin film layer, a high-temperature process is completed before the patterned electrode layer and the dielectric layer are formed, stress caused by thermal mismatch in the subsequent preparation process is reduced, and the morphology accuracy, reliability, stability and durability of the piezoelectric heterogeneous substrate are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a piezoelectric heterogeneous substrate, a preparation method and a semiconductor device. Background Art

[0002] With the development of wireless communication technology, 5G and 6G frequency bands have put forward higher requirements for RF front-end components. As the core component of RF front-end, RF filter needs to have higher frequency and larger bandwidth, which has a great impact on the sound velocity (v) and electromechanical coupling coefficient (k) of acoustic resonator. 2 ) puts forward higher requirements, requiring RF substrates with better performance. Surface acoustic wave (SAW) resonators and bulk acoustic wave (BAW) resonators are widely used in RF systems. Surface acoustic wave resonators based on lithium niobate or lithium tantalate piezoelectric heterogeneous substrates can achieve better acoustic energy confinement and temperature compensation, and bulk acoustic wave resonators based on aluminum nitride or scandium-doped aluminum nitride can achieve higher operating frequencies, but they are difficult to meet the frequency or bandwidth requirements in the 5G and 6G frequency bands.

[0003] By preparing a metal layer at the bottom of the piezoelectric film layer and preparing electrodes on the surface, a higher sound speed and a larger electromechanical coupling coefficient can be achieved by utilizing the acoustic mode excited by the longitudinal electric field. At present, the ion beam stripping method is generally used to prepare high-quality piezoelectric single crystal films (i.e., piezoelectric film layers) on the surface of the substrate layer. When the piezoelectric single crystal film is transferred by direct bonding of a piezoelectric wafer, the piezoelectric film layer needs to be annealed at a high temperature to restore the lattice damage caused by ion implantation. In the high-temperature process, there may be a large thermal mismatch between the metal layer distributed on the entire surface and the piezoelectric film layer. At the same time, the chemical properties of the metal layer may be affected. The material selection and temperature control requirements in the preparation process are relatively strict, and it is not conducive to the overall performance of the piezoelectric heterogeneous substrate. In addition, in the subsequent preparation process, the surface-distributed metal layer as the bottom electrode will increase the leakage of the body wave energy of the acoustic resonator and introduce strong noise. Summary of the invention

[0004] In view of the above problems in the prior art, the present application provides a piezoelectric heterogeneous substrate, a preparation method and a semiconductor device. The specific technical solution is as follows:

[0005] On the one hand, the present application provides a piezoelectric heterogeneous substrate, comprising a substrate layer, a dielectric layer, a patterned electrode layer and a piezoelectric film layer, wherein the dielectric layer is located between the substrate layer and the piezoelectric film layer, the patterned electrode layer is located in the dielectric layer, and one side of the patterned electrode layer is exposed to the dielectric layer and is electrically connected to the piezoelectric film layer;

[0006] The piezoelectric film layer has a first surface and a second surface facing away from each other, the first surface is the original exposed surface of the piezoelectric heterogeneous substrate used to form the piezoelectric film layer, the first surface is located on the side of the piezoelectric film layer facing away from the substrate layer, and the second surface is formed by thinning the side of the piezoelectric wafer substrate facing away from the original exposed surface.

[0007] Furthermore, the piezoelectric heterogeneous substrate further comprises an intermediate adhesion layer, wherein the intermediate adhesion layer is located between the patterned electrode layer and the dielectric layer, and / or

[0008] The intermediate adhesion layer is located between the patterned electrode layer and the piezoelectric film layer.

[0009] Furthermore, the intermediate adhesive layer satisfies at least one of the following characteristics:

[0010] The intermediate adhesive layer and the patterned electrode layer are arranged in a conformal and aligned manner;

[0011] The material of the intermediate adhesion layer includes at least one of titanium, tungsten, titanium tungsten, nickel, chromium and molybdenum;

[0012] The thickness of the intermediate adhesion layer is 1 nm to 15 nm.

[0013] Furthermore, the piezoelectric heterogeneous substrate has an air gap therein, and the air gap is located between the patterned electrode layer and the dielectric layer.

[0014] Furthermore, the piezoelectric heterogeneous substrate satisfies at least one of the following characteristics:

[0015] The material of the substrate layer includes at least one of silicon, silicon oxide, quartz, sapphire, silicon carbide, silicon nitride, gallium nitride and diamond;

[0016] The material of the dielectric layer includes at least one of silicon oxide, silicon nitride, polysilicon, amorphous silicon, aluminum oxide and aluminum nitride;

[0017] The thickness of the dielectric layer is 10nm to 2000nm;

[0018] The material of the patterned electrode layer includes at least one of gold, silver, copper, aluminum, nickel, platinum, titanium, tantalum, tungsten, chromium and molybdenum;

[0019] The thickness of the patterned electrode layer is 5nm to 150nm;

[0020] The material of the piezoelectric film layer includes at least one of single crystal lithium niobate, single crystal lithium tantalate, aluminum nitride, scandium-doped aluminum nitride and lead zirconate titanate;

[0021] The thickness of the piezoelectric film layer is 50nm-2200nm.

[0022] On the other hand, the present application also provides a method for preparing a piezoelectric heterogeneous substrate, comprising:

[0023] Bonding the original exposed surface of the piezoelectric wafer substrate to the surface of the sacrificial protection structure, and thinning the piezoelectric wafer substrate to form a piezoelectric film layer on the sacrificial protection structure to obtain a composite structure; the piezoelectric film layer has a first surface and a second surface that are opposite to each other, the first surface is the original exposed surface of the piezoelectric wafer substrate, the second surface is a surface formed by thinning the side of the piezoelectric wafer substrate away from the original exposed surface, and the second surface is exposed to the surface of the composite structure;

[0024] A patterned electrode layer and a dielectric layer are formed on the second surface; the patterned electrode layer is located in the dielectric layer, and one side of the patterned electrode layer is exposed to the dielectric layer and is electrically connected to the piezoelectric film layer;

[0025] The surface of one side of the composite structure having the dielectric layer is bonded to the surface of the substrate layer, and the sacrificial protection structure is removed to obtain a piezoelectric heterogeneous substrate; the piezoelectric heterogeneous substrate includes a substrate layer, a dielectric layer, a patterned electrode layer and a piezoelectric film layer, and the first surface of the piezoelectric film layer is located on the side of the piezoelectric film layer away from the substrate layer.

[0026] Furthermore, the sacrificial protection structure comprises a sacrificial layer and an oxide layer. In the composite structure, the oxide layer is located between the sacrificial layer and the piezoelectric film layer. The sacrificial protection structure is obtained by the following steps:

[0027] Thermal oxidation is performed on one side surface of the sacrificial layer to form the oxide layer on the sacrificial layer; the thickness of the oxide layer is 100 nm to 10000 nm.

[0028] Furthermore, before bonding the surface of the composite structure having the dielectric layer to the surface of the substrate layer and removing the sacrificial protection structure to obtain the piezoelectric heterogeneous substrate, the method further includes:

[0029] The composite structure is chamfered to form a chamfer at the edge of the composite structure; the depth of the chamfer is greater than or equal to the preset thickness of the sacrificial layer, and the width of the chamfer is 0.5 mm to 5 mm.

[0030] Furthermore, after forming the patterned electrode layer and the dielectric layer on the second surface, the method further comprises:

[0031] The composite structure is subjected to a first heat treatment; the temperature of the first heat treatment is greater than the forming temperature of the dielectric layer, and the time of the first heat treatment is greater than the forming time of the dielectric layer.

[0032] On the other hand, the present application also provides a semiconductor device, comprising a piezoelectric heterogeneous substrate and a surface electrode as described in any of the above items, wherein the surface electrode is located on the piezoelectric film layer and at least a portion of the surface electrode is aligned and arranged on the patterned electrode layer.

[0033] Based on the above technical solution, this application has the following beneficial effects:

[0034] 1. The present application adopts a dielectric layer to fill the gap between the patterned electrode layers. On the one hand, compared with the traditional surface electrode layer, the patterned electrode layer occupies a small area, which is beneficial to reducing the stress caused by thermal mismatch between the patterned electrode layer and the piezoelectric film layer, thereby effectively preventing the debonding of the piezoelectric film layer, which is beneficial to improving the quality of the piezoelectric heterogeneous substrate; on the other hand, it can further reduce the stress deformation of the piezoelectric film layer during the preparation process, which is beneficial to improving the morphological accuracy, reliability, stability and durability of the piezoelectric heterogeneous substrate; further, in the piezoelectric heterogeneous substrate, the first surface of the piezoelectric film layer is the original exposed surface of the piezoelectric heterogeneous substrate forming the piezoelectric film layer, and is exposed on the side away from the substrate layer. When applied to semiconductor devices, such as resonators, semiconductor devices based on the piezoelectric film layer can effectively improve the electromechanical coupling coefficient, spurious response and operating frequency under the same in-plane propagation angle, thereby meeting the performance requirements of various different semiconductor devices.

[0035] 2. The preparation method of the present application optimizes the process flow. The thinning treatment of the piezoelectric wafer substrate is carried out on a sacrificial protection structure, and high-temperature processes such as ion beam stripping and annealing have been completed before the formation of the patterned electrode layer and the dielectric layer. Therefore, during and after the subsequent formation of the patterned electrode layer and the dielectric layer, there is no need to perform high-temperature processes on the piezoelectric wafer substrate, thereby avoiding the thermal mismatch between the patterned electrode layer and the piezoelectric film layer, and also avoiding affecting the chemical properties of the patterned electrode layer material, which is beneficial to improving the structural accuracy, structural reliability and performance stability of the final piezoelectric heterogeneous substrate.

[0036] 3. The preparation method of the present application directly forms a patterned electrode layer with a preset shape, and fills the gaps between the patterned electrode layers with a dielectric layer, which can effectively reduce the stress caused by the thermal mismatch between the piezoelectric film layer and the patterned electrode layer during the subsequent high-temperature process to increase the bonding strength, and avoid unexpected reactions caused by the activity of the metal material of the patterned electrode layer during the high-temperature process, thereby reducing the adverse effects on the piezoelectric film layer.

[0037] 4. The present application adopts a silicon sacrificial layer with a mature process and an oxide layer formed by thermal oxidation of its surface, which are relatively convenient to prepare and remove. At the same time, the oxide layer can play a protective role and realize the reuse of the oxide layer. In addition, through the sacrificial protection structure, the initial piezoelectric wafer substrate is flipped and bonded twice in the process of becoming the final piezoelectric heterogeneous substrate. The original exposed surface of the piezoelectric wafer substrate finally forms the first surface of the piezoelectric thin film layer, which is exposed to the surface of the piezoelectric heterogeneous substrate, so that the crystal axis direction of the piezoelectric thin film layer is the same as the crystal axis direction of the piezoelectric wafer substrate, so as to be suitable for the preparation of semiconductor devices with specific functions. Under the condition of having the same in-plane propagation angle, the electromechanical coupling coefficient, stray response and operating frequency of the semiconductor device are effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments or prior art descriptions. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 A cross-sectional view of a piezoelectric heterogeneous substrate provided in an embodiment of the present application;

[0040] Figure 2 A cross-sectional view of another piezoelectric heterogeneous substrate provided in an embodiment of the present application;

[0041] Figure 3 A cross-sectional view of a piezoelectric heterogeneous substrate provided for some optional embodiments of the present application;

[0042] Figure 4 A cross-sectional view of a piezoelectric heterogeneous substrate provided for some other optional embodiments of the present application;

[0043] Figure 5 A cross-sectional view of a piezoelectric heterogeneous substrate provided for another optional embodiment of the present application;

[0044] Figure 6 A flow chart of a method for preparing a piezoelectric heterogeneous substrate provided in an embodiment of the present application;

[0045] Figure 7 A surface morphology image of a piezoelectric wafer substrate after patterning provided in an embodiment of the present application;

[0046] Figure 8 A flow chart of a method for forming a dielectric layer provided in an embodiment of the present application;

[0047] Fig. 9A flow chart of another method for preparing a piezoelectric heterogeneous substrate provided in an embodiment of the present application.

[0048] Wherein, the accompanying drawings are marked as follows:

[0049] 1-substrate layer, 2-dielectric layer, 21-step layer, 3-patterned electrode layer, 4-piezoelectric film layer, 41-first surface, 42-second surface, 400-piezoelectric wafer substrate, 401-original exposed surface, 5-air gap, 6-sacrificial protection structure, 61-sacrificial layer, 62-oxide layer. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments, and the structure in the drawings is only a technical solution of a specific embodiment of the present application. The structure of the present application may include fewer or more structural features and is not limited to the structure described in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0051] It should be noted that in the description of the present application, for the following defined terms, unless a different definition is given in the claims or elsewhere in this specification, these definitions should be applied. All numerical values, whether or not explicitly indicated, are defined herein as being modified by the term "about". The term "about" generally refers to a numerical range that a person of ordinary skill in the art would consider to be equivalent to the stated value to produce substantially the same properties, functions, results, etc. A numerical range indicated by a low value and a high value is defined to include all numerical values ​​included in the numerical range and all subranges included in the numerical range.

[0052] It should be noted that, in the description of the present application, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0053] It should be noted that, in the description of the present application, the meaning of the terms "on", "above", "above", and "above" should be interpreted in the broadest sense, meaning that the description containing these terms is interpreted as "the component can be set on another component in direct contact, or there can be an intermediate component or layer between the components". In addition, for the convenience of description, the present application may also use spatial relative terms such as "under", "below", "under", "on", "above", "above", "lower", "upper", etc. to describe the relationship between an element or component and another element or component shown in the drawings. In addition to the orientations described in the figures, the spatially relative terms are also intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90° or in other orientations), and the spatially relative descriptors used in the present application can be interpreted accordingly.

[0054] The term "layer" as used in this application refers to a portion of a material including an area having a certain thickness. A layer may extend over the entire underlying or superstructure, or may extend over a localized area of ​​the underlying or superstructure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically and / or along a tapered surface. A layer may include multiple layers. For example, a redistribution layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0055] In view of the technical problem in the prior art that the high-temperature process steps in the preparation process of the piezoelectric heterogeneous substrate easily cause thermal stress between the metal electrode and the piezoelectric film layer, resulting in poor structural stability and difficulty in mass production, the embodiments of the present application provide a piezoelectric heterogeneous substrate, a preparation method and a semiconductor device, such as Figure 1As shown, the piezoelectric heterogeneous substrate includes a substrate layer 1, a dielectric layer 2, a patterned electrode layer 3 and a piezoelectric film layer 4, the dielectric layer 2 is located between the substrate layer 1 and the piezoelectric film layer 4, the patterned electrode layer 3 is located in the dielectric layer 2, and one side of the patterned electrode layer 3 is exposed to the dielectric layer 2 and is electrically connected to the piezoelectric film layer 4; on the one hand, compared with the traditional surface electrode layer, the patterned electrode layer 3 occupies a small area, which is conducive to reducing the stress generated by thermal mismatch between the patterned electrode layer 3 and the piezoelectric film layer 4, thereby effectively preventing the piezoelectric film layer 4 from debonding, which is beneficial On the other hand, the dielectric layer 2 is filled in the gap of the patterned electrode layer 3, which can further reduce the stress deformation of the piezoelectric film layer 4 during the preparation process, which is beneficial to improving the morphological accuracy, reliability, stability and durability of the piezoelectric heterogeneous substrate; in addition, the piezoelectric heterogeneous substrate can reduce the stress generated by the large difference in thermal expansion coefficients between different layers on the structural accuracy, structural reliability and structural stability of the piezoelectric heterogeneous substrate during the preparation process, which is beneficial to simplify the preparation complexity of the piezoelectric heterogeneous substrate and improve the preparation yield.

[0056] Specifically, the piezoelectric film layer 4 has a first surface 41 and a second surface 42 which are opposite to each other. The first surface 41 is an original exposed surface 401 of a piezoelectric heterogeneous substrate 400 for forming the piezoelectric film layer 4. The first surface 41 is located on the side of the piezoelectric film layer 4 which is opposite to the substrate layer 1. In the piezoelectric heterogeneous substrate, the first surface 41 is exposed to the surface of the piezoelectric heterogeneous substrate. The second surface 42 is a surface formed by thinning the side of the piezoelectric wafer substrate 400 which is opposite to the original exposed surface 401. The second surface 42 is electrically connected to the patterned electrode layer 3. That is, During the preparation process, through a first flip bonding peeling and a second flip bonding, the crystal axis direction of the piezoelectric film layer 4 is made to be the same as the crystal axis direction of the piezoelectric wafer substrate 400; in this way, the first surface 41 of the piezoelectric film layer 4 is exposed to the side away from the substrate layer 1, and is applied to semiconductor devices, such as resonators. The semiconductor device based on the piezoelectric film layer 4 can effectively improve the electromechanical coupling coefficient, spurious response, operating frequency and other performances while having the same in-plane propagation angle, thereby meeting the performance requirements of various semiconductor devices.

[0057] Specifically, the material of the substrate layer 1 includes at least one of silicon, silicon oxide, quartz, sapphire, silicon carbide, silicon nitride, gallium nitride and diamond, which can effectively play a supporting role, improve the structural stability of the piezoelectric heterogeneous substrate, and is also beneficial to improving the electromechanical coupling coefficient of the piezoelectric heterogeneous substrate.

[0058] Specifically, the material of the dielectric layer 2 includes at least one of silicon oxide, silicon nitride, polycrystalline silicon, amorphous silicon, aluminum oxide and aluminum nitride, and has good insulation properties. The dielectric layer 2 is filled in the gap of the patterned electrode layer 3, which can effectively avoid debonding of the patterned electrode layer 3 and the piezoelectric film layer 4 due to thermal mismatch during the preparation process, thereby greatly improving the structural accuracy and structural reliability of the piezoelectric heterogeneous substrate.

[0059] Specifically, the thickness of the dielectric layer 2 is 10nm to 2000nm; it can be understood that the thickness of the dielectric layer 2 can be any point value between 10nm and 2000nm; illustratively, the thickness of the dielectric layer 2 can be 10nm, 20nm, 50nm, 100nm, 500nm, 1000nm, 1500nm, 1800nm, 2000nm, etc.; within this thickness range, the thickness of the dielectric layer 2 is greater than the thickness of the patterned electrode layer 3, and can effectively wrap the peripheral side of the patterned electrode layer 3 and the side close to the substrate layer 1, effectively preventing undesirable stress deformation between the patterned electrode layer 3 and the piezoelectric film layer 4, and greatly improving the structural accuracy and structural stability inside the piezoelectric heterogeneous substrate.

[0060] Specifically, the preset shape of the patterned electrode layer 3 includes at least one of a polygon and an interdigitated pattern; illustratively, Figure 2 As shown, the preset shape of the patterned electrode layer 3 can be a cross-finger pattern; as an example, the preset shape of the patterned electrode layer 3 can be a single polygon; as an example, the preset shape of the patterned electrode layer 3 can be a combination of a polygon and a cross-finger pattern; the preset shapes of the patterned electrode layer 3 are diverse and can meet the performance requirements of different semiconductor devices.

[0061] The material of the patterned electrode layer 3 includes at least one of gold, silver, copper, aluminum, nickel, platinum, titanium, tantalum, tungsten, chromium and molybdenum. In the semiconductor device prepared subsequently, together with the surface electrode on the surface of the piezoelectric film layer 4, the acoustic mode excited by the longitudinal electric field can be used to greatly improve the sound velocity and electromechanical coupling coefficient of the semiconductor device, so that the semiconductor device can meet the frequency or bandwidth requirements in the 5G and 6G frequency bands as much as possible, thereby improving the applicability of the piezoelectric heterogeneous substrate and the semiconductor device having the piezoelectric heterogeneous substrate.

[0062] Specifically, the thickness of the patterned electrode layer 3 is 5nm to 150nm; it can be understood that the thickness of the patterned electrode layer 3 can be any point value in the range of 5nm to 150nm; illustratively, the thickness of the patterned electrode layer 3 can be 5nm, 10nm, 25nm, 50nm, 100nm, 125nm, 150nm, etc.; within this thickness range, on the one hand, it can provide good electromechanical coupling performance, which is beneficial to the improvement of the sound velocity of the piezoelectric heterogeneous substrate; on the other hand, the thickness of the patterned electrode layer 3 is less than the thickness of the dielectric layer 2, and can be protected and restricted by the dielectric layer 2 during the preparation process, effectively preventing the patterned electrode layer 3 from being affected by the high temperature conditions during the preparation process, resulting in stress caused by debonding and a series of structural precision reduction and poor stability, and also preventing the prepared piezoelectric heterogeneous substrate and semiconductor device from being prone to cracking during use, thereby improving their structural reliability and structural durability.

[0063] Specifically, the material of the piezoelectric film layer 4 includes at least one of single-crystal lithium niobate, single-crystal lithium tantalate, aluminum nitride, scandium-doped aluminum nitride and lead zirconate titanate; the target thickness of the piezoelectric film layer 4 is 50nm~2200nm; it can be understood that the target thickness of the piezoelectric film layer 4 can be any point value between 50nm and 2200nm; illustratively, the target thickness of the piezoelectric film layer 4 can be 50nm, 100nm, 150nm, 500nm, 750nm, 1000nm, 1500nm, 2000nm, 2200nm, etc.; in this way, the piezoelectric film layer 4 can provide a good breakdown field strength, which is beneficial to improving the electrical properties of the piezoelectric heterogeneous substrate.

[0064] The substrate layer 1, dielectric layer 2, patterned electrode layer 3 and piezoelectric film layer 4 in the piezoelectric heterogeneous substrate cooperate with each other, which can effectively improve the operating frequency, sound velocity, electromechanical coupling coefficient and temperature stability of the piezoelectric heterogeneous substrate and the semiconductor device having the piezoelectric heterogeneous substrate, so that the piezoelectric heterogeneous substrate and the semiconductor device can meet the frequency and bandwidth requirements in the 5G and 6G frequency bands.

[0065] Specifically, the piezoelectric heterogeneous substrate also includes an intermediate adhesion layer (not shown). In some exemplary embodiments, the intermediate adhesion layer is located between the patterned electrode layer 3 and the dielectric layer 2; in other exemplary embodiments, the intermediate adhesion layer is located between the patterned electrode layer 3 and the piezoelectric film layer 4; in other exemplary embodiments, the piezoelectric heterogeneous substrate includes multiple intermediate adhesion layers, wherein there is at least one intermediate adhesion layer located between the patterned electrode layer 3 and the dielectric layer 2, and there is at least one intermediate adhesion layer located between the patterned electrode layer 3 and the piezoelectric film layer 4; the intermediate adhesion layer is used to increase the adhesion between the patterned electrode layer 3 and the dielectric layer 2 and / or between the dielectric layer 2 and the piezoelectric film layer 4, to prevent the dielectric layer 2 and the piezoelectric film layer 4 from falling off, which is beneficial to improving the structural reliability and structural stability of the piezoelectric heterogeneous substrate.

[0066] Specifically, in some preferred embodiments, the intermediate adhesion layer is contoured and aligned with the patterned electrode layer 3, and the intermediate adhesion layer has good adhesion, which can greatly improve the adhesion reliability between the patterned electrode layer 3 and the adjacent layer structure; in addition, the material of the intermediate adhesion layer is metal, and the same preparation method as the patterned electrode layer 3 can be adopted during the preparation process, which simplifies the preparation difficulty and improves the alignment accuracy between the intermediate adhesion layer and the patterned electrode layer 3, which is further beneficial to improving the overall structural stability and durability of the piezoelectric heterogeneous substrate.

[0067] Specifically, the material of the intermediate adhesion layer includes at least one of titanium, tungsten, titanium tungsten, nickel, chromium and molybdenum. Compared with the adhesion between the patterned electrode layer 3 and the piezoelectric film layer 4, the adhesion between the intermediate adhesion layer and the patterned electrode layer 3, between the intermediate adhesion layer and the dielectric layer 2, and between the intermediate adhesion layer and the piezoelectric film layer 4 are better, which can effectively improve the adhesion reliability of the piezoelectric film layer 4, the dielectric layer 2 and the patterned electrode layer 3, and is beneficial to improving the overall structural accuracy, structural reliability and structural stability of the piezoelectric heterogeneous substrate.

[0068] Specifically, the thickness of the intermediate adhesion layer is 1nm to 15nm; it can be understood that the thickness of the intermediate adhesion layer can be any point value between 1nm and 15nm; illustratively, the thickness of the intermediate adhesion layer can be 1nm, 3nm, 5nm, 6nm, 8nm, 10nm, 12nm, 13nm, 15nm, etc.; on the one hand, it can effectively improve the adhesion inside the piezoelectric heterogeneous substrate and improve the overall structural stability of the piezoelectric heterogeneous substrate, and on the other hand, it can avoid adverse effects on the performance optimization of the piezoelectric heterogeneous substrate.

[0069] Specifically, Figure 3 and Figure 4As shown, the piezoelectric heterogeneous substrate has an air gap 5, which is located between the patterned electrode layer 3 and the dielectric layer 2. The air gap 5 has an extremely high acoustic impedance and can confine the acoustic wave energy in the piezoelectric film layer 4, so as to facilitate the preparation of various types of acoustic wave resonators, such as thin film bulk acoustic resonator (FBAR) and laser diode bar (YBAR) devices.

[0070] In some exemplary embodiments, the patterned electrode layer 3 has a preset shape, wherein an air gap 5 exists in at least a portion of the region between the patterned electrode layer 3 and the dielectric layer 2, so that the patterned electrode layer 3 on the portion of the region is suspended relative to the substrate layer 1, that is, at least a portion of the patterned electrode layer 3 is suspended above the substrate layer 1, and an air gap 5 exists between the portion of the patterned electrode layer 3 and the substrate layer 1 at the bottom and the dielectric layer 2 on the peripheral side; illustratively, as Figure 3 and Figure 4 As shown, in the entire piezoelectric heterogeneous substrate, there is an air gap 5 between the patterned electrode layer 3 and the dielectric layer 2; illustratively, there is an air gap 5 in a partial area between the patterned electrode layer 3 and the dielectric layer 2, as shown in FIG. Figure 1-4 The structures shown can coexist in the same piezoelectric heterogeneous substrate, but are located in different regions of the piezoelectric heterogeneous substrate. In this way, the piezoelectric heterogeneous substrate is more flexible and diverse, and can meet the performance requirements of a variety of different semiconductor devices, thereby expanding the scope of application of the piezoelectric heterogeneous substrate.

[0071] In addition, in some other exemplary embodiments, Figure 5 As shown, a suspended groove may be opened in the substrate layer 1, and the suspended groove is located below the patterned electrode layer 3 to form a suspended structure to meet the performance requirements of specific semiconductor devices and further expand the application scope of the piezoelectric heterogeneous substrate.

[0072] On the other hand, Figure 6 As shown, the embodiment of the present application also provides a method for preparing a piezoelectric heterogeneous substrate, comprising:

[0073] S1, bonding the original exposed surface of the piezoelectric wafer substrate to the surface of the sacrificial protection structure, and thinning the piezoelectric wafer substrate to form a piezoelectric film layer on the sacrificial protection structure to obtain a composite structure; the piezoelectric film layer has a first surface and a second surface that are opposite to each other, the first surface is the original exposed surface of the piezoelectric wafer substrate, the second surface is a surface formed by thinning the side of the piezoelectric wafer substrate away from the original exposed surface, and the second surface is exposed to the surface of the composite structure;

[0074] S2, forming a patterned electrode layer and a dielectric layer on the second surface; the patterned electrode layer is located in the dielectric layer, and one side of the patterned electrode layer is exposed to the dielectric layer and is electrically connected to the piezoelectric film layer;

[0075] S3, bonding the surface of one side of the composite structure having the dielectric layer to the surface of the substrate layer, and removing the sacrificial protection structure to obtain a piezoelectric heterogeneous substrate; the piezoelectric heterogeneous substrate includes a substrate layer, a dielectric layer, a patterned electrode layer and a piezoelectric film layer, and the first surface of the piezoelectric film layer is located on the side of the piezoelectric film layer away from the substrate layer.

[0076] First, in step S1, a sacrificial protection structure 6 is used to pre-bond the original exposed surface 401 of the piezoelectric wafer substrate 400 to the surface of the sacrificial protection structure 6 to achieve the first flip bonding of the piezoelectric wafer substrate 400. Afterwards, the piezoelectric wafer substrate 400 is thinned on the sacrificial protection structure 6. The thinning process may be performed by at least one of ion beam stripping or wafer grinding to form a piezoelectric film layer 4. Exemplarily, the piezoelectric film layer 4 is formed by an ion beam stripping process, and then ions are implanted into the bonded piezoelectric wafer substrate 400 to form a damaged layer inside the piezoelectric wafer substrate 400. Afterwards, the piezoelectric wafer substrate 400 on the sacrificial protection structure 6 is heat-treated to strip off the portion of the piezoelectric wafer substrate 400 away from the sacrificial protection structure 6 along the damaged layer, and the remaining damaged layer is post-annealed and flattened to form a piezoelectric film layer 4 on the sacrificial protection structure 6.

[0077] In this way, a high-quality piezoelectric film layer 4 is first formed on the sacrificial protection structure 6, and steps involving high temperature conditions such as heat treatment and high-temperature post-annealing are all performed on the sacrificial protection structure 6. Then, the patterned electrode layer 3 and the dielectric layer 2 are formed in the S2 step, so that in the subsequent S2-S3 steps, there is no need to perform high-temperature annealing and other processes on the piezoelectric wafer substrate 400. Compared with the situation in which the metal layer and the dielectric layer are formed first in the traditional process, the thermal mismatch between the patterned electrode layer 3 and the piezoelectric film layer 4 in the subsequent steps can be effectively avoided, and the high temperature can be avoided. The influence of the chemical properties of the patterned electrode layer 3 is also avoided, and the reaction caused by the influence of the metal activity of the patterned electrode layer 3 on the piezoelectric film layer 4 is further avoided.

[0078] Specifically, in some exemplary embodiments, the sacrificial protection structure 6 includes a sacrificial layer 61 and an oxide layer 62. In the composite structure, the oxide layer 62 is located between the sacrificial layer 61 and the piezoelectric film layer 4. The sacrificial protection structure is obtained by the following steps:

[0079] Thermal oxidation is performed on one side surface of the sacrificial layer to form the oxide layer on the sacrificial layer; the thickness of the oxide layer is 100 nm to 10000 nm.

[0080] Among them, the material of the sacrificial layer 61 includes silicon, and semiconductor material silicon with a more complete process system is used as the sacrificial layer 61. A high-temperature process is pre-performed on the sacrificial protection structure 6 with the sacrificial layer 61 to restore the crystal quality of the piezoelectric film layer 4. Then the piezoelectric film layer 4 with restored crystal quality is transferred to the substrate layer 1 through composite structure bonding, which effectively avoids the debonding and other situations that may be caused by the stress generated by thermal mismatch, which is beneficial to improving the structural accuracy and performance of the piezoelectric heterogeneous substrate and simplifying the preparation method; accordingly, the material of the oxide layer 62 is silicon oxide, which has good inertness. The piezoelectric film layer 4 is formed on the oxide layer 62, which can protect the piezoelectric film layer 4 in subsequent preparation steps, thereby improving the preparation yield, accuracy and performance of the piezoelectric heterogeneous substrate; in addition, for silicon-based substrates, the overall thickness of the wafer mostly has an error of several microns to tens of microns. The oxide layer 62 can always protect the piezoelectric film layer 4 during batch processing, and also realizes the reuse of the oxide layer, thereby improving the preparation economy.

[0081] It can be understood that the thickness of the oxide layer 62 can be any value between 100nm and 10000nm; illustratively, the thickness of the oxide layer can be 100nm, 200nm, 500nm, 1000nm, 2500nm, 5000nm, 10000nm, etc.; it can effectively protect the piezoelectric film layer 4 from being damaged during the subsequent removal of the sacrificial layer 61, thereby improving the structural integrity and performance of the piezoelectric film layer 4.

[0082] Specifically, in step S1, the preset thickness of the piezoelectric film layer 4 is 50nm~2000nm, and the thickness difference between the preset thickness and the target thickness of the piezoelectric film layer 4 is 0nm~200nm, so that the target thickness of the final piezoelectric film layer is in the range of 50nm~2200nm; it can be understood that the preset thickness of the piezoelectric film layer 4 can be any point value between 50nm~2000nm, and the thickness difference between the preset thickness and the target thickness of the piezoelectric film layer 4 can be any point value between 0nm~200nm; exemplarily, the preset thickness of the piezoelectric film layer 4 can be 50nm, 100nm, 500nm, 1000nm, 1500nm, 1750nm, 2000nm, etc.; the thickness difference between the preset thickness and the target thickness of the piezoelectric film layer 4 can be 0nm, 10nm, 50nm, 100nm, 150nm, 180nm, 200nm, etc.

[0083] In the subsequent process of removing the oxide layer 62, the piezoelectric film layer 4 is prone to certain corrosion, or the target thickness of the piezoelectric film layer 4 fluctuates. By setting a certain thickness difference in step S1, the surface area of ​​the piezoelectric film layer 4 can be processed after completing the preparation of steps S1-S3, so as to achieve precise control of the final thickness of the piezoelectric film layer 4 with high fault tolerance.

[0084] Thus, after step S1, the piezoelectric wafer substrate 400 is flipped and bonded once, so that the first surface 41 of the piezoelectric film layer 4 (ie, the original exposed surface 401 of the piezoelectric wafer substrate 400) is bonded to the sacrificial protection structure 6, and the second surface 42 of the piezoelectric film layer 4 is exposed.

[0085] Then, if Figure 7 As shown, in step S2, the patterned electrode layer 3 is formed on the second surface 42. This step first forms a metal layer on the entire surface of the second surface 42, and then patterns the metal layer to obtain the patterned electrode layer 3. Then, the dielectric layer 2 is formed on the second surface 42 having the patterned electrode layer 3. In this way, the high-temperature process of the piezoelectric film layer 4 is completed before forming the patterned electrode layer 3 and the dielectric layer 2, thereby avoiding the adverse effects of the stress caused by thermal mismatch on the structural accuracy and structural stability of the piezoelectric heterogeneous substrate; it also greatly reduces the complexity of the entire preparation method, simplifies the preparation method, and is also conducive to improving the overall preparation accuracy and preparation yield.

[0086] In step S2, the dielectric layer 2 is formed after the patterned electrode layer 3 is formed. The dielectric layer 2 fills the gap in the patterned electrode layer 3. Together with the patterned electrode layer 3, it can further restrict the patterned electrode layer 3 and the piezoelectric film layer 4, effectively reducing the stress that may be caused by other subsequent high-temperature treatment processes. That is, the preparation method can further reduce the stress caused by thermal mismatch between the patterned electrode layer 3 and the piezoelectric film layer 4, thereby reducing the adverse effects of stress on the overall structure, greatly improving the structural accuracy, structural reliability and structural stability of the prepared piezoelectric heterogeneous substrate and the semiconductor device having the piezoelectric heterogeneous substrate; in addition, compared with the metal layer distributed on the entire surface, the body wave energy of the acoustic resonator will be increased. In the case of leakage and introduction of strong noise, when the piezoelectric heterogeneous substrate prepared by the preparation method is applied to semiconductor devices (such as acoustic wave resonators), the patterned electrode layer 3 and the dielectric layer 2 can also reduce the leakage of body wave energy and reduce noise, thereby further improving the acoustic energy confinement capability of the piezoelectric heterogeneous substrate; and, directly forming the patterned electrode layer 3 in step S2 can also improve the convenience of preparing various types of semiconductor devices. For example, in some embodiments, it is necessary to release part of the dielectric layer 2 under the patterned electrode layer 3 to prepare a body wave device. In this case, compared with the surface metal layer distributed on the entire surface, the release convenience of the dielectric layer 2 under the patterned electrode layer 3 is better, and the preparation accuracy of forming the air gap 5 is higher.

[0087] The dielectric layer 2 can be formed on the second surface 42 of the piezoelectric film layer 4 having the patterned electrode layer 3 by physical vapor deposition or chemical vapor deposition. The formation temperature of the dielectric layer 2 is less than or equal to a preset temperature, which is 400°C to 750°C. It can be understood that the preset temperature can be any point value between 400°C and 750°C. Exemplarily, the preset temperature can be 400°C, 450°C, 500°C, 550°C, 600°C, 650°C, 700°C, 750°C, etc. In this way, the temperature is relatively low, which can reduce thermal stress. It can also effectively deposit the dielectric layer 2, improve the molding accuracy of the dielectric layer 2, effectively cover the patterned electrode layer 3 and fill the gap in the patterned electrode layer 3, improve the filling sufficiency, and thus help to reduce the adverse effects of stress generated in the subsequent heat treatment process on the overall structure of the piezoelectric heterogeneous substrate. In some preferred embodiments, the preset temperature can be selected as 600°C, that is, the formation temperature of the dielectric layer 2 is less than or equal to 600°C.

[0088] Specifically, after forming the patterned electrode layer and the dielectric layer on the second surface, that is, between step S2 and step S3, the method further includes:

[0089] The composite structure is subjected to a first heat treatment; the temperature of the first heat treatment is greater than the forming temperature of the dielectric layer, and the time of the first heat treatment is greater than the forming time of the dielectric layer.

[0090] The first heat treatment is used to remove air at the interface between the dielectric layer 2 and the patterned electrode layer 3 to prevent the formation of bonding bubbles, thereby improving the filling density between the dielectric layer 2 and the patterned electrode layer 3, which is beneficial to improving the bonding accuracy and bonding reliability, and further beneficial to improving the overall preparation accuracy and preparation yield.

[0091] In some exemplary embodiments, before and after the first heat treatment, the heating and cooling rates of the first heat treatment are 1°C / min to 5°C / min; it can be understood that the heating and cooling rates of the first heat treatment can be any point value in the range of 1°C / min to 5°C / min; exemplarily, the heating and cooling rates of the first heat treatment can be 1°C / min, 1.5°C / min, 2°C / min, 3°C / min, 3.5°C / min, 4°C / min, 5°C / min, etc.; the heating and cooling rates are relatively fast, and the first heat treatment is to prepare the dielectric layer 2 on the piezoelectric film layer 4 of the sacrificial layer 61. At this time, the thickness of the piezoelectric film layer 4 has been thinned to reach the micron level to the submicron level, and the piezoelectric film layer 4 is not easily cracked by the sudden change in temperature, so the overall preparation efficiency can be improved with a relatively high heating and cooling rate, and it is not easy to have an adverse effect on the performance of the piezoelectric heterogeneous substrate.

[0092] Among them, Figure 8 As shown, in the process of forming the dielectric layer 2 in step S2, a step layer 21 is formed on the area corresponding to the patterned electrode layer 3, and the step layer 21 covers the patterned electrode layer 3, so that the patterned electrode layer 3 is located as a whole inside the dielectric layer 2. Afterwards, the dielectric layer 2 with the step layer 21 is planarized, and the step layer 21 is removed so that the surface reaches a preset flatness to obtain the dielectric layer 2.

[0093] The preset flatness RMS (root mean square roughness) is less than the preset roughness, and the preset roughness is 0.5nm~2nm; it can be understood that the preset roughness can be any point value between 0.5nm and 2nm; illustratively, the preset roughness can be 0.5nm, 0.8nm, 1nm, 1.2nm, 1.5nm, 1.8nm, 2nm, etc.; the high flatness of the surface of the dielectric layer 2 is beneficial to improve the subsequent bonding accuracy and bonding reliability with the substrate layer 1, and improve the structural accuracy, structural reliability and structural stability of the piezoelectric heterogeneous substrate finally obtained; in some preferred embodiments, the preset roughness is 1nm, that is, the preset flatness of the surface of the dielectric layer 2 is less than 1nm.

[0094] Specifically, in some exemplary embodiments, when the thickness of the step layer 21 is relatively thick, for example, when the thickness of the step layer 21 is greater than or equal to 5 nm, before performing planarization to remove the step layer 21, the step layer 21 can be pre-etched to reduce the thickness of the step layer 21 to less than 5 nm, and then the step layer 2 is planarized. This is beneficial to reduce the performance requirements for the polishing equipment, and the polishing removal amount is also less, which is beneficial to improve the preparation accuracy and preparation yield.

[0095] Specifically, in some exemplary embodiments, before bonding the surface of the composite structure having the dielectric layer to the surface of the substrate layer and removing the sacrificial protection structure to obtain the piezoelectric heterogeneous substrate, that is, between step S2 and step S3, the method further includes:

[0096] The composite structure is chamfered to form a chamfer at the edge of the composite structure; the depth of the chamfer is greater than or equal to the preset thickness of the sacrificial layer, and the width of the chamfer is 0.5 mm to 5 mm.

[0097] The chamfering treatment is used to remove defects at the edge of the composite structure, improve the surface uniformity and flatness of the composite structure, and improve the surface quality of the composite structure and its dielectric layer 2, which is beneficial to improving the bonding reliability between the dielectric layer 2 and the surface of the substrate layer 1 in the subsequent steps and the surface quality of the final piezoelectric heterogeneous substrate; it should be noted that in the subsequent process of removing the sacrificial layer 61, the sacrificial layer 61 will be thinned first and then removed after reaching a preset thickness. The original thickness of the sacrificial layer 61 in the initial state before thinning is greater than the preset thickness, that is, the preset thickness of the sacrificial layer 61 is the thickness reached after the initial thinning; for example, the original thickness of the sacrificial layer 61 is 500μm, and the preset thickness reached after the initial thinning is 50μm, then the depth of the chamfer is greater than 50μm, so as to prevent the edge from breaking and separating during the subsequent grinding process.

[0098] It can be understood that the width of the chamfer can be any value between 0.5mm and 5mm; illustratively, the width of the chamfer can be 0.5mm, 1mm, 1.5mm, 2.5mm, 3.5mm, 5mm, etc.; in this way, the surface flatness and uniformity are good, and the surface of one side of the dielectric layer 2 used for bonding has a higher surface quality.

[0099] Next, in step S3, the composite structure is flipped over so that one side surface of the dielectric layer 2 of the composite structure is bonded to the surface of the substrate layer 1, and then the sacrificial protection structure 6 is removed so that the first surface 41 of the piezoelectric film layer 4 is exposed on the surface of the piezoelectric heterogeneous substrate; in this way, through the two flipping and bonding steps in steps S1 and S3, the crystal axis direction of the original piezoelectric wafer substrate 400 can still maintain the same direction, and the original exposed surface 401 of the piezoelectric wafer substrate 400 and the first surface 42 of the piezoelectric film layer 4 are in the same direction, that is, the crystal axis direction of the finally formed piezoelectric film layer 4 is consistent with that of the original piezoelectric wafer substrate The crystal axis directions of 400 are the same, which makes it easy to select a piezoelectric wafer substrate 400 with a suitable crystal axis for preparation. For example, a +X-cut LN film is selected as the piezoelectric film layer 4, and a +X-cut LN substrate can be used as the piezoelectric wafer substrate 400 for preparation; more importantly, the positive and negative directions of the crystal axis directions of the piezoelectric film layer 4 can be suitable for the preparation of subsequent semiconductor devices. On the semiconductor device made based on the piezoelectric film layer 4, while having the same in-plane propagation angle, the electromechanical coupling coefficient, spurious response and operating frequency of semiconductor devices such as resonators can be significantly improved to meet the frequency or bandwidth requirements in the 5G and 6G frequency bands.

[0100] Next, in step S3, after bonding one side surface of the composite structure having the dielectric layer to the surface of the substrate layer to form a bonding structure, and before removing the sacrificial protection structure 6, the bonding structure is subjected to a second heat treatment to increase the bonding strength between the dielectric layer 2 and the substrate layer 1; wherein, during the second heat treatment, the temperature of the second heat treatment is 500°C to 450°C, the time is 2h to 24h, and the atmosphere environment includes at least one of nitrogen, oxygen, inert gas and vacuum environment; the heating and cooling rates before and after the second heat treatment are 0.5°C / min to 2.5°C / min, and the heating and cooling rates before and after the second heat treatment are less than or equal to the heating and cooling rates before and after the first heat treatment, so that the heating and cooling rates before and after the second heat treatment are relatively small, thereby avoiding the difference in thermal expansion coefficients between the sacrificial protection structure 6 and the substrate layer 1 from having an adverse effect on the structure of the piezoelectric heterogeneous substrate when the temperature changes sharply.

[0101] It can be understood that the temperature of the second heat treatment can be any value between 50°C and 450°C, the time can be any value between 2h and 24h, and the heating and cooling speed before and after the second heat treatment can be any value between 0.5°C / min and 2.5°C / min; illustratively, the temperature of the second heat treatment can be 50°C, 100°C, 150°C, 200°C, 250°C, 300°C, 400°C, 450°C, etc.; the time can be 2h, 4h, 6h, 10h, 15h, 20h, 24h, etc.; the heating and cooling rates before and after the second heat treatment can be 0.5℃ / min, 1℃ / min, 1.5℃ / min, 1.8℃ / min, 2℃ / min, 2.2℃ / min, 2.5℃ / min, etc.; in this way, the bonding strength between the dielectric layer 2 and the substrate layer 1 can be effectively improved, and it is also beneficial to improve the bonding strength between adjacent layers inside the piezoelectric heterogeneous substrate, improve the overall structural strength of the piezoelectric heterogeneous substrate, prevent debonding, and greatly improve stability and durability.

[0102] Next, in step S3, the sacrificial protection structure 6 in the bonding structure is removed. In some exemplary embodiments, the sacrificial layer 61 can be initially thinned by grinding so that the thickness of the sacrificial layer 61 is thinned to a preset thickness, which is 15 μm to 85 μm. It can be understood that the preset thickness can be any point value between 15 μm and 85 μm. Exemplarily, the preset thickness can be 15 μm, 25 μm, 30 μm, 50 μm, 60 μm, 75 μm, 85 μm, etc. In this way, the sacrificial layer 61 is thinner after thinning, which can facilitate the subsequent removal of the sacrificial layer 61 by etching, thereby improving the efficiency and accuracy of the subsequent etching removal of the sacrificial layer 61.

[0103] Next, the sacrificial layer 61 thinned to a preset thickness is etched to remove the remaining sacrificial layer 61, wherein, when the preset thickness is 15μm to 85μm, the remaining sacrificial layer 61 is removed at 30°C to 60°C by at least one of a potassium hydroxide solution or a tetramethylammonium hydroxide solution; in addition, when the preset thickness is 15μm to 50μm, the remaining sacrificial layer 61 is removed by reactive ion etching (RIE) or inductively coupled plasma etching (ICP); at the same time, in the process of removing the sacrificial layer 61, the oxide layer 62 is also corroded to a certain extent, but in this process, the removal thickness of the oxide layer 62 is less than or equal to the thickness of the oxide layer 62, so that the oxide layer 62 effectively protects the piezoelectric film layer 4 and maintains the accuracy of the morphology of the piezoelectric film layer 4.

[0104] Next, at least one of a hydrofluoric acid solution or a buffered oxide etching solution is used to remove the oxide layer 62 at 20° C. to 30° C. to obtain a piezoelectric heterogeneous substrate.

[0105] Specifically, in some exemplary embodiments, the piezoelectric heterogeneous substrate further includes an air gap 5; correspondingly, Fig. 9 As shown, after step S3, the method further includes:

[0106] The piezoelectric heterogeneous substrate is etched to partially remove the dielectric layer between the patterned electrode layer and the substrate layer below the piezoelectric film layer to form the air gap.

[0107] In this step, the piezoelectric film layer 4 covers the surface of the entire piezoelectric heterogeneous substrate. The target etching area can be defined on the piezoelectric film layer 4, and the target etching area is etched to form an etching window through the part of the piezoelectric film layer 4 that penetrates the target etching area. Afterwards, the dielectric layer 2 below is removed through the etching window by an etching method such as gas etching. The preparation is simple and quick, and the molding accuracy is good.

[0108] On the other hand, the present application also provides a semiconductor device, comprising the piezoelectric heterogeneous substrate and surface electrode as described above, wherein the surface electrode is located on the piezoelectric film layer 4 and at least part of the surface electrode is arranged on the patterned electrode layer 3 to utilize the acoustic mode excited by the longitudinal electric field to improve the sound velocity and electromechanical coupling coefficient of the semiconductor device; in some exemplary embodiments, the semiconductor device includes at least one of a surface acoustic wave resonator and a bulk acoustic wave resonator.

[0109] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0110] The above description has fully disclosed the specific implementation methods of the present application. It should be pointed out that any changes made by technicians familiar with the field to the specific implementation methods of the present application do not deviate from the scope of the claims of the present application. Accordingly, the scope of the claims of the present application is not limited to the above specific implementation methods.

Claims

1. A piezoelectric heterogeneous substrate, characterized in that: The device comprises a substrate layer, a dielectric layer, a patterned electrode layer and a piezoelectric film layer, wherein the dielectric layer is located between the substrate layer and the piezoelectric film layer, the patterned electrode layer is located in the dielectric layer, and one side of the patterned electrode layer is exposed to the dielectric layer and is electrically connected to the piezoelectric film layer; The piezoelectric film layer has a first surface and a second surface facing away from each other, the first surface is the original exposed surface of the piezoelectric heterogeneous substrate used to form the piezoelectric film layer, the first surface is located on the side of the piezoelectric film layer facing away from the substrate layer, and the second surface is formed by thinning the side of the piezoelectric wafer substrate facing away from the original exposed surface.

2. The piezoelectric heterogeneous substrate according to claim 1, characterized in that: The piezoelectric heterogeneous substrate further comprises an intermediate adhesion layer, wherein the intermediate adhesion layer is located between the patterned electrode layer and the dielectric layer, and / or The intermediate adhesion layer is located between the patterned electrode layer and the piezoelectric film layer.

3. The piezoelectric heterogeneous substrate according to claim 2, characterized in that: The intermediate adhesive layer satisfies at least one of the following characteristics: The intermediate adhesive layer and the patterned electrode layer are arranged in a conformal and aligned manner; The material of the intermediate adhesion layer includes at least one of titanium, tungsten, titanium tungsten, nickel, chromium and molybdenum; The thickness of the intermediate adhesion layer is 1 nm to 15 nm.

4. The piezoelectric heterogeneous substrate according to any one of claims 1 to 3, characterized in that: The piezoelectric heterogeneous substrate has an air gap therein, and the air gap is located between the patterned electrode layer and the dielectric layer.

5. The piezoelectric heterogeneous substrate according to any one of claims 1 to 3, characterized in that: The piezoelectric heterogeneous substrate satisfies at least one of the following characteristics: The material of the substrate layer includes at least one of silicon, silicon oxide, quartz, sapphire, silicon carbide, silicon nitride, gallium nitride and diamond; The material of the dielectric layer includes at least one of silicon oxide, silicon nitride, polysilicon, amorphous silicon, aluminum oxide and aluminum nitride; The thickness of the dielectric layer is 10nm to 2000nm; The material of the patterned electrode layer includes at least one of gold, silver, copper, aluminum, nickel, platinum, titanium, tantalum, tungsten, chromium and molybdenum; The thickness of the patterned electrode layer is 5nm to 150nm; The material of the piezoelectric film layer includes at least one of single crystal lithium niobate, single crystal lithium tantalate, aluminum nitride, scandium-doped aluminum nitride and lead zirconate titanate; The thickness of the piezoelectric film layer is 50nm-2200nm.

6. A method for preparing a piezoelectric heterogeneous substrate, characterized in that: include: Bonding the original exposed surface of the piezoelectric wafer substrate to the surface of the sacrificial protection structure, and thinning the piezoelectric wafer substrate to form a piezoelectric film layer on the sacrificial protection structure to obtain a composite structure; the piezoelectric film layer has a first surface and a second surface that are opposite to each other, the first surface is the original exposed surface of the piezoelectric wafer substrate, the second surface is a surface formed by thinning the side of the piezoelectric wafer substrate away from the original exposed surface, and the second surface is exposed to the surface of the composite structure; A patterned electrode layer and a dielectric layer are formed on the second surface; the patterned electrode layer is located in the dielectric layer, and one side of the patterned electrode layer is exposed to the dielectric layer and is electrically connected to the piezoelectric film layer; Bonding a surface of the composite structure having the dielectric layer on one side thereof to a surface of a substrate layer, and removing the sacrificial protection structure to obtain a piezoelectric heterogeneous substrate; The piezoelectric heterogeneous substrate comprises a substrate layer, a dielectric layer, a patterned electrode layer and a piezoelectric film layer. The first surface of the piezoelectric film layer is located on a side of the piezoelectric film layer away from the substrate layer.

7. The method for preparing a piezoelectric heterogeneous substrate according to claim 6, characterized in that: The sacrificial protection structure comprises a sacrificial layer and an oxide layer. In the composite structure, the oxide layer is located between the sacrificial layer and the piezoelectric film layer. The sacrificial protection structure is obtained by the following steps: Thermal oxidation is performed on one side surface of the sacrificial layer to form the oxide layer on the sacrificial layer; the thickness of the oxide layer is 100 nm to 10000 nm.

8. The method for preparing a piezoelectric heterogeneous substrate according to claim 7, characterized in that: Before bonding the surface of the composite structure having the dielectric layer to the surface of the substrate layer and removing the sacrificial protection structure to obtain the piezoelectric heterogeneous substrate, the method further includes: The composite structure is chamfered to form a chamfer at the edge of the composite structure; the depth of the chamfer is greater than or equal to the preset thickness of the sacrificial layer, and the width of the chamfer is 0.5 mm to 5 mm.

9. The method for preparing a piezoelectric heterogeneous substrate according to claim 6, characterized in that: After forming a patterned electrode layer and a dielectric layer on the second surface, the method further comprises: The composite structure is subjected to a first heat treatment; the temperature of the first heat treatment is greater than the forming temperature of the dielectric layer, and the time of the first heat treatment is greater than the forming time of the dielectric layer.

10. A semiconductor device, characterized in that: It comprises the piezoelectric heterogeneous substrate and surface electrodes as described in any one of claims 1 to 5, wherein the surface electrodes are located on the piezoelectric film layer and at least part of the surface electrodes are arranged on the patterned electrode layer.

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