Layout and logic diagram comparison LVS verification method and device

Abstract

The invention provides a layout and logic diagram comparison LVS verification method, which is applied to a three-dimensional integrated circuit (3D IC) comprising at least two bare chip stacked layer by layer and at least one through silicon via (TSV), and comprises the following steps: acquiring a first netlist file; obtaining a first layout file, wherein the first layout file comprises a circuit layout of the three-dimensional integrated circuit; according to the first layout file, constructing a simplified model of the three-dimensional integrated circuit, the simplified model comprising a connection relationship and a stack structure of the at least two bare chips and the at least one TSV in a circuit layout; and comparing the first netlist file with the simplified model to obtain LVS verification information of the three-dimensional integrated circuit. According to the method, the 3D IC is simplified into a plurality of independent models, and then the models are converted into LVS verification of the 2D stacked model, so that the operation efficiency of the LVS verification is optimized.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip design, and more specifically, to a method and device for LVS verification of layout and logic diagram comparison. Background Art

[0002] Three-dimensional integrated circuits (3D ICs) are developed on the basis of traditional two-dimensional integrated circuits. They are new integrated circuits that integrate different functional devices and circuits vertically. The packaging technology of 3D IC is also called stacked chip packaging technology, which refers to the packaging technology of stacking two or more bare crystal chips (dies) vertically in the same package without changing the size of the package. Compared with 2D packaging technology and 2.5D packaging technology, the principle of 3D packaging technology is to make a chip stacking structure and directly use through silicon vias (TSV) to connect the electronic signals of different bare crystal chips above and below, so as to directly stack memory or other bare crystal chips vertically. 3D packaging technology has a smaller packaging area, lower power consumption, and ultra-large bandwidth.

[0003] Layout versus schematics (LVS) verification is used to verify whether the layout and logic diagram of an integrated circuit or chip match. For the structure of multiple bare die chips stacked layer by layer in 3D IC, there is currently no complete LVS verification solution. Engineers need to check the connectivity of the stacking interface based on their own experience or script tools, which is inefficient and inaccurate. Therefore, there is an urgent need for a method to efficiently implement LVS verification of 3D IC bare die chip stacking structures. Summary of the invention

[0004] The embodiments of the present application provide a method and device for LVS verification of layout and logic diagram comparison, which can abstract the 3D stacking structure into a simplified model, greatly reduce the running time of verification, effectively improve the verification efficiency, and make LVS verification of the 3D stacking part feasible.

[0005] In a first aspect, an embodiment of the present application provides a method for LVS verification by comparing a layout with a logic diagram, the method being applied to LVS verification of a three-dimensional integrated circuit, the three-dimensional integrated circuit comprising at least two bare crystal chips stacked layer by layer and at least one through silicon via TSV for connecting the at least two bare crystal chips, the method comprising: obtaining a first netlist file, the first netlist file comprising a netlist statement for describing a logical connection relationship between the at least two bare crystal chips and the at least one TSV; obtaining a first layout file, the first layout file comprising a circuit layout of the three-dimensional integrated circuit; constructing a simplified model of the three-dimensional integrated circuit according to the first layout file, the simplified model comprising a connection relationship and a stacking structure between the at least two bare crystal chips and the at least one TSV in the circuit layout; comparing the first netlist file with the simplified model to obtain LVS verification information of the three-dimensional integrated circuit.

[0006] In the solution of the embodiment of the present application, by constructing a simplified model of the at least two bare die chips and the at least one TSV, the LVS verification of the three-dimensional stacked part is transformed into a complete LVS verification that can be performed by a conventional 2D LVS verification tool. In addition, since the 3D stacked structure is abstracted into a simplified model, the running time of the verification is greatly reduced, the verification efficiency is effectively improved, and the LVS verification of the 3D stacked part becomes feasible.

[0007] In combination with the first aspect, in a possible implementation of the first aspect, the first netlist file is compared with the simplified model to obtain LVS verification information of the three-dimensional integrated circuit, including: obtaining a first rule file, the first rule file including multiple rule instructions for describing the at least two bare crystal chips, the at least one TSV, the connection relationship and the stacking structure; determining a second netlist file from the simplified model according to the multiple rule instructions, the second netlist file including netlist statements for describing the connection relationship and the stacking structure; comparing the first netlist file with the second netlist file to obtain the LVS verification information.

[0008] In combination with the first aspect, in a possible implementation of the first aspect, obtaining the first rule file includes: determining a first rule instruction for describing the at least two bare die chips and the at least one TSV based on the circuit layer information of each bare die chip in the simplified model and the connection relationship between the circuit layers and the connection information of the input port and the output port of each TSV; determining a second rule instruction for describing the connection relationship and the stacking structure between the at least two bare die chips and the at least one TSV; and merging the first rule instruction and the second rule instruction to obtain the first rule file.

[0009] In the scheme of the embodiment of the present application, the rule instructions provided by different foundries are optimized and adjusted, and the rule instructions describing each bare crystal chip, each through silicon via and three-dimensional stacking structure are integrated to obtain a first rule file, so that the LVS verification process can use fused rule instructions instead of rule instructions with different syntaxes given by each foundry.

[0010] In combination with the first aspect, in a possible implementation of the first aspect, the at least one TSV is multiple TSVs, and the first netlist file further includes: a netlist statement for describing a connection relationship between the multiple TSVs, and a TSV module for defining each TSV in the multiple TSVs.

[0011] In the solution of the embodiment of the present application, multiple TSVs with different layouts and connection relationships are instantiated into the same TSV module, which improves the efficiency of netlist file design at the design end. Through this netlist structure design, the three-dimensional stacking structure can be converted into a complete, conventional 2D chip design.

[0012] In combination with the first aspect, in a possible implementation of the first aspect, constructing a simplified model of a three-dimensional integrated circuit includes: obtaining interface feature information of a first bare crystal chip among the at least two bare crystal chips, the interface feature information including interface names and coordinate positions of one or more interfaces of the first bare crystal chip; extracting partial circuit layers from the multi-layer circuit layers in the layout of the first bare crystal chip, the partial circuit layers including at least partial TSVs of the at least one TSV; constructing a simplified model of the first bare crystal chip based on the interface feature information of the first bare crystal chip and the partial circuit layers.

[0013] In the solution of the embodiment of the present application, by abstracting the bare crystal chip into a simplified model, the running time of the verification process is greatly optimized and the verification efficiency is effectively improved.

[0014] In combination with the first aspect, in a possible implementation of the first aspect, after constructing a simplified model of the first bare crystal chip, the method also includes: determining that the portion of the circuit layer includes one or more open circuit wirings; generating a wiring plane, connecting the one or more open circuit wirings through the wiring plane.

[0015] In the solution of the embodiment of the present application, since only part of the circuit layer is extracted, the power wiring or signal wiring of the part of the circuit layer may be broken, which has a fatal impact on the LVS verification of the entire three-dimensional stacking part. Therefore, the present application pulls the broken wiring through by designing the wiring plane, so that there is no fault situation of broken wiring due to the extraction of the circuit layer in the simplified model of the three-dimensional stacking structure.

[0016] In combination with the first aspect, in a possible implementation of the first aspect, constructing the simplified model of the three-dimensional integrated circuit includes: obtaining the functional type of the at least one TSV; and constructing the simplified model of the at least one TSV according to the functional type of the at least one TSV.

[0017] In combination with the first aspect, in a possible implementation of the first aspect, the functional type includes a signal TSV, which is used to transmit a signal; and according to the functional type of the at least one TSV, a simplified model of the at least one TSV is constructed, including: when it is determined that the at least one TSV is a signal TSV, the simplified model of the at least one TSV is constructed as a two-port device model, and the two ports of the two-port device model include an input port and an output port.

[0018] In the solution of the embodiment of the present application, the corresponding simplified model is determined based on the functional type of the through silicon via, so that the continuity of the signal in the through silicon via can be considered and the complexity of verification can be avoided.

[0019] In a second aspect, an embodiment of the present application provides a device for LVS verification by comparing a layout with a logic diagram, the device being applied to LVS verification of a three-dimensional integrated circuit, the three-dimensional integrated circuit comprising at least two bare crystal chips stacked layer by layer and at least one through silicon via TSV for connecting the at least two bare crystal chips, the device comprising: an acquisition module for acquiring a first netlist file, the first netlist file comprising a netlist statement for describing a logical connection relationship between the at least two bare crystal chips and the at least one TSV, and acquiring a first layout file, the first layout file comprising a circuit layout of the three-dimensional integrated circuit; a construction module for constructing a simplified model of the three-dimensional integrated circuit according to the first layout file, the simplified model comprising a connection relationship and a stacking structure between the at least two bare crystal chips and the at least one TSV in the circuit layout; a processing module for comparing the first netlist file with the simplified model to obtain LVS verification information of the three-dimensional integrated circuit.

[0020] In combination with the second aspect, in a possible implementation of the second aspect, the acquisition module is specifically used to: obtain a first rule file, the first rule file includes multiple rule instructions for describing the at least two bare crystal chips, the at least one TSV, the connection relationship and the stacking structure; the processing module is specifically used to: determine a second netlist file from the simplified model according to the multiple rule instructions, the second netlist file includes netlist statements for describing the connection relationship and the stacking structure; compare the first netlist file and the second netlist file to obtain LVS verification information.

[0021] In combination with the second aspect, in a possible implementation of the second aspect, the processing module is specifically used to: determine a first rule instruction for describing the at least two bare crystal chips and the at least one TSV based on the circuit layer information of each bare crystal chip in the simplified model and the connection relationship between the circuit layers and the connection information of the input port and the output port of each TSV; determine a second rule instruction for describing the connection relationship and the stacking structure between the at least two bare crystal chips and the at least one TSV; the acquisition module is specifically used to: merge the first rule instruction and the second rule instruction to obtain the first rule file.

[0022] In combination with the second aspect, in a possible implementation of the second aspect, the at least one TSV is multiple TSVs, and the first netlist file also includes: a netlist statement for describing a connection relationship between the multiple TSVs, and a TSV module for defining each TSV in the multiple TSVs.

[0023] In combination with the second aspect, in a possible implementation of the second aspect, the acquisition module is specifically used to: obtain interface feature information of the first bare crystal chip among the at least two bare crystal chips, and the interface feature information includes the interface name and coordinate position of one or more interfaces of the first bare crystal chip; the construction module is specifically used to: extract partial circuit layers from the multi-layer circuit layers in the layout of the first bare crystal chip, and the partial circuit layers include at least partial TSVs in the at least one TSV; construct a simplified model of the first bare crystal chip based on the interface feature information of the first bare crystal chip and the partial circuit layers.

[0024] In combination with the second aspect, in a possible implementation of the second aspect, the device also includes a generation module, and after the construction module constructs a simplified model of the first bare crystal chip, the generation module is used to determine that the part of the circuit layer includes one or more open circuit wirings; generate a wiring plane, and connect the one or more open circuit wirings through the wiring plane.

[0025] In combination with the second aspect, in a possible implementation manner of the second aspect, the construction module is specifically used to: obtain the functional type of the at least one TSV; and construct a simplified model of the at least one TSV according to the functional type of the at least one TSV.

[0026] In combination with the second aspect, in a possible implementation of the second aspect, the function type includes a signal TSV, which is used to transmit a signal; the construction module is specifically used to: when determining that the at least one TSV is a signal TSV, construct a simplified model of the at least one TSV as a two-port device model, and the two ports of the two-port device model include an input port and an output port.

[0027] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, which stores program code. When the computer storage medium runs on a computer, it enables the computer to execute the first aspect or any possible implementation of the first aspect.

[0028] In a fourth aspect, an embodiment of the present application provides a computer program product, which includes: a computer program code, when the computer program code runs on a computer, enables the computer to execute the first aspect or any possible implementation of the first aspect.

[0029] In a fifth aspect, an embodiment of the present application provides a computer device, which includes a processor, wherein the processor is used to couple with a memory, read and execute instructions and / or program codes in the memory to execute the first aspect or any possible implementation of the first aspect.

[0030] In a sixth aspect, an embodiment of the present application provides a chip system, which includes a logic circuit, which is used to couple with an input / output interface and transmit data through the input / output interface to execute the first aspect or any possible implementation method of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of a 3D IC package provided in an embodiment of the present application.

[0032] Figure 2 It is a schematic flowchart of an LVS verification process provided in an embodiment of the present application.

[0033] Figure 3 It is a schematic flow chart of a LVS verification method provided in an embodiment of the present application.

[0034] Figure 4 It is a schematic diagram of a first netlist file provided in an embodiment of the present application.

[0035] Figure 5 It is a schematic diagram of a simplified model of a through silicon via TSV provided in an embodiment of the present application.

[0036] Figure 6 It is a schematic diagram of a simplified model of a bare crystal chip shown in an embodiment of the present application.

[0037] Figure 7 It is a schematic diagram of a simplified correction model shown in an embodiment of the present application.

[0038] Figure 8 It is a schematic diagram of another simplified correction model shown in an embodiment of the present application.

[0039] Fig. 9 It is a schematic structural block diagram of an LVS verification device provided in an embodiment of the present application.

[0040] Fig.10 It is a schematic diagram of the hardware structure of an LVS verification device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0042] In order to facilitate understanding of the technical solution of the present application, the professional terms mentioned in the present application are briefly explained below.

[0043] 1. 3D IC packaging

[0044] At present, 3D IC packaging is an emerging semiconductor packaging technology that can achieve high-speed and high-density interconnection between chips. The interconnection methods of 2D packaging, 2.5D packaging and 3D IC packaging are different. Figure 1 A schematic diagram showing an interconnection method of a 3D IC package is shown.

[0045] In 2D packaging technology, all bare die and passive components are mounted horizontally on Figure 1 The surface of the substrate shown in the figure is directly in contact with the surface of the substrate, such as fan-out wafer-level packaging (FOWLP) and fan-out panel level package (FOPLP). Except for a very small number of bonding points directly connected by bonding wires, the electrical connections in 2D packaging technology need to pass through the substrate. Furthermore, 2D+ packaging technology has been developed based on 2D packaging technology. 2D+ packaging technology refers to a 3D structure of bare die stacked and connected by bonding wires. In the stacked 3D structure, its electrical interconnection needs to pass through the substrate, that is, first bonded to the substrate by bonding wires, and then electrically interconnected on the substrate.

[0046] like Figure 1 If die#2 is not included, then Figure 1 The structure shown is a 2.5D package. In a 2.5D package, the die or passive components are placed side by side on a silicon interposer. The die or passive components are connected to the silicon interposer through micro bumps. The silicon interposer is connected to the substrate through bumps, and the silicon through-holes serve as channels for electrical connection between the upper and lower surfaces of the silicon substrate. Therefore, a 2.5D package requires the manufacture of a silicon-based interposer and requires complex process steps such as lithography.

[0047] As process technology continues to scale and design complexity continues to increase, traditional 2D and 2.5D integrated chip designs are unable to meet the market's rapidly growing high-performance needs. 2D packaging requires a large number of long-distance interconnects, which leads to increased circuit delays, so the concept of 3D integrated chips was proposed. Figure 1 As shown in the dotted box in the figure, 3D integrated chips are stacked vertically, and the stacked multiple chip dies are connected with shorter silicon via interconnections and high bandwidth, which makes up for the shortcomings of two-dimensional integrated circuit design. In order to improve the signal transmission speed, the 3D packaged silicon via short-range vertical interconnection replaces the 2D packaged bonding wire long-range interconnection. At the same time, compared with the high-density interconnection achieved through the interposer in 2.5D packaging, the 3D package achieves high-density interconnection through silicon vias, and the package area is smaller than that of 2.5D packaging.

[0048] like Figure 1 As shown in the figure, unlike 2D packaging that interconnects through bonding wires and 2.5D packaging that routes and punches holes in the silicon interposer, 3D IC packaging directly drills and routes holes on multiple bare die chips in the stacked structure to connect the upper and lower bare die chips. As shown in the dotted box, in the physical structure of the 3D stacking part, multiple bare die chips are stacked together, and silicon through vias can pass through the bare die chips to achieve internal vertical electrical connections between the upper and lower bare die chips. For ease of description, the following will be Figure 1 The dotted line frame portion in the figure is called the "three-dimensional stacking portion" or "three-dimensional stacking structure". The upper and lower bare die chips can be multiple bare die chips of the same type, such as the stack structure in dynamic random access memory (DRAM). The upper and lower bare die chips can also be Figure 1 The different types of die #1 and die #2 shown in the figure can be made by different foundries and have different processes. In addition, other bare die chips or passive devices such as Figure 1 Die#1 and die#3 in the example are mounted on an interposer, which can provide electrical interconnection for the bare die chips on the interposer.

[0049] 2. LVS

[0050] LVS verification is used to verify whether the layout and logic diagram match, or LVS compares the connectivity of the layout and logic diagram at the transistor level, and then outputs all inconsistencies.

[0051] Figure 2A schematic flow chart of an LVS verification flow is shown, wherein the input files of the LVS verification flow generally include a schematic netlist file, a design rule file, and a layout stream file.

[0052] The schematic netlist file may include a circuit netlist, such as a gate-level Verilog netlist combined with a simulation program with integrated circuit emphasis, spice model / CDL (circuit description language) model to convert into a spice netlist. A circuit netlist is a text file that describes a circuit in terms of components, nodes, and connection modes, including detailed information about the circuit, such as the types and properties of the components used, descriptions of connections between components, and definitions of power supplies. A circuit netlist may be a netlist text representation of an electronic circuit, listing all components and connections between components. In an embodiment of the present application, the components in the spice netlist may be a bare crystal chip and TSV in a 3D IC, the nodes may be multiple interfaces in the bare crystal chip and signal ports of the TSV, etc., the connection mode may be a logical connection relationship between the bare crystal chip and the TSV, etc., and the LVS verification process requires that the logical connection relationship be compared with the physical connection relationship in the layout file.

[0053] The layout file is used to describe the plane geometry of the actual integrated circuit physical layout. After the layout and wiring of the design results in the integrated circuit design process, the results of the logic design are converted into the physical layout description of the actual integrated circuit. For example, in an embodiment of the present application, the layout file can be a GDSII (graphical design system / graphic data system) file. The GDSII file is a binary file that contains the plane geometry, text or labels in the integrated circuit layout, as well as other related information composed of a hierarchical structure. The data of the GDSII file can be used to reconstruct all or part of the layout information, and can also be used to make a photolithography mask.

[0054] The design rule file consists of the rule instructions required to perform LVS verification. In an embodiment of the present application, the rule instructions may include the stacking structure information of the integrated circuit and the description of each component and connection relationship. For example, it may include the rule instructions for defining how many layers of bare crystal chips a signal passes through for transmission, the rule instructions for defining each circuit layer in the chip bare crystal, or the rule instructions for defining the input and output ports of TSV. The design rule file is used to extract the physical netlist used to describe the connection relationship in the layout from the layout layout file during the LVS verification process.

[0055] like Figure 2 As shown in the process, the LVS verification process mainly consists of the following steps:

[0056] First, according to the design rule file, the LVS verification tool extracts the physical netlist determined according to the actual layout from the layout file, such as extracting the device information in the layout and then extracting the physical connection relationship or actual connection relationship between the devices. Among them, the device information includes the devices and device properties in the physical layout, such as the bare crystal chip and the layer definition of the bare crystal chip, and the physical connection relationship includes the connecting lines between different semiconductor devices. The extraction process needs to be based on the rule instructions in the design rule file that describe the devices, device properties, and physical connection relationships. This part of the content will be introduced in detail below and will not be repeated here.

[0057] Then, the physical netlist obtained in the above steps is compared with the circuit netlist in the schematic netlist file. The comparison process may include preprocessing processes of the physical netlist such as series-parallel structure simplification, virtual device filtering, gate circuit identification, and comparison of netlist topology structures. For example, in layout design, field effect transistors (metal-oxide-semiconductor field-effect transistors, MOSFETs) usually use the layout folding method to be equivalent to the parallel connection of multiple transistors. The preprocessing process can merge the folded, parallel or series devices in the layout into a complete device for LVS verification. For another example, the netlist comparison process can be to compare each node in the circuit netlist and the physical netlist one by one. If two nodes that are interconnected on the physical netlist or layout are not connected at the corresponding positions on the circuit netlist or schematic, an error report can be output.

[0058] Finally, based on the output LVS verification information including the error report, the input layout file is corrected, and finally a layout file is obtained whose physical connection relationship is consistent with the logical connection relationship in the schematic netlist file.

[0059] At present, LVS verification of 2D packaging technology and 2.5D packaging technology mainly focuses on the connectivity of bumps in the stacking interface, such as the connectivity between bare die chips and bumps on the silicon interposer or the connectivity of bumps in the upper and lower interfaces of the silicon interposer. In 3D IC packaging technology, the connection between chip bare die is through TSV instead of bumps, so LVS verification of 2.5D packaging technology is not applicable to 3D IC packaging technology.

[0060] Moreover, the layout file for LVS verification of 2.5D packaging technology is the complete layout of chip die, silicon interposer and substrate. In 3D IC, multiple stacked die chips may be of the same type, that is, the complete layout of multiple die chips may be the same. In this case, the logical connection relationship in LVS verification of 2.5D packaging technology is not accurate, for example Figure 1 As shown, the bottom layer die#1 is connected to one of the interfaces of the upper layer die#2, but due to Figure 1 The complete layouts of multiple die#2s in the 3D ID are exactly the same, and the interface feature information defined is also exactly the same. At this time, if the LVS verification method of 2.5D packaging technology is used, the error of connecting die#1 to the same interface of all die#2s will occur. In addition, when there are a large number of bare die chips stacked in 3D ID, there are a large number of connection interfaces that need to be verified. At this time, the verification process is complicated, and the LVS verification is time-consuming and inefficient.

[0061] In order to solve the above technical problems, the present application proposes a LVS verification method 300, which is applied to LVS verification of a three-dimensional stacked structure. The other parts of the three-dimensional integrated circuit except the three-dimensional stacked structure can be verified by the conventional 2D packaging or 2.5D packaging LVS verification method, which is not limited by the present application. Figure 1 As shown, it includes at least two bare die chips stacked layer by layer in a dotted frame and at least one through silicon via TSV for connecting the at least two bare die chips. Figure 3 A schematic flowchart of method 300 is shown, wherein method 300 includes steps 310 to 340. By constructing a simplified model of the at least two bare die chips and the at least one TSV, method 300 converts the LVS verification of the three-dimensional stacked part into a complete LVS verification that can be performed by a conventional 2D LVS verification tool. In addition, since method 300 abstracts the three-dimensional stacked structure into a simplified model, the running time of the verification is greatly reduced, the verification efficiency is effectively improved, and the LVS verification of the 3D stacked part becomes feasible.

[0062] Step 310: Obtain a first netlist file.

[0063] The first netlist file is the schematic netlist file mentioned above, and includes a netlist statement for describing the logical connection relationship between at least two bare crystal chips and at least one TSV. For example, the logical connection relationship included in the first netlist file may be a logical connection relationship of signals in a stacked structure, where a signal is transmitted from one of the signal interfaces of a bare crystal chip to an input port of the TSV, and an output port of the TSV transmits the signal to a signal interface of another bare crystal chip.

[0064] In addition, as described above with respect to the netlist file, the first netlist file may also include device modules, such as a die module and a TSV module. In an embodiment of the present application, Figure 1 The stacked structure of the three-dimensional integrated circuit shown may include multiple through silicon vias, and each of the multiple through silicon vias may be defined by a TSV module in the first netlist file, and the same is true for the die module. Figure 1 The three-dimensional stacked structure shown in the dotted box includes 100 through silicon vias or a larger number of through silicon vias. If the 100 through silicon vias or a larger number of through silicon vias are modularized, the efficiency will be low and the netlist content will be complicated. Therefore, only one TSV module can be used to repeatedly define the above 100 through silicon vias or a larger number of through silicon vias.

[0065] Figure 4 FIG. 1 shows a schematic diagram of a first netlist file. Figure 4 As shown in (a), the signal is input from interface A in die#1, transmitted to input port a1 of TSV#1, passes through two layers of die#2 to output port a2, and finally transmitted to interface B of die#2 on the third layer from bottom to top to realize signal output. Figure 4 As shown in (b), each bare die and TSV is instantiated into a die module and a TSV module. The modularized U_die1 (die#1), U_TSV1 (TSV#1) and U_die4 (top-level die#2) include the above-defined interfaces A, B and ports a1 and a2. According to the logical connection relationship between the bare die and TSV defined by the design end, that is, the ports for the above-mentioned signal connections and the signal transmission paths, the first netlist is determined to include the following Verilog statement description:

[0066] "module 3D_TOP(A,B,C……)

[0067] U_Die1 Die1 A a1;

[0068] U_TSV1 TSV a1 a2;

[0069] U_Die4 Die2 a2 B;”

[0070] in, Figure 4 The four layers of bare crystal chips from bottom to top in (a) are respectively instantiated as U_Die1~U_Die4 in the die sub-module, and the two TSVs from left to right are respectively instantiated as U_TSV1 and U_TSV2 in the TSV sub-module. "U_TSV1 TSV A a1" means that the signal is transmitted from the A interface to the a1 port of the TSV in the bottom layer Die#1, "U_TSV2 TSV a1a2" means that the signal is transmitted from the a1 port to the a2 port in the TSV, and "U_Die3 Die2 a2 B" means that the signal is transmitted from the a2 port of the TSV to the B interface of the third layer Die#2 from bottom to top. Similarly, the signal logical connection relationship of U_TSV2 can also be represented by the first netlist file. In the embodiment of the present application, the Verilog statement description of the above example can be converted into Figure 4 The Spice netlist shown in (c) is used for LVS verification.

[0071] Step 320: Obtain a first layout file.

[0072] The first layout file is the layout file mentioned above, and may include a circuit layout of a three-dimensional integrated circuit.

[0073] Step 330: constructing a simplified model of the three-dimensional integrated circuit according to the first layout file, wherein the simplified model includes a connection relationship and a stacking structure between the at least two bare die chips and the at least one TSV in the circuit layout.

[0074] In an embodiment of the present application, a simplified model of a three-dimensional integrated circuit may include a simplified model of a three-dimensional stacked structure. The construction process of the simplified model of a through silicon via may be to determine the functional type of the through silicon via according to the physical connection information of the at least one through silicon via, and to construct the simplified model of the through silicon via according to the functional type of the through silicon via; the construction process of a simplified model of a bare crystal chip may be to extract the interface feature information of each bare crystal chip, and integrate the interface indicated by the interface feature information and multiple circuit layers into a simplified model. The specific construction process will be introduced below and will not be repeated here.

[0075] Optionally, in an embodiment of the present application, the physical connection information of the at least one through silicon via, the interface feature information of each bare crystal chip, and the connection relationship between the bare crystal chip and the through silicon via can be extracted from the first layout file in step 320, or can be extracted from the design file provided by the design end and combined with the three-dimensional stacking structure in the first layout file to form a simplified model. For example, the design file of the design end includes a text file, and the text file includes a text description of the physical connection information and the interface feature information.

[0076] Figure 5 A schematic diagram of a simplified model of a through silicon via is shown. The functional types of through silicon vias include signal TSV and power TSV. The input and output ports of the signal TSV are used to connect to the interface of the bare die chip to transmit signals, such as Figure 4 As shown in U_TSV1 and U_TSV2, the input and output ports of the power TSV can be used to connect to the power interface of the bare die chip to transmit power energy for power supply, or are not connected to any bare die chip.

[0077] like Figure 5 As shown, if the through silicon via is a signal TSV, the present application constructs the signal TSV as a two-port device model, and the two ports of the two-port device model are used to describe the input interface and output interface of the signal TSV. Figure 4 The silicon through via shown in (a) in the figure, by identifying the interface connected to the input and output ports of U_TSV1, the input port a1 and the output port a2 of U_TSV1 are obtained, U_TSV1 is determined to be a signal TSV, and the interface of the bare crystal chip connected to the input and output interfaces of U_TSV1 is determined to be the interface A of the bottom layer die#1 and the interface B of the third layer die#2 from bottom to top. Then, the simplified model of U_TSV1 is constructed as a two-port device model, with the input port as interface A and the output port as interface B. If the TSV is a power TSV, the present application may not construct a simplified model for the power TSV, but only needs to treat the power TSV as a metal layer, and describe the power TSV in the first netlist file mentioned above as being used to provide power energy for one or more bare crystal chips. In other embodiments of the present application, a simplified model may also be constructed for the power TSV, for example, a portless device model is constructed to indicate that the silicon through via is used to provide power energy.

[0078] Figure 6 A schematic diagram of a simplified model of a bare crystal chip is shown. The simplified model of the bare crystal chip may include the acquired interface feature information of the bare crystal chip, such as the interface name, coordinate position, interface load, etc. of multiple interfaces in the bare crystal chip, and the interface feature information and multiple circuit layers are integrated into a simplified model. The specific construction process of the simplified model of the bare crystal chip will be introduced below, which will not be repeated here.

[0079] Optionally, in some embodiments of the present application, information about the interface between the bare die chip and the through silicon via in the first netlist file is as follows: Figure 4The interfaces A, a1, a2, and B shown can be obtained through the simplified model of step 330. In other words, step 330 may not be executed in the same order as step 310. The present application may determine the interface information of the bare crystal chip and the through silicon via according to the simplified model obtained in step 330, and merge the netlist describing the interface information of the bare crystal chip and the through silicon via with the obtained netlist describing the logical connection relationship or stacking structure of the bare crystal chip and the through silicon via to obtain a complete first netlist file. The netlist describing the stacking structure of the bare crystal chip and the through silicon via can also be obtained based on the complete simplified model of the stacking structure in step 330, such as which layers of bare crystal chips, which through silicon vias are included in the stacking structure, and how many layers of bare crystal chips the signal transmitted in the through silicon via penetrates.

[0080] Step 340: Compare the first netlist file with the simplified model to obtain LVS verification information of the three-dimensional integrated circuit.

[0081] like Figure 2 As shown in the LVS verification process in, in an embodiment of the present application, the process of comparing the first netlist file with the simplified model can be: obtaining a first rule file, the first rule file including multiple rule instructions for describing at least two bare crystal chips, at least one silicon through via, and a connection relationship and a stacking structure of the stacking part; and extracting a second netlist file from the simplified model based on the first rule file or the multiple rule instructions, the second netlist file is the physical netlist mentioned above, including a netlist statement for describing the connection relationship and the stacking structure of the three-dimensional stacking part of the three-dimensional integrated circuit; finally, the first netlist file in step 310 is compared with the above-mentioned second netlist file to obtain LVS verification information of the stacking part of the three-dimensional integrated circuit.

[0082] Optionally, the first rule file can be obtained based on the simplified model obtained in step 330. For example, the simplified model of the bare crystal chip includes interface feature information and multiple circuit layers. The first rule file may include rule instructions describing the multiple circuit layers, interfaces and vias in the circuit layers, and definition rule instructions describing connection relationships, such as "INPUT-layer layer Metal#1=8" means defining a circuit layer Metal#1 in the layout of a bare crystal chip and the number of the circuit layer Metal#1 is 8, and "Connect Metal#1Metal#2by via#1" means that the circuit layer Metal#1 and the circuit layer Metal#2 are connected through via#1. The definition method of the rule instruction of via#1 is the same as the definition method of the rule instruction of the circuit layer. Via#1 can be a through hole between different circuit layers in the same bare crystal chip, or a silicon through hole used to connect different bare crystal chips. For example, the rule instructions describing each bare crystal chip may include the connection relationship between the circuit layers of each bare crystal chip (such as direct contact or connection through through holes between circuit layers), the rule instructions describing each through silicon via may include the input port and output port information of each through silicon via, and the rule instructions describing the stacked structure may include the connection relationship between the circuit layers of different bare crystal chips or the interfaces included in the circuit layers (such as connection through silicon vias) and how many layers of bare crystal chips are penetrated by the through silicon vias in the stacked structure.

[0083] In some other embodiments of the present application, the first rule file may be obtained by merging the first rule instructions and the second rule instructions. For example, the first rule instructions may be determined based on the circuit layer information of each bare crystal chip and the connection relationship between the circuit layers and the connection information of the input port and the output port of each silicon via in the simplified model, and is used to describe the bare crystal chip and the silicon via. The second rule file may be a description of the connection relationship and stacking structure between the bare crystal chip and the silicon via in the simplified model.

[0084] For example, if an interface of Metal#3 in bare die chip die#4 is connected to an interface of Metal#4 in bare die chip die#5 through silicon via#2, the first rule file defines Metal#3 in the rule instructions related to die#4, defines Metal#4 in the rule instructions related to die#5, defines silicon via#2, and defines the connection relationship "Connect Metal#3Metal#4by via#2". Furthermore, during the LVS verification process, based on the first rule file, the LVS verification tool locates the circuit layer Metal#3 of die#4, the circuit layer Metal#4 of die#5, and the silicon via#2 in the simplified model, extracts the relevant interfaces of Metal#3 and Metal#4 connected to the input port and output port of via#2 respectively, and adds the connection relationship between the interfaces and the die modules used to define die#4 and die#5 to the second netlist file.

[0085] Optionally, in an embodiment of the present application, if multiple bare crystal chips and TSVs stacked in a three-dimensional integrated circuit come from different foundries, that is, the process design kits (PDKs) corresponding to the multiple bare crystal chips and TSVs are different, the above-mentioned first rule instructions and second rule instructions can use the same rule syntax for design, for example, based on the rule instructions given by different foundries, adjust and optimize, remove some rule instructions based on the content of the simplified model, and modify multiple rule instructions to the same rule syntax to merge into a first rule file.

[0086] The method 300 of the present application proposes an efficient, simple and highly complete LVS verification method for 3D ICs. The method can transform the LVS verification of 3D ICs into the LVS verification of conventional 2D structures. In addition, since each bare die and TSV are abstracted into a simplified model, the runtime of the verification process is greatly optimized, the verification efficiency is effectively improved, and the LVS verification of the 3D stacked part becomes feasible.

[0087] The following is an introduction to a specific embodiment of constructing a simplified model of a bare die chip:

[0088] In an embodiment of the present application, a simplified model of a bare die chip is constructed by obtaining interface feature information of each bare die chip, such as interface name, coordinate position, interface load, etc., and extracting multiple circuit layers. As mentioned above, the interface feature information can be extracted from the complete layout file of the bare die chip, or from a text file included in the design file.

[0089] like Figure 6As shown in (a), label 1 is the extracted interface information of each stacked bare crystal chip, such as the name and coordinate position of all interfaces with connection relationships in each bare crystal chip, such as the name and coordinate position of a signal pin pin or the name and coordinate position of a power pin pin. Figure 6 This is just an example. The interface can be located in any circuit layer in the bare die. Figure 6 For ease of description, only some interfaces of some circuit layers are shown. In an embodiment of the present application, the information of the signal pin pin or the power pin pin can be obtained by the following method: For example, the present application can capture the name and coordinate position of the pin pin in the layout GDS file of multiple bare crystal chips stacked layer by layer through a script tool. For another example, the present application can parse the library exchange file (LEF) file generated by multiple chip bare crystals stacked layer by layer through a script to obtain the original coordinate position of each pin pin. Among them, the LEF file is a simplified version of the GDS file, which specifically records the layer definition, port position and through-hole definition in each circuit layer of the bare crystal chip, and the layer definition can also include the size information, size rules, etc. of the circuit layer.

[0090] like Figure 6 As shown in (b), reference numeral 2 is a partial circuit layer extracted from all circuit layers in the complete layout of each bare crystal chip. In an embodiment of the present application, the extraction method can be to capture the graphics of the partial circuit layer in the layout GDS file of each bare crystal chip through a script tool, and export it as a separate file. The partial circuit layer includes at least a portion of the through silicon vias. For example, Figure 6 As shown in (b), in the embodiment of the present application, if the through silicon via via#2 is connected to one of the circuit layers Metal#3 inside the bare crystal chip die#6, the part of the circuit layer to be extracted in the bare crystal chip die#6 can be the K circuit layers above and below the circuit layer Metal#3 (the value is 5 in the figure). For another example, Figure 6 As shown in (c), if the through silicon via #3 penetrates the bare die #7, the part of the circuit layer of die #7 that needs to be extracted can be the top K layer circuit layer of die #7 (the value in the figure is 5). In addition, Figure 6 The circuit layers shown in (b) and (c) may also include Figure 6 All interface pins that have connection relationships are extracted in (a).

[0091] If the value of K is small, the signal wiring and power wiring of the circuit layer interface will be divided into multiple parts, resulting in the graphics of some circuit layers being too complex; if the value of K is large, the calculation amount of the LVS verification process is large, resulting in a long running time. In the embodiment of the present application, the value of K is preferably 2 to 10. The reason is that each 2 to 10 layers close to TSV only contain power wiring and a small number of clock routing, and most of the interfaces are concentrated in the 2 to 10 layers. The interface is not complicated, and the cost-effectiveness of extracting the first 2 to 10 layers is the highest. In addition, since the number of circuit layers contained in the complete layout of the bare crystal chip is large and the layers are complex, the complexity of LVS verification can be reduced by extracting only part of the circuit layer. However, in the embodiment of the present application, the value of K can also be a value greater than or equal to 10, and the specific value of K needs to be determined based on the circuit layer information of the bare crystal chip.

[0092] Optionally, the simplified model of the bare die chip may also include a complex model of each interface. Figure 6 As shown in (d) in FIG. 1 , reference numeral 3 is a load model connected to the interface pin pin, i.e., a single-ended or multi-ended device model. Figure 6 The information of the interface pins of each bare die chip extracted in (a) and Figure 6 After the GDS graphics of the partial circuit layers of each bare die are exported from (b) and (c), the load information of each interface pin, i.e., the single-ended or multi-ended device model, is extracted through the script tool. Figure 6 The coordinates and interface position of each interface pin in (a) are automatically mounted on the single-ended or multi-terminal device model corresponding to each interface pin, such as a load power supply, a load driving circuit or a switching circuit. Figure 6 (d) is only an example, and only a schematic diagram of the load model of some interfaces is marked.

[0093] By Figure 6 The contents of labels 1 to 3 in the original layout file are integrated to remove the redundant circuit layers and layer definitions in the original layout file, and the simplified models of each bare die chip are obtained. Figure 5 The simplified model of the through-silicon via in the 3D IC stacking structure is transformed into the LVS verification of the conventional 2D stacking model, which effectively improves the efficiency of LVS verification.

[0094] Since this application constructs an equivalent model of the bare crystal chip and omits some circuit layers of the bare crystal chip, the equivalent model needs to be corrected to ensure that the equivalent model used as the layout file does not report errors during the LVS verification process. Figure 7 A method for calibrating a simplified model of a bare die is shown. Figure 7 As shown, since the embodiment of the present application extracts only part of the circuit layers when extracting the GDS graphics of the multi-layer circuit layers, there are open circuits in the power wiring or signal wiring in part of the circuit layers, that is, the complete loop of the open power wiring or signal wiring exists in other circuit layers in the multi-layer circuit layers that have not been extracted. Figure 7 The two interface wirings connected to the same resistor and the two interface wirings connected to each other become disconnected wirings after being extracted from a part of the circuit layer. Figure 7 The interface wiring connected to the ground line becomes a disconnected wiring because the ground line is located in other circuit layers.

[0095] The open wiring situation has a great impact on LVS verification, so it is necessary to identify and analyze the open wiring, and connect the open wiring to solve the problem of open circuit. Therefore, the embodiment of the present application can automatically extract the open circuit power wiring and the open circuit signal wiring in this part of the circuit layer through a script tool, and design one or more wiring planes to connect the connected open circuit wiring in the original complete layout, so that there is no open circuit wiring in the simplified model of each bare crystal chip. Among them, the open circuit wiring with the same function or connected to the same circuit element can be connected to the same wiring plane, for example Figure 7 The two interface wirings connected to the same resistor are connected to wiring plane 1, and all wirings connected to the ground line can be connected to wiring plane 3. The one or more wiring planes can be defined in the first rule file by rule instructions, for example, as a layer definition in the first rule file, and describe that the disconnection wiring is connected to the above wiring plane, or as Figure 7 As shown, a through layer or circuit layer is generated in the simplified model, and the disconnection wiring is connected to the layer or circuit layer.

[0096] Specifically, the method for determining whether a part of the circuit layer includes disconnected power wiring and disconnected signal wiring can be to use the existing LVS verification method of 2D integrated circuits, that is, to verify whether there is disconnected circuit wiring and disconnected signal wiring in a single bare die chip, and to locate and extract the coordinate position and connection relationship of the disconnected wiring through a script tool. Finally, the disconnected wiring can be connected by defining or simplifying the layers or circuit layers added to the model through the above rule instructions.

[0097] Figure 8 Another method for correcting the simplified model of a bare die chip is shown. Since the multiple bare die chips stacked layer by layer in a 3D IC can be of the same type, and the multiple simplified models corresponding to the multiple bare die chips of the same type are exactly the same, that is, each bare die chip has the same interface feature information. However, as mentioned above, if Figure 1As shown, the bottom layer die#1 is connected to an interface of one of the die#2s, and eventually the LVS verification process in the embodiment of the present application will result in an error that die#1 is connected to the same interface of all the die#2s. Therefore, it is necessary to heterogeneously divide the multiple simplified models corresponding to the multiple bare die chips of the same type to distinguish the multiple identical simplified models, so that the multiple simplified models corresponding to the multiple bare die chips of the same type become unique simplified models.

[0098] For example, the embodiment of the present application shows a method of heterogeneous simplified model, that is, for multiple bare die chips of the same type, the present application generates a simplified model of a bare die chip and copies it multiple times, and distinguishes the multiple bare die chips of the same type by numbering the circuit layers in the multiple identical simplified models differently. Figure 8 As shown, based on Figure 1 The three-dimensional stacked structure shown in the figure, the present application can generate a simplified model of die#2 and copy it three times, and can use the script tool to number the three circuit layers in the three simplified models of die#2 separately, and the three circuit layers in the three simplified models of die#2 are numbered 11.1-11.3 to 13.1-13.3 respectively. Furthermore, in the first netlist file and the first rule file, the circuit layer where the interface is located can be Figure 8 The numbers shown are used to indicate the above connection relationships to avoid conflicts. Figure 4 In the first netlist file shown, U_TSV1 sends the signal from interface a2 to interface B of circuit layer 13 . 3 of die# 2 instead of all interfaces B of die# 2.

[0099] Through the above process of correcting the simplified model, the problem of broken wiring in the simplified model is solved, and the simplified models of all bare die chips in the 3D stacking structure are unique. In this way, the LVS verification problem of the 3D IC stacking part is converted into a conventional 2D stacking structure that can be verified by conventional 2D LVS verification tools.

[0100] Combine the following Fig. 9 and Fig.10 The device of the embodiment of the present application is described. It should be understood that the device described below can execute the method of the embodiment of the present application, and in order to avoid unnecessary repetition, repeated descriptions are appropriately omitted when introducing the device of the embodiment of the present application.

[0101] Fig. 9 1 is a schematic structural block diagram of a device for LVS verification of layout and logic diagram comparison provided in an embodiment of the present application. Fig. 9The illustrated device 900 for LVS verification by comparing layout with logic diagram includes an acquisition module 901, a construction module 902, and a processing module 903. The acquisition module 901 is used to: acquire a first netlist file, the first netlist file includes a netlist statement for describing the logical connection relationship between the at least two bare crystal chips and the at least one TSV, and acquire a first layout file, the first layout file includes the circuit layout of the three-dimensional integrated circuit; the construction module 902 is used to: construct a simplified model of the three-dimensional integrated circuit according to the first layout file, the simplified model includes the connection relationship and stacking structure of the at least two bare crystal chips and the at least one TSV in the circuit layout; the processing module 903 is used to: compare the first netlist file with the simplified model to obtain LVS verification information of the three-dimensional integrated circuit.

[0102] Optionally, the acquisition module 901 is specifically used to: acquire a first rule file, the first rule file including multiple rule instructions for describing the at least two bare crystal chips, the at least one TSV, the connection relationship and the stacking structure; the processing module 903 is specifically used to: determine a second netlist file from the simplified model according to the multiple rule instructions, the second netlist file including netlist statements for describing the connection relationship and the stacking structure; compare the first netlist file and the second netlist file to obtain LVS verification information.

[0103] Optionally, the processing module 903 is specifically used to: determine a first rule instruction for describing the at least two bare crystal chips and the at least one TSV based on the circuit layer information of each bare crystal chip in the simplified model and the connection relationship between the circuit layers and the connection information of the input port and the output port of each TSV; determine a second rule instruction for describing the connection relationship and the stacking structure of the at least two bare crystal chips and the at least one TSV; the acquisition module 901 is specifically used to: merge the first rule instruction and the second rule instruction to obtain the first rule file.

[0104] Optionally, the at least one TSV is a plurality of TSVs, and the first netlist file further includes: a netlist statement for describing a connection relationship between the plurality of TSVs, and a TSV module for defining each TSV in the plurality of TSVs.

[0105] Optionally, the acquisition module 901 is specifically used to: acquire interface feature information of the first bare crystal chip among the at least two bare crystal chips, the interface feature information including interface names and coordinate positions of one or more interfaces of the first bare crystal chip; the construction module 902 is specifically used to: extract partial circuit layers from the multi-layer circuit layers in the layout of the first bare crystal chip, the partial circuit layers including at least partial TSVs of the at least one TSV; construct a simplified model of the first bare crystal chip based on the interface feature information of the first bare crystal chip and the partial circuit layers.

[0106] Optionally, the device 900 also includes a generation module (not shown in the figure). After the construction module 902 constructs the simplified model of the first bare crystal chip, the generation module is used to determine that the part of the circuit layer includes one or more open circuit wirings; generate a wiring plane, and connect the one or more open circuit wirings through the wiring plane.

[0107] Optionally, the construction module 902 is specifically configured to: obtain the functional type of the at least one TSV; and construct a simplified model of the at least one TSV according to the functional type of the at least one TSV.

[0108] Optionally, the function type includes a signal TSV, which is used to transmit a signal; the construction module 902 is specifically used to: when determining that the at least one TSV is a signal TSV, construct a simplified model of the at least one TSV as a two-port device model, and the two ports of the two-port device model include an input port and an output port.

[0109] The device and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation processes are detailed in the method embodiments above, which will not be repeated here.

[0110] The modules of each example described in the embodiments of the present application can be implemented with electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0111] For example, in the implementation process, the acquisition module 901, the construction module 902 and the processing module 903 can be completed by instructions or program codes in the form of software, for example, by a combination of hardware and software modules in a processor. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory, and implements the acquisition module 901, the construction module 902 and the processing module 903 in combination with its hardware.

[0112] It should be noted that: when the device provided in the above embodiment executes the above method, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. For example, in device 900, acquisition module 901 can be used to execute any step in the above method, and processing unit 903 can be used to execute any step in the above method. The steps that each unit is responsible for implementing can be specified as needed, and all the functions of the above device can be realized by each unit implementing different steps in the above method.

[0113] Fig.10 It is a schematic diagram of the hardware structure of a device for LVS verification of layout and logic diagram comparison provided in an embodiment of the present application. Fig.10 The layout and logic diagram are compared to the LVS verification device 1000 (the device 1000 can be a computer device) including a memory 1001, a processor 1002, a communication interface 1003 and a bus 1004. The memory 1001, the processor 1002 and the communication interface 1003 are connected to each other through the bus 1004.

[0114] The memory 1001 may be a read-only memory (ROM), a static storage device, a dynamic storage device or a random access memory (RAM). The memory 1001 may store a program. When the program stored in the memory 1001 is executed by the processor 1002, the processor 1002 is used to execute the various steps of the method of the embodiment of the present application. For example, the processor 1002 may execute the method 300 described above.

[0115] Processor 1002 can adopt a general central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit (GPU) or one or more integrated circuits to execute relevant programs to implement the method of the method embodiment of the present application.

[0116] The processor 1002 may also be an integrated circuit chip with signal processing capability. In the implementation process, each step of the method of the present application may be completed by an integrated logic circuit of hardware in the processor 1002 or by instructions in the form of software.

[0117] The processor 1002 may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, or discrete hardware components. The methods, steps, and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed by a hardware decoding processor, or may be executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, or the like. The storage medium is located in the memory 1001, and the processor 1002 reads the information in the memory 1001 and completes the processing in combination with its hardware. Fig. 9 The functions required to be executed by the modules included in the shown device, or the method 300 of the method embodiment of the present application.

[0118] The communication interface 1003 uses a transceiver device such as but not limited to a transceiver to implement communication between the apparatus 1000 and other devices or a communication network.

[0119] The bus 1004 may include a path for transmitting information between various components of the device 1000 (eg, the memory 1001 , the processor 1002 , and the communication interface 1003 ).

[0120] An embodiment of the present application also provides a computer device, which includes a processor, and the processor is used to couple with a memory, read and execute instructions and / or program codes in the memory, so as to execute the method described in any one of the above embodiments.

[0121] An embodiment of the present application further provides a chip system, which includes a logic circuit, wherein the logic circuit is used to couple with an input / output interface and transmit data through the input / output interface to execute the method described in any one of the above embodiments.

[0122] It should be noted that the processor in the embodiment of the present application can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method embodiment can be completed by an integrated logic circuit of hardware in the processor or an instruction or program code in the form of software. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor to be executed, or a combination of hardware and software modules in the decoding processor to be executed. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0123] It can be understood that the memory in the embodiments of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0124] The present application also provides a computer program product, which includes: a computer program code, when the computer program code is run on a computer, the computer executes the method of any one of the above embodiments.

[0125] The present application also provides a computer-readable medium storing a program code. When the program code is executed on a computer, the computer executes a method of any one of the above embodiments.

[0126] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0127] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0128] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0129] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions or program codes to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0130] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for LVS verification by comparing layout and logic diagram, characterized in that: The method is applied to LVS verification of a three-dimensional integrated circuit, wherein the three-dimensional integrated circuit includes at least two bare crystal chips stacked layer by layer and at least one through silicon via TSV for connecting the at least two bare crystal chips, and the method includes: Acquire a first netlist file, wherein the first netlist file includes a netlist statement for describing a logical connection relationship between the at least two bare die chips and the at least one TSV; Acquire a first layout file, wherein the first layout file includes a circuit layout of the three-dimensional integrated circuit; Constructing a simplified model of the three-dimensional integrated circuit according to the first layout file, wherein the simplified model includes a connection relationship and a stacking structure of the at least two bare die chips and the at least one TSV in the circuit layout; The first netlist file is compared with the simplified model to obtain LVS verification information of the three-dimensional integrated circuit.

2. The method according to claim 1, characterized in that: The comparing the first netlist file with the simplified model to obtain LVS verification information of the three-dimensional integrated circuit includes: Obtaining a first rule file, wherein the first rule file includes a plurality of rule instructions for describing the at least two bare die chips, the at least one TSV, the connection relationship, and the stacking structure; Determine a second netlist file from the simplified model according to the plurality of rule instructions, wherein the second netlist file includes a netlist statement for describing the connection relationship and the stacking structure; The first netlist file and the second netlist file are compared to obtain the LVS verification information.

3. The method according to claim 2, characterized in that The obtaining of the first rule file comprises: Determine a first rule instruction for describing the at least two bare die chips and the at least one TSV according to the circuit layer information of each bare die chip and the connection relationship between the circuit layers and the connection information of the input port and the output port of each TSV in the simplified model; Determine a second rule instruction for describing a connection relationship and a stacking structure between the at least two bare die chips and the at least one TSV; The first rule instruction and the second rule instruction are merged to obtain the first rule file.

4. The method according to any one of claims 1 to 3, characterized in that The at least one TSV is a plurality of TSVs, and the first netlist file further includes: a netlist statement for describing a connection relationship among the plurality of TSVs, and a TSV module for defining each of the plurality of TSVs.

5. The method according to any one of claims 1 to 4, characterized in that The step of constructing the simplified model of the three-dimensional integrated circuit comprises: Acquire interface feature information of a first bare die chip among the at least two bare die chips, wherein the interface feature information includes interface names and coordinate positions of one or more interfaces of the first bare die chip; Extracting a portion of circuit layers from the multi-layer circuit layers in the layout of the first bare die chip, wherein the portion of circuit layers includes at least a portion of the at least one TSV; A simplified model of the first bare crystal chip is constructed according to the interface feature information of the first bare crystal chip and the partial circuit layer.

6. The method according to claim 5, characterized in that After constructing the simplified model of the first bare die chip, the method further includes: Determining that the partial circuit layer includes one or more disconnected wirings; A wiring plane is generated, through which the one or more disconnected wirings are connected.

7. The method according to any one of claims 1 to 6, characterized in that The step of constructing the simplified model of the three-dimensional integrated circuit comprises: Obtaining a functional category of the at least one TSV; A simplified model of the at least one TSV is constructed according to the functional category of the at least one TSV.

8. The method according to claim 7, characterized in that The functional category includes a signal TSV, and the signal TSV is used to transmit a signal; The step of constructing a simplified model of the at least one TSV according to the functional type of the at least one TSV includes: When it is determined that the at least one TSV is a signal TSV, the simplified model of the at least one TSV is constructed as a two-port device model, and the two ports of the two-port device model include an input port and an output port.

9. A device for LVS verification of layout and logic diagram, characterized in that: The device is applied to LVS verification of a three-dimensional integrated circuit, wherein the three-dimensional integrated circuit includes at least two bare crystal chips stacked layer by layer and at least one through silicon via TSV for connecting the at least two bare crystal chips, and the device includes: An acquisition module is used to: acquire a first netlist file, the first netlist file includes a netlist statement for describing a logical connection relationship between the at least two bare die chips and the at least one TSV, and acquire a first layout file, the first layout file includes a circuit layout of the three-dimensional integrated circuit; A construction module, configured to: construct a simplified model of the three-dimensional integrated circuit according to the first layout file, wherein the simplified model includes a connection relationship and a stacking structure between the at least two bare die chips and the at least one TSV in the circuit layout; The processing module is used to compare the first netlist file with the simplified model to obtain LVS verification information of the three-dimensional integrated circuit.

10. The device according to claim 9, characterized in that The acquisition module is specifically used for: Obtaining a first rule file, wherein the first rule file includes a plurality of rule instructions for describing the at least two bare die chips, the at least one TSV, the connection relationship, and the stacking structure; The processing module is specifically used for: Determine a second netlist file from the simplified model according to the plurality of rule instructions, wherein the second netlist file includes a netlist statement for describing the connection relationship and the stacking structure; The first netlist file and the second netlist file are compared to obtain the LVS verification information.

11. The device according to claim 10, characterized in that The processing module is specifically used for: Determine a first rule instruction for describing the at least two bare die chips and the at least one TSV according to the circuit layer information of each bare die chip and the connection relationship between the circuit layers and the connection information of the input port and the output port of each TSV in the simplified model; Determine a second rule instruction for describing a connection relationship and a stacking structure between the at least two bare die chips and the at least one TSV; The acquisition module is specifically used for: The first rule instruction and the second rule instruction are merged to obtain the first rule file.

12. The device according to any one of claims 9 to 11, characterized in that The at least one TSV is a plurality of TSVs, and the first netlist file further includes: a netlist statement for describing a connection relationship among the plurality of TSVs, and a TSV module for defining each of the plurality of TSVs.

13. The device according to any one of claims 9 to 12, characterized in that The acquisition module is specifically used for: Acquire interface feature information of a first bare die chip among the at least two bare die chips, wherein the interface feature information includes interface names and coordinate positions of one or more interfaces of the first bare die chip; The building blocks are specifically used for: Extracting a portion of circuit layers from the multi-layer circuit layers in the layout of the first bare die chip, wherein the portion of circuit layers includes at least a portion of the at least one TSV; A simplified model of the first bare crystal chip is constructed according to the interface feature information of the first bare crystal chip and the partial circuit layer.

14. The device according to claim 13, characterized in that The device further includes a generating module, which is used to: after the building module builds the simplified model of the first bare die chip, Determining that the partial circuit layer includes one or more disconnected wirings; A wiring plane is generated, through which the one or more disconnected wirings are connected.

15. The device according to any one of claims 9 to 14, characterized in that The building blocks are specifically used for: Obtaining a functional category of the at least one TSV; A simplified model of the at least one TSV is constructed according to the functional category of the at least one TSV.

16. The device according to claim 15, characterized in that The functional category includes a signal TSV, and the signal TSV is used to transmit a signal; The building blocks are specifically used for: When it is determined that the at least one TSV is a signal TSV, the simplified model of the at least one TSV is constructed as a two-port device model, and the two ports of the two-port device model include an input port and an output port.

17. A computer readable medium, characterized in that The computer readable medium stores a program code, and when the computer program code is executed on a computer, the computer is caused to perform the method according to any one of claims 1 to 8.

18. A computer program product, characterized in that The computer program product comprises a computer program code, which, when executed on a computer, causes the computer to perform the method according to any one of claims 1 to 8.

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