Preparation method of packaging structure and packaging structure

Abstract

The invention relates to a preparation method of a packaging structure and the packaging structure, and the preparation method of the packaging structure comprises the steps: providing a first carrier plate; an interposer structure, an interposer substrate, a wiring layer and a conductive through hole structure are formed on the first carrier plate, the wiring layer is located on the side, away from the first carrier plate, of the interposer substrate, and the conductive through hole structure penetrates through the interposer substrate and is connected with the wiring layer; forming a chip on one side, far away from the interposer substrate, of the wiring layer; forming a plastic package layer covering the chip and the interposer structure; removing the first carrier plate; and forming an external circuit module on one side of the interposer structure far away from the chip, wherein the external circuit module is connected with the chip through the interposer structure. The performance of the packaging structure can be effectively improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a method for preparing a packaging structure and a packaging structure. Background Art

[0002] For some packaging structure products, circuit structures are formed on both sides of the wiring layer, one side of the circuit structure includes a chip wrapped by a plastic packaging layer, and the other side includes an external circuit module.

[0003] For this type of product, the traditional process usually first coats an organic film layer such as polyimide (PI), and then forms each wiring layer through processes such as photolithography and copper electroplating. However, the performance of the product formed in this way is poor. Summary of the invention

[0004] Based on this, the present application provides a method for preparing a packaging structure and a packaging structure that can improve product performance.

[0005] A method for preparing a packaging structure, comprising:

[0006] providing a first carrier board;

[0007] forming an interposer structure on the first carrier, the interposer structure comprising an interposer substrate, a wiring layer and a conductive through-hole structure, the wiring layer being located on a side of the interposer substrate away from the first carrier, the conductive through-hole structure penetrating the interposer substrate and connecting the wiring layer;

[0008] forming a chip on a side of the wiring layer away from the interposer substrate;

[0009] forming a plastic packaging layer covering the chip and the interposer structure;

[0010] removing the first carrier plate;

[0011] An external circuit module is formed on a side of the interposer structure away from the chip, and the external circuit module is connected to the chip through the interposer structure.

[0012] In one embodiment, forming an interposer structure on the first carrier includes:

[0013] Providing an interposer initial structure, the interposer initial structure comprising an interposer initial sheet, a wiring layer, and a conductive initial structure, the wiring layer being located on one side of the interposer initial sheet, and the conductive initial structure extending inwardly from a side of the interposer initial sheet where the wiring layer is provided;

[0014] A first pad is formed on the wiring layer, and a side of the initial structure of the interposer where the first pad is formed is bonded to a second carrier board;

[0015] Etching a side of the interposer initial sheet away from the wiring layer to expose the conductive initial structure, and the remaining interposer initial sheet forms an interposer substrate, wherein the conductive initial structure protrudes from a surface of the interposer substrate;

[0016] forming a protective material layer covering the conductive initial structure and the interposer substrate;

[0017] Grinding the conductive initial structure and the protective material layer to grind the protruding portion of the conductive initial structure flat, and the remaining conductive initial structure forms a conductive through-hole structure, and the remaining protective material layer forms a protective layer;

[0018] forming a second pad covering the conductive through-hole structure and the protective layer to form an interposer structure, and bonding a side of the interposer structure where the second pad is formed to the first carrier;

[0019] The second carrier plate is removed.

[0020] In one embodiment, the step of forming a first pad on the wiring layer and bonding a side of the initial structure of the intermediate layer on which the first pad is formed to a second carrier board comprises:

[0021] forming a first pad on the wiring layer;

[0022] Performing a ring cutting on the structure after the first pad is formed to form a ring cutting space;

[0023] forming a first adhesive layer on the annular cut space and on a side of the initial structure of the interposer where the first pad is formed;

[0024] bonding a second carrier plate via the first adhesive layer;

[0025] Furthermore, the etching is performed on a side of the initial interposer sheet away from the wiring layer to expose the initial conductive structure, and at the same time, the first adhesive layer located in the annular space is removed by etching;

[0026] The forming of the second pad covering the conductive through-hole structure and the protective layer to form an interposer structure, and bonding the side of the interposer structure where the second pad is formed to the first carrier, comprises:

[0027] forming a second pad covering the conductive via structure and the protective layer to form an interposer structure;

[0028] forming a second adhesive layer on the annular space and on a side of the interposer structure where the second pad is formed;

[0029] The first carrier is bonded via the second adhesive layer.

[0030] In one embodiment, forming a chip on a side of the wiring layer away from the interposer substrate includes:

[0031] Mounting the chip onto the first pad;

[0032] Or, forming a chip on a side of the wiring layer away from the interposer substrate comprises:

[0033] The chip is hybrid bonded to the first pad.

[0034] In one embodiment, before forming the external circuit module on the side of the interposer structure away from the chip, the method further includes:

[0035] Forming a first fixing hole penetrating the intermediate layer structure and the plastic packaging layer;

[0036] The external circuit module is formed on a side of the interposer structure away from the chip, comprising:

[0037] Installing passive components on a portion of the second pads;

[0038] forming a first frame structure covering the passive device and another part of the second pad, wherein the first frame structure comprises a first frame and a socket located on the first frame;

[0039] forming an external plug-in on a side of the first frame structure away from the interposer structure, wherein the external plug-in is connected to the second pad through the socket;

[0040] After the external circuit module is formed on the side of the interposer structure away from the chip, the method further includes:

[0041] A fixing piece is passed through the first fixing hole to fix and install a heat sink on a side of the plastic packaging layer away from the intermediate layer structure.

[0042] A packaging structure, comprising:

[0043] An interposer structure, comprising an interposer substrate, a wiring layer and a conductive via structure, wherein the wiring layer is located on one side of the interposer substrate, and the conductive via structure penetrates the interposer substrate and connects the wiring layer;

[0044] A chip, located on a side of the wiring layer away from the interposer substrate;

[0045] A plastic packaging layer, covering the chip and the interposer structure;

[0046] The external circuit module is located at a side of the interposer structure away from the chip and is connected to the chip through the interposer structure.

[0047] In one of the embodiments, the interposer structure further includes a protective layer, the protective layer is located on a side of the interposer substrate away from the wiring layer, and the conductive via structure penetrates the protective layer and the interposer substrate.

[0048] In one of the embodiments, the interposer structure further includes a first pad, the first pad is located on the surface of the wiring layer, and the chip is mounted or hybrid bonded to the first pad.

[0049] In one embodiment, the interposer structure further includes a second pad, which is located on a side of the interposer substrate away from the wiring layer and covers the conductive through-hole structure. The packaging structure further includes a first frame structure, which includes a first frame and a socket located on the first frame.

[0050] The external circuit module comprises:

[0051] A passive component is mounted on a portion of the second pad, and the first frame structure covers the passive component and another portion of the second pad;

[0052] The external plug-in is located at a side of the first frame structure away from the interposer structure and is connected to the second pad through the socket.

[0053] In one embodiment, the interposer substrate includes a silicon wafer, and / or the packaging structure further includes:

[0054] A heat sink is located on a side of the plastic packaging layer away from the intermediate layer structure;

[0055] A first fixing hole, penetrating the intermediate layer structure and the plastic packaging layer;

[0056] A fixing member passes through the first fixing hole to fix the heat sink.

[0057] The above-mentioned packaging structure preparation method first forms an interposer structure on a first carrier. Afterwards, the first carrier can be used as a support for the interposer structure, a chip is formed on the side of the wiring layer away from the interposer substrate, and a plastic encapsulation layer is formed to cover the chip. Afterwards, the plastic encapsulation layer can be used as a support, so that the first carrier can be removed, and an external circuit module is formed on the side of the interposer structure away from the chip, so that the preparation of the packaging structure can be effectively realized.

[0058] At the same time, the packaging structure of the present application uses an interposer structure to connect the chip and the external circuit module, instead of the traditional wiring layer structure formed by coating the PI film layer and then photolithography copper plating, thereby preventing the structure from warping due to the excessive thermal expansion coefficient of the PI film layer and copper. At the same time, the interposer technology can realize a wiring layer with a high degree of integration. Therefore, connecting the chip and the external circuit module through the interposer structure can effectively improve the circuit integration density. Moreover, when the interposer structure is a silicon interposer, the heat dissipation of silicon is relatively good, thereby effectively improving the heat dissipation of the product. Therefore, the use of the present application can effectively improve the performance of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0060] Figure 1 is a flow chart of a method for preparing a packaging structure provided in an embodiment;

[0061] Figures 2 to 17 A schematic diagram of a partial cross-sectional structure of a structure obtained in each step of a method for preparing a packaging structure provided in an embodiment;

[0062] Fig.18 A schematic diagram of a partial cross-sectional structure of a packaging structure provided in an embodiment;

[0063] Fig.19 It is a schematic diagram of a partial cross-sectional structure of a first frame structure provided in one embodiment.

[0064] Description of reference numerals:

[0065] 110-first carrier, 120-second carrier, 200-intermediate layer structure, 210-intermediate layer substrate, 220-wiring layer, 230-conductive via structure, 2001-intermediate layer initial structure, 2101-intermediate layer initial sheet, 2301-conductive initial structure, 240-first pad, 250-second pad, 260-first graphic dielectric layer, 270-second graphic dielectric layer, 300-chip, 400-plastic package Layer, 500-external circuit module, 510-passive device, 520-external plug-in, 521-voltage management module, 522-connector, 600-protective layer, 6001-protective material layer, 710-first adhesive layer, 720-second adhesive layer, 730-adhesive, 740-fixing part, 800-first frame structure, 900-heat sink, 10-annular space, 20-first fixing hole, 30-second fixing hole. DETAILED DESCRIPTION

[0066] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0067] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0068] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0069] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0070] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0071] In one embodiment, see Figure 1 , a method for preparing a packaging structure is provided, comprising the following steps:

[0072] Step S10: providing a first carrier board 110 .

[0073] The first carrier plate 110 is a carrier plate that can be used for support. The material of the first carrier plate 110 can include but is not limited to a glass plate, a metal plate or a plastic plate.

[0074] In step S20, an interposer structure 200 is formed on the first carrier 110. The interposer structure 200 includes an interposer substrate 210, a wiring layer 220, and a conductive through-hole structure 230. The wiring layer 220 is located on a side of the interposer substrate 210 away from the first carrier 110. The conductive through-hole structure 230 penetrates the interposer substrate 210 and connects the wiring layer 220.

[0075] The interposer structure 200 may include but is not limited to a silicon interposer. The interposer substrate 210 may include but is not limited to a silicon wafer. The material of the conductive via structure 230 may include but is not limited to metal materials such as copper.

[0076] A plurality of interconnected wiring layers 220 may be provided on one side of the interposer substrate 210, and an insulating dielectric layer may be provided between adjacent wiring layers 220. It should be noted that only a partial structure of the wiring layer 220 is simply illustrated in the figure.

[0077] In step S30 , a chip 300 is formed on a side of the wiring layer 220 away from the interposer substrate 210 .

[0078] A plurality of chips 300 may be formed on a side of the wiring layer 220 away from the interposer substrate 210. The chips 300 may be electrically connected to the wiring layer 220. The plurality of chips 300 may be arranged at intervals. Different chips 300 may have different functions.

[0079] Step S40 , forming a plastic packaging layer 400 covering the chip 300 and the interposer structure 200 .

[0080] The plastic encapsulation layer 400 can completely cover the chip 300, thereby performing plastic encapsulation protection on the chip 300. The material of the plastic encapsulation layer 400 can include but is not limited to epoxy molding compound (EMC).

[0081] Step S50 , removing the first carrier board 110 .

[0082] The first carrier 110 may be removed by laser lift-off or the like, thereby exposing a side of the interposer structure 200 away from the chip 300 .

[0083] Step S70 , forming an external circuit module 500 on a side of the interposer structure 200 away from the chip 300 , and the external circuit module 500 is connected to the chip 300 through the interposer structure 200 .

[0084] After removing the first carrier board 110 , the structure may be turned over to facilitate forming the external circuit module 500 .

[0085] The external circuit module 500 may include a passive device 510 (IPD) and / or an external plug-in 520 , etc. The external plug-in 520 may include a voltage management module 521 and / or a connector 522 , etc.

[0086] In this embodiment, the interposer structure 200 is first formed on the first carrier 110. Afterwards, the first carrier 110 can be used as a support for the interposer structure 200, and the chip 300 is formed on the side of the wiring layer 220 away from the interposer substrate 210, and the plastic encapsulation layer 400 is formed to cover the chip 300. Afterwards, the plastic encapsulation layer 400 can be used as a support, so that the first carrier 110 can be removed, and the external circuit module 500 can be formed on the side of the interposer structure 200 away from the chip 300, so that the preparation of the packaging structure can be effectively realized.

[0087] At the same time, the packaging structure formed by the method of this embodiment uses an interposer structure 200 to connect the chip 300 and the external circuit module 500, instead of using the traditional wiring layer 220 structure formed by coating the PI film layer and then photolithography copper plating, thereby preventing the structure from warping due to the excessive thermal expansion coefficient of the PI film layer and copper. At the same time, the interposer technology can realize a wiring layer 220 with a high degree of integration. Therefore, connecting the chip 300 and the external circuit module 500 through the interposer structure 200 can effectively improve the circuit integration density. Moreover, when the interposer structure 200 is a silicon interposer, the heat dissipation of silicon is relatively good, thereby effectively improving the heat dissipation of the product. Therefore, the method of this embodiment can effectively improve the performance of the packaging structure.

[0088] In one embodiment, step S20 includes:

[0089] Step S21, providing an interposer initial structure 2001, the interposer initial structure 2001 includes an interposer initial sheet 2101, a wiring layer 220 and a conductive initial structure 2301, wherein the wiring layer 220 is located on one side of the interposer initial sheet 2101, and the conductive initial structure 2301 extends inward from the side of the interposer initial sheet 2101 where the wiring layer 220 is provided.

[0090] In the interposer initial structure 2001 , one end of the conductive initial structure 2301 may be connected to the wiring layer 220 . Meanwhile, the other end of the conductive initial structure 2301 may extend to the inside of the interposer initial sheet 2101 , but does not penetrate the interposer initial sheet 2101 .

[0091] In step S22 , a first pad 240 is formed on the wiring layer 220 , and a side of the interposer initial structure 2001 where the first pad 240 is formed is bonded to the second carrier 120 .

[0092] The material of the first pad 240 may include, but is not limited to, copper, etc. The first pad 240 may cover at least a portion of the wiring layer 220 , thereby being electrically connected to the wiring layer 220 .

[0093] After the initial interposer structure 2001 is bonded to the second carrier 120 , the second carrier 120 may serve as a support for subsequent processes.

[0094] Step S23 , etching the side of the interposer initial sheet 2101 away from the wiring layer 220 to expose the conductive initial structure 2301 , and the remaining interposer initial sheet 2101 forms the interposer substrate 210 , and the conductive initial structure 2301 protrudes from the surface of the interposer substrate 210 .

[0095] The interposer initial sheet 2101 may be etched and thinned from a side away from the wiring layer 220 by dry etching process, etc., until the thickness of the remaining interposer initial sheet 2101 (interposer substrate 210 ) is smaller than the height of the conductive initial structure 2301 .

[0096] Step S24 , forming a protective material layer 6001 covering the conductive initial structure 2301 and the interposer substrate 210 .

[0097] The protective material layer 6001 may be formed by a deposition process (such as chemical vapor deposition or atomic layer deposition, etc.). The material of the protective material layer 6001 may include but is not limited to silicon oxide, silicon nitride or silicon oxynitride, etc.

[0098] Step S25 , grinding the conductive initial structure 2301 and the protective material layer 6001 to flatten the protruding portion of the conductive initial structure 2301 , and the remaining conductive initial structure 2301 forms the conductive through-hole structure 230 , and the remaining protective material layer 6001 forms the protective layer 600 .

[0099] Before grinding, the surface of the interposer substrate 210 is covered by the protective material layer 6001. Therefore, during the grinding process, the protective material layer 6001 can prevent the metal of the conductive initial structure 2301 from entering the interposer substrate 210, thereby preventing leakage between adjacent conductive via structures 230.

[0100] In step S26 , a second pad 250 is formed to cover the conductive via structure 230 and the protection layer 600 to form the interposer structure 200 , and a side of the interposer structure 200 where the second pad 250 is formed is bonded to the first carrier 110 .

[0101] The material of the second pad 250 may include but is not limited to copper, etc. After the second pad 250 is formed, the preparation of the interposer structure 200 may be completed.

[0102] After the initial interposer structure 2001 is bonded to the first carrier 110 , the first carrier 110 and the second carrier 120 may be disposed opposite to each other.

[0103] Step S27, removing the second carrier board 120.

[0104] The second carrier 120 may be removed by laser lift-off or the like.

[0105] After the second carrier 120 is removed, the first carrier 110 can be used as a support for subsequent processes.

[0106] In this embodiment, in the interposer initial structure 2001 provided at the beginning, the conductive initial structure 2301 does not penetrate the interposer initial sheet 2101. In the subsequent process, the interposer initial sheet 2101 is formed into the interposer substrate 210 through etching, grinding and other processes, thereby effectively reducing the thickness of the interposer substrate, and then reducing the thickness of the packaging structure, thereby facilitating the improvement of the packaging integration. At the same time, at this time, in the process of forming the conductive initial structure 2301, it is also unnecessary to form a through hole penetrating the interposer initial sheet 2101, thereby reducing the process difficulty of the conductive initial structure 2301.

[0107] Furthermore, before the conductive initial structure 2301 and the protective material layer 6001 are ground, a protective material layer 6001 is formed to cover the conductive initial structure 2301 and the interposer substrate 210. Therefore, during the grinding process, the protective material layer 6001 can prevent the metal of the conductive initial structure 2301 from entering the interposer substrate 210, thereby preventing leakage between adjacent conductive via structures 230.

[0108] In one embodiment, step S22 includes:

[0109] Step S221 , forming a first pad 240 on the wiring layer 220 .

[0110] First, a first patterned dielectric layer 260 may be formed by a photolithography process, etc., and the first patterned dielectric layer 260 has a first opening. The material of the first patterned dielectric layer 260 may include, but is not limited to, PI. Then, a first patterned photoresist layer may be formed on the first dielectric layer. The first patterned photoresist layer has a second opening, and the second opening is arranged opposite to the first opening. Then, a first pad 240 may be formed in the second opening and the first opening by an electroplating process, etc., and the first patterned photoresist layer is removed.

[0111] At this time, as an example, step S30 may include: step S31, mounting the chip 300 on the first pad 240. Or, as an example, step S30 may include: step S32, hybrid bonding the chip 300 to the first pad 240.

[0112] Step S222 , performing ring cutting on the structure after the first pad 240 is formed, to form a ring cutting space 10 .

[0113] During the ring cutting, a portion of the thickness of the edge of the initial sheet 2101 of the intermediate layer can be cut off.

[0114] As an example, the depth of the cutout of the interposer initial sheet 2101 may be greater than the height of the conductive initial structure 2301 .

[0115] In step S223 , a first adhesive layer 710 is formed on the annular space 10 and the side of the initial structure 2001 of the interposer where the first pad 240 is formed.

[0116] Step S224 , bonding the second carrier 120 via the first adhesive layer 710 .

[0117] Thereafter, the first adhesive layer 710 may be cured.

[0118] The formation of the annular space 10 facilitates the initial structure of the intermediate layer 2001 to be more firmly adhered to the second carrier board 120 .

[0119] At the same time, step S23 etches the side of the initial interposer sheet 2101 away from the wiring layer 220 to expose the initial conductive structure 2301 and remove the first adhesive layer 710 located in the annular space 10. At this time, the annular space 10 can be hollowed out again.

[0120] When the cutting depth of the initial sheet 2101 of the intermediate layer in step S222 can be greater than the height of the conductive initial structure 2301, it can be ensured that step S23 can etch the initial sheet 2101 of the intermediate layer to expose the first adhesive layer in the annular space 10, and then the first adhesive layer 710 in the annular space 10 can be effectively etched and removed.

[0121] Step S26 includes:

[0122] Step S261 , forming a second pad 250 covering the conductive via structure 230 and the protection layer 600 to form the interposer structure 200 .

[0123] The second pad 250 may be formed in a similar manner to the first pad 240 .

[0124] First, a second patterned dielectric layer 270 may be formed by a photolithography process, etc., and the second patterned dielectric layer 270 has a third opening. The material of the second patterned dielectric layer 270 may include, but is not limited to, PI. Then, a second patterned photoresist layer may be formed on the second dielectric layer. The second patterned photoresist layer has a fourth opening, and the fourth opening is arranged opposite to the third opening. Then, a second pad 250 may be formed in the fourth opening and the third opening by an electroplating process, etc., and the second patterned photoresist layer is removed.

[0125] Step S262 , forming a second adhesive layer 720 on the annular space 10 and the side of the interposer structure 200 where the second pad 250 is formed;

[0126] Step S263 , bonding the first carrier 110 via the second adhesive layer 720 .

[0127] Thereafter, the second adhesive layer 720 may be cured.

[0128] At this time, the annular space 10 facilitates the initial structure of the intermediate layer 2001 to be more firmly adhered to the first carrier board 110 .

[0129] After that, the structure in the corresponding area of ​​the annular space 10 can be completely removed. Then, in step S27, the second carrier 120 is removed. In step S27, after the second carrier 120 is removed, the first adhesive layer 710 can be removed to expose the first pad 240.

[0130] Meanwhile, in the subsequent step S50 , after removing the first carrier board, the second adhesive layer 720 may be removed to expose the second pad 250 .

[0131] In this embodiment, before bonding the second carrier 120, the annular cutting space 10 is first formed, so that the initial structure of the interposer 2001 can be more firmly bonded to the second carrier 120 through the annular cutting space 10. At the same time, when the initial interposer sheet 2101 is etched and thinned to form the interposer substrate 210, the first adhesive layer 710 of the annular cutting space 10 is removed, so that the annular cutting space 10 is hollowed out again, so that the initial structure of the interposer 2001 can be more firmly bonded to the first carrier 110 through the annular cutting space 10 again.

[0132] Of course, in other embodiments, circumcision may not be performed, and the present application has no limitation to this.

[0133] In one embodiment, before step S70, the method further includes:

[0134] Step S60 , forming a first fixing hole 20 penetrating the interposer structure 200 and the plastic encapsulation layer 400 .

[0135] Step S70 includes:

[0136] Step S71 , installing the passive device 510 on a portion of the second pad 250 .

[0137] As a part of the external circuit module 500 , the passive component 510 can be directly mounted on the second pad 250 by means of surface mount mounting.

[0138] Step S72, forming a first frame structure 800 covering the passive device 510 and another part of the second pad 250, the first frame structure 800 includes a first frame 810 and a socket 820 located on the first frame 810 (see Fig.19 ).

[0139] The first frame structure 800 can seal the passive device 510 and the second pad 250 .

[0140] As an example, a mounting groove may be provided on the surface of the first frame 810, and the socket 820 may be placed in the mounting groove to position the socket.

[0141] Optionally, the first frame structure 800 may further include a conductive portion 830. The conductive portion 830 may be located in the first frame 810 and may be disposed at the bottom of the socket 820. The material of the conductive portion 830 may include, but is not limited to, conductive rubber.

[0142] In step S73 , an external plug-in 520 is formed on a side of the first frame structure 800 away from the interposer structure 200 , and the external plug-in 520 is connected to the second pad 250 through the socket 820 .

[0143] The pins of the external plug 520 may be inserted into the socket 820 , thereby being conductively connected to the second pad 250 through the socket 820 and the conductive portion 830 .

[0144] The external plug-in 520 may include but is not limited to a voltage management module 521 and / or a connector 522 , etc. The external plug-in 520 may be plugged into the first frame structure 800 in a pluggable manner, thereby connecting to the second pad 250 through the first frame structure 800 .

[0145] After step S70, the method further includes:

[0146] Step S80 , using a fixing member to pass through the first fixing hole 20 , and fixing the heat sink 900 on a side of the plastic packaging layer 400 away from the intermediate layer structure 200 .

[0147] The fixing member may include but is not limited to bolts and the like.

[0148] As an example, the heat sink 900 may be first bonded to the side of the plastic layer 400 away from the interposer structure 200 by means of adhesive 730 (such as TIM adhesive). Then, the fixing member 740 is passed through the first fixing hole 20 to fix the heat sink 900 .

[0149] After passing through the first fixing hole 20 , the fixing piece may not penetrate the heat dissipation plate 900 , or may penetrate the heat dissipation plate 900 .

[0150] In this embodiment, the connection between the heat sink 900 and the plastic packaging layer 400 can be made more reliable by the fixing member.

[0151] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0152] In one embodiment, a packaging structure is further provided, which includes an interposer structure 200 , a chip 300 , a plastic packaging layer 400 and an external circuit module 500 .

[0153] The interposer structure 200 includes an interposer substrate 210 , a wiring layer 220 , and a conductive via structure 230 .

[0154] The interposer structure 200 may include but is not limited to being a silicon interposer. The interposer substrate 210 may include but is not limited to being a silicon wafer.

[0155] The wiring layer 220 is located on one side of the interposer substrate 210. One side of the interposer substrate 210 may be provided with multiple interconnected wiring layers 220, and an insulating dielectric layer may be provided between adjacent wiring layers 220. It should be noted that the figure only simply illustrates a partial structure of the wiring layer 220.

[0156] The conductive via structure 230 penetrates the interposer substrate 210 and connects the wiring layer 220. The material of the conductive via structure 230 may include but is not limited to metal materials such as copper.

[0157] The chip 300 is located on a side of the wiring layer 220 away from the interposer substrate 210 .

[0158] A plurality of chips 300 may be disposed on a side of the wiring layer 220 away from the interposer substrate 210. The chips 300 may be electrically connected to the wiring layer 220. The plurality of chips 300 may be disposed at intervals. Different chips 300 may have different functions.

[0159] The plastic encapsulation layer 400 covers the chip 300 and the interposer structure 200, thereby performing plastic encapsulation protection on the chip 300. The material of the plastic encapsulation layer 400 may include but is not limited to epoxy molding compound (EMC).

[0160] The external circuit module 500 is located on a side of the interposer structure 200 away from the chip 300 .

[0161] The external circuit module 500 may include a passive device 510 (IPD) and / or an external plug-in 520 , etc. The external plug-in 520 may include a voltage management module 521 and / or a connector 522 , etc. The external circuit module 500 is connected to the chip 300 via the interposer structure 200 .

[0162] In this embodiment, the interposer structure 200 is used to connect the chip 300 and the external circuit module 500, instead of the traditional wiring layer 220 structure formed by coating the PI film layer and then photolithography copper plating, so as to prevent the structural warping caused by the excessive thermal expansion coefficient of the PI film layer and copper. At the same time, the interposer technology can realize a wiring layer 220 with a high degree of integration. Therefore, the circuit integration density can be effectively improved by connecting the chip 300 and the external circuit module 500 through the interposer structure 200. In addition, when the interposer structure 200 is a silicon interposer, the heat dissipation of silicon is relatively good, thereby effectively improving the heat dissipation of the product. Therefore, the method of this embodiment can effectively improve the performance of the packaging structure.

[0163] In one embodiment, the interposer structure 200 further includes a protective layer 600. The material of the protective layer 600 may include but is not limited to silicon oxide, silicon nitride or silicon oxynitride.

[0164] The protection layer 600 is located on a side of the interposer substrate 210 away from the wiring layer 220 , and the conductive via structure 230 penetrates the protection layer 600 and the interposer substrate 210 .

[0165] The protection layer 600 can prevent metal in the conductive via structure 230 from entering the interposer substrate 210 , thereby preventing leakage between adjacent conductive via structures 230 .

[0166] In one embodiment, the interposer structure 200 further includes a first pad 240. The material of the first pad 240 may include but is not limited to copper.

[0167] The first pad 240 is located on the surface of the wiring layer 220 and may cover at least a portion of the wiring layer 220 , thereby being electrically connected to the wiring layer 220 .

[0168] The chip 300 is die mounted or hybrid bonded to the first pad 240 .

[0169] In one embodiment, the interposer structure 200 further includes a second pad 250 .

[0170] The second pad 250 is located on a side of the interposer substrate 210 away from the wiring layer 220 and covers the conductive via structure 230, thereby being electrically connected to the conductive via structure 230. The material of the second pad 250 may include but is not limited to copper, etc. There may be a plurality of second pads 250.

[0171] The external circuit module 500 includes a passive component 510 and an external plug-in 520 .

[0172] The passive component 510 is mounted to a portion of the second pad 250. The passive component 510 can be directly mounted to the second pad 250 by patch mounting. At the same time, the package structure can also have another portion of the second pad 250 that is not covered by the passive component 510.

[0173] The package structure further includes a first frame structure 800. The first frame structure 800 covers the passive device 510 and another portion of the second pad 250. The first frame structure 800 includes a first frame 810 and a socket 820 located on the first frame 810.

[0174] The first frame structure 800 can seal the passive device 510 and the second pad 250 .

[0175] The external plug-in 520 is located on a side of the first frame structure 800 away from the interposer structure 200 .

[0176] The external plug-in 520 may include but is not limited to a voltage management module 521 and / or a connector 522 , etc. The external plug-in 520 may be plugged into the socket 820 in a pluggable manner, thereby connecting to the second pad 250 through the first frame structure 800 .

[0177] In one embodiment, the packaging structure further includes a heat dissipation plate 900 , a first fixing hole 20 and a fixing member.

[0178] The heat dissipation plate 900 is located on a side of the plastic encapsulation layer 400 away from the interposer structure 200. As an example, the heat dissipation plate 900 may be bonded to the plastic encapsulation layer 400 by adhesive (such as TIM adhesive).

[0179] The first fixing hole 20 passes through the intermediate layer structure 200 and the plastic packaging layer 400 .

[0180] The fixing member passes through the first fixing hole 20 to fix the heat sink 900. The fixing member may include but is not limited to bolts and the like.

[0181] After passing through the first fixing hole 20 , the fixing piece may not penetrate the heat dissipation plate 900 , or may penetrate the heat dissipation plate 900 .

[0182] As an example, the packaging structure may further include a first frame structure 800 and a second frame structure, etc.

[0183] The first frame structure 800 may include a first frame 810 and a socket 820 , etc. The external circuit module 500 may be located at a side of the first frame structure 800 away from the interposer structure 200 .

[0184] The second frame structure (not shown) may be located at a side of the external circuit module 500 away from the interposer structure 200 for mechanical fixing and limiting.

[0185] The first frame structure 800 may also have a second fixing hole 30. The second frame structure may also have a third fixing hole. The second fixing hole and the third fixing hole may be arranged opposite to the first fixing hole 20. The fixing member may also pass through the second fixing hole and the third fixing hole at the same time, so as to fix the second frame structure and the first frame structure 800 at the same time.

[0186] In this embodiment, the connection between the heat sink 900 and the plastic packaging layer 400 can be made more reliable by the fixing member.

[0187] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0188] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0189] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a packaging structure, characterized in that: include: providing a first carrier board; forming an interposer structure on the first carrier, the interposer structure comprising an interposer substrate, a wiring layer and a conductive through-hole structure, the wiring layer being located on a side of the interposer substrate away from the first carrier, the conductive through-hole structure penetrating the interposer substrate and connecting the wiring layer; forming a chip on a side of the wiring layer away from the interposer substrate; forming a plastic packaging layer covering the chip and the interposer structure; removing the first carrier plate; An external circuit module is formed on a side of the interposer structure away from the chip, and the external circuit module is connected to the chip through the interposer structure.

2. The method for preparing a packaging structure according to claim 1, characterized in that: The step of forming an interposer structure on the first carrier includes: Providing an interposer initial structure, the interposer initial structure comprising an interposer initial sheet, a wiring layer, and a conductive initial structure, the wiring layer being located on one side of the interposer initial sheet, and the conductive initial structure extending inwardly from a side of the interposer initial sheet where the wiring layer is provided; A first pad is formed on the wiring layer, and a side of the initial structure of the interposer where the first pad is formed is bonded to a second carrier board; Etching a side of the interposer initial sheet away from the wiring layer to expose the conductive initial structure, and the remaining interposer initial sheet forms an interposer substrate, wherein the conductive initial structure protrudes from a surface of the interposer substrate; forming a protective material layer covering the conductive initial structure and the interposer substrate; Grinding the conductive initial structure and the protective material layer to grind the protruding portion of the conductive initial structure flat, and the remaining conductive initial structure forms a conductive through-hole structure, and the remaining protective material layer forms a protective layer; forming a second pad covering the conductive through-hole structure and the protective layer to form an interposer structure, and bonding a side of the interposer structure where the second pad is formed to the first carrier; The second carrier plate is removed.

3. The method for preparing a packaging structure according to claim 2, characterized in that: The method of forming a first pad on the wiring layer and bonding a side of the initial structure of the intermediate layer where the first pad is formed to a second carrier board comprises: forming a first pad on the wiring layer; Performing a ring cutting on the structure after the first pad is formed to form a ring cutting space; forming a first adhesive layer on the annular cut space and on a side of the initial structure of the interposer where the first pad is formed; bonding a second carrier plate via the first adhesive layer; Furthermore, the etching is performed on a side of the initial interposer sheet away from the wiring layer to expose the initial conductive structure, and at the same time, the first adhesive layer located in the annular space is removed by etching; The forming of the second pad covering the conductive through-hole structure and the protective layer to form an interposer structure, and bonding the side of the interposer structure where the second pad is formed to the first carrier, comprises: forming a second pad covering the conductive via structure and the protective layer to form an interposer structure; forming a second adhesive layer on the annular space and on a side of the interposer structure where the second pad is formed; The first carrier is bonded via the second adhesive layer.

4. The method for preparing a packaging structure according to claim 2, characterized in that: The chip is formed on a side of the wiring layer away from the interposer substrate, comprising: Mounting the chip onto the first pad; Or, forming a chip on a side of the wiring layer away from the interposer substrate comprises: The chip is hybrid bonded to the first pad.

5. The method for preparing a packaging structure according to claim 2, characterized in that: Before forming an external circuit module on a side of the interposer structure away from the chip, the method further includes: Forming a first fixing hole penetrating the intermediate layer structure and the plastic packaging layer; The external circuit module is formed on a side of the interposer structure away from the chip, comprising: Installing passive components on a portion of the second pads; forming a first frame structure covering the passive device and another part of the second pad, wherein the first frame structure comprises a first frame and a socket located on the first frame; forming an external plug-in on a side of the first frame structure away from the interposer structure, wherein the external plug-in is connected to the second pad through the socket; After the external circuit module is formed on the side of the interposer structure away from the chip, the method further includes: A fixing piece is passed through the first fixing hole to fix and install a heat sink on a side of the plastic packaging layer away from the intermediate layer structure.

6. A packaging structure, characterized in that: include: An interposer structure, comprising an interposer substrate, a wiring layer and a conductive through-hole structure, wherein the wiring layer is located on one side of the interposer substrate, and the conductive through-hole structure penetrates the interposer substrate and connects the wiring layer; A chip, located on a side of the wiring layer away from the interposer substrate; A plastic packaging layer, covering the chip and the interposer structure; The external circuit module is located at a side of the interposer structure away from the chip and is connected to the chip through the interposer structure.

7. The packaging structure according to claim 6, characterized in that: The interposer structure further includes a protection layer, which is located on a side of the interposer substrate away from the wiring layer, and the conductive via structure penetrates the protection layer and the interposer substrate.

8. The packaging structure according to claim 6, characterized in that: The interposer structure further includes a first pad, which is located on the surface of the wiring layer, and the chip is mounted or hybrid-bonded to the first pad.

9. The packaging structure according to claim 6, characterized in that: The interposer structure further includes a second pad, which is located on a side of the interposer substrate away from the wiring layer and covers the conductive through-hole structure. The packaging structure further includes a first frame structure, which includes a first frame and a socket located on the first frame. The external circuit module comprises: A passive component is mounted on a portion of the second pad, and the first frame structure covers the passive component and another portion of the second pad; The external plug-in is located at a side of the first frame structure away from the interposer structure and is connected to the second pad through the socket.

10. The packaging structure according to claim 6, characterized in that: The interposer substrate includes a silicon wafer, and / or the packaging structure further includes: A heat sink is located on a side of the plastic packaging layer away from the intermediate layer structure; A first fixing hole, penetrating the intermediate layer structure and the plastic packaging layer; A fixing member passes through the first fixing hole to fix the heat sink.

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