Logic gate

Abstract

A logic gate including a semiconductor device is provided. The semiconductor device includes a charge reservoir disposed between a first charge-accepting layer and a second charge-accepting layer. The first charge accepting layer defines a first current flow path connected at one end to the common output contact and at the other end to the drive contact. The second charge accepting layer defines a current flow path connected at one end to the common output contact and at the other end to the ground contact. The charge repository includes a potential well having a lowest energy state of mobile charge carriers at an energy lower than that of the lowest energy state of mobile charge carriers of both the first and second charge accepting layers. The logic gate further includes a control gate and a ground electrode separated from the charge accepting layer by a non-conductive layer. The control gate and the ground electrode are configured to apply an input voltage across the semiconductor device such that mobile charge carriers confined within the charge repository are transferred to the first charge accepting layer at a first applied input voltage and to the second charge accepting layer at a second applied input voltage.

Description

Technical Field

[0001] The present invention relates to logic gates, and more particularly to digital logic gates for use in digital circuits. Background Art

[0002] Logic gates are devices that serve as building blocks for digital circuits and perform the basic logic functions that are essential to these digital circuits. Digital computing is based on CMOS (complementary metal oxide semiconductor) logic gates, which consist of pairs of devices (transistors or switches) that exhibit complementary behavior in use. That is, in use, when one of the pair is on, the other of the pair is off, and vice versa. In all known CMOS logic gate configurations, this is achieved by having one of the pair be an n-type semiconductor (nMOS) and the other be a p-type semiconductor (pMOS).

[0003] refer to Figure 1 Discuss the principles of traditional CMOS gates, Figure 1 The simplest conventional logic gate, the NOT gate, is shown. Figure 1 The NOT gate 1 is composed of p-MOS10 and n-MOS20 connected in series. During the entire operation, the high drive voltage V DD (e.g. +2.5V) is applied to gate 1, and the input voltage V IN Can be applied to gate 1 to control the behavior of pMOS 10 and nMOS 20 .

[0004] For example, when the input voltage V IN When high, a high resistance is generated on pMOS10 and a low resistance is generated on nMOS20. This prevents current from flowing through pMOS10, which means that all drive voltages V DD drops on pMOS10, and the output voltage V OUT is 0.

[0005] On the contrary, at the input voltage V IN When the voltage is low, a low resistance is generated across pMOS10 and a high resistance is generated across nMOS20. This allows current to flow through pMOS10, indicating that all drive voltages V DD The output voltage V OUT was identified.

[0006] The end result is that when the input voltage V IN When high, the output voltage V OUT is low, when the input voltage V IN When it is low, the output voltage V OUTis high, and the arrangement relies on paired devices with a single requirement that, given the same input, when one is in a high resistance state, the other is in a low resistance state, and vice versa. This same principle is used to build other logic gates, such as AND, NAND, OR, and NOR gates.

[0007] Since one of the pMOS and nMOS is always in the "off" state, CMOS logic gates consume a lot of power only momentarily during the switching between the "on" and "off" states. Therefore, CMOS devices are often preferred over other forms of logic because they do not generate as much waste heat. Summary of the invention

[0008] However, the inventors have realised that in addition to the advantages achieved with CMOS logic gates, other advantages may be realised. An improved logic device has now been devised which overcomes or substantially mitigates the disadvantages associated with the prior art.

[0009] According to a first aspect of the present invention, there is provided a logic gate comprising a semiconductor device, the semiconductor device comprising a charge storage reservoir arranged between a first charge accepting layer and a second charge accepting layer, the first charge accepting layer defining a first current flow path, one end of the first current flow path being connected to a common output contact and the other end being connected to a drive contact, and the second charge accepting layer defining a current flow path, one end of the current flow path being connected to the common output contact and the other end being connected to a ground contact, the charge storage reservoir comprising a potential well having a lowest energy state of mobile charge carriers, the lowest energy state being at an energy lower than the energy of the lowest energy state of mobile charge carriers of both the first charge accepting layer and the second charge accepting layer, the logic gate further comprising a control gate and a ground electrode separated from the charge accepting layers by a non-conductive layer, the control gate and the ground electrode being configured to apply an input voltage across the semiconductor device so that mobile charge carriers confined within the charge storage reservoir are transferred to the first charge accepting layer under a first applied input voltage and are transferred to the second charge accepting layer under a second applied input voltage.

[0010] At the first applied input voltage, the lowest energy state of the mobile charge carriers of the first charge accepting layer may be lower than the lowest energy state of the mobile charge carriers of both the charge reservoir and the second charge accepting layer.

[0011] At the second applied input voltage, the lowest energy state of the mobile charge carriers of the second charge accepting layer may be lower than the lowest energy state of the mobile charge carriers of both the charge reservoir and the first charge accepting layer.

[0012] An advantage of the present invention is that the logic gate according to the present invention reduces the number of devices required to implement a digital logic gate. For example, as described above, relative to the simplest conventional logic gate, the NOT gate, the logic gate according to the present invention requires half the number of devices required for a conventional CMOS gate. Where a conventional CMOS gate requires one nMOS device and one pMOS device, the logic gate according to the present invention provides a first charge accepting layer of a pMOS that effectively acts as a conventional CMOS gate, and a second charge accepting layer of an nMOS that effectively acts as a conventional CMOS NOT gate. This makes the logic gate of the present invention, and any circuit that includes the logic gate of the present invention, more compact.

[0013] The advantage of the present invention is also that the logic gate of the present invention operates symmetrically. That is, the application of the first applied input voltage has a first effect on the transmission of mobile charge carriers, and the application of the second applied input voltage has an equal and opposite effect on the transmission of mobile charge carriers. In contrast, in traditional CMOS gates, it is difficult to implement nMOS and pMOS with equivalent but opposite characteristics. The root cause of this situation is believed to be that electrons are easier to move than holes, because the movement of holes actually requires the lack of movement of electrons. Therefore, the performance of pMOS in traditional CMOS is not as good as that of nMOS, and the logic gate is generally limited to the performance of pMOS. In contrast, the logic gate of the present invention only requires one type of charge carrier. This problem is alleviated when these charge carriers are electrons.

[0014] It is also believed that the present invention is beneficial for reducing power consumption. The main source of power consumption in traditional CMOS logic gates is due to the fact that both nMOS and pMOS are momentarily in the "on" state when the input voltage is switched, that is, when switching between a first applied input voltage and a second applied input voltage. However, due to the high speed of modern digital logic circuits, the input voltage switches so frequently that a large amount of power is consumed over time. In contrast, simulations of logic gates according to the present invention show that power consumption is reduced because there is no applied input voltage for which both charge accepting layers are conductive at the same time, i.e., in the "on" state. In particular, simulations of logic gates according to the present invention show that there is no applied input voltage for which there are enough mobile charge carriers in both of the two accepting layers to enable them to fully conduct electricity at the same time, i.e., in the "on" state.

[0015] The logic gate may include a substrate layer. The semiconductor device may be grown on the substrate layer.

[0016] The first charge accepting layer, the second charge accepting layer and the charge storage reservoir may form an active layer. The control gate may be disposed on a first outer surface of the active layer. The ground electrode may be disposed on a second outer surface of the active layer. The first and second outer surfaces may be different surfaces. The first and second outer surfaces may be opposite surfaces of the active layer. For example, the control gate may be disposed on the top surface of the active layer, and the ground electrode may be disposed on the bottom surface of the active layer.

[0017] Alternatively, the semiconductor device may include one or more additional layers arranged between the active layer and the control gate and / or ground electrode.

[0018] For example, the control gate can be separated from the first charge accepting layer by a first external charge barrier disposed on the outer surface of the first charge accepting layer, i.e., disposed on the side of the first charge accepting layer opposite to the charge storage reservoir. In addition, the ground electrode can be separated from the second charge accepting layer by a second external charge barrier disposed on the outer surface of the second charge accepting layer, i.e., disposed on the side of the second charge accepting layer opposite to the charge storage reservoir. Therefore, the external charge barrier can be referred to as a non-conductive layer, or even an insulating layer. In the case where the logic gate further includes a substrate layer, the second external charge barrier can be disposed between the second charge accepting layer and the substrate.

[0019] In this arrangement, the control gate can be arranged on the outer surface of the first external charge barrier, that is, on the side of the first external charge barrier opposite to the first charge accepting layer, and the ground electrode can be arranged on the outer surface of the second external charge barrier, for example, between the second external charge barrier and the substrate.

[0020] An input voltage may be applied to each of the charge reservoir, the first charge accepting layer, and the second charge accepting layer.

[0021] The drive contact and the ground contact can be used to apply a drive voltage to the device. The drive voltage can be applied to each of the charge storage reservoir, the first charge accepting layer and the second charge accepting layer. The drive voltage can be a constant voltage.

[0022] The common output contact can be used to provide an output voltage. The output voltage can depend on the conductivity of the first charge accepting layer and the second charge accepting layer. Since the conductivity of the first charge accepting layer and the second charge accepting layer depends on the presence of mobile charge carriers in these layers, and the presence of mobile charge carriers in these layers depends on the input voltage, the output voltage may depend on the input voltage. Therefore, the output voltage can be controlled by controlling the input voltage.

[0023] Some or all of the control grid, ground electrode, common output contact, drive contact and ground contact may be connected to other parts of the device, such as another part of the integrated circuit, ground or another logic gate. Such connection may enable the drive voltage to be applied to the logic gate via the drive contact, and / or enable the input voltage to be applied to the logic gate via the control grid. This may also enable the output voltage to be output from the logic gate via the common output contact. In other words, any one of the drive voltage, input voltage and output voltage may be provided by or provided to an external source.

[0024] Some or all of the control grid, ground electrode, common output contact, drive contact and ground contact can be made of metal material. Alternatively, some or all of the control grid, ground electrode, common output contact, drive contact and ground contact can be formed by semiconductor material. For example, the control grid can be formed by a conductive layer arranged between the first charge acceptance layer and the first outer surface of the semiconductor device. Similarly, the ground electrode can be formed by a conductive layer arranged between the second charge acceptance layer and the second outer surface. This arrangement may be advantageous in a variety of embodiments because it can reduce the distance between the control grid and the ground electrode in use, thereby increasing the electric field for a given input voltage, and can also provide a common ground electrode for multiple devices integrated on the same chip, and different input voltages can be applied to the common ground electrode. Although not required, the common output contact and / or the drive contact and / or the ground contact can be n-doped or p-doped.

[0025] The charge reservoir may be doped. The charge reservoir may be doped before the input voltage is applied. This may induce charge carriers in the charge reservoir. The semiconductor device may be configured so that in the absence of the input voltage, those induced charge carriers remain in the charge reservoir. Optionally, the first charge accepting layer and the second charge accepting layer may also be doped, and the charge reservoir may be doped to different degrees, such as a greater or lesser degree. Again, this may induce charge carriers in the charge reservoir. The semiconductor device may be configured so that in the absence of the input voltage, those induced charge carriers remain in the charge reservoir.

[0026] The semiconductor device may include a heterostructure. The semiconductor device may have a heterojunction at the interface between the first charge accepting layer and the charge storage reservoir. The semiconductor device may have a heterojunction at the interface between the charge storage reservoir and the second charge accepting layer. The potential well of the charge storage reservoir may include a quantum well. The quantum well of the charge storage reservoir may be defined between the first charge accepting layer and the second charge accepting layer. The quantum well of the charge storage reservoir may be formed by a charge storage reservoir having an offset conduction band and / or valence band to form a heterojunction at the interface between the charge storage reservoir and the first charge accepting layer and / or between the charge storage reservoir and the second charge accepting layer. For example, the charge storage reservoir may have a conduction band minimum energy lower than the conduction band minimum energy of the first charge accepting layer and the conduction band minimum energy of the second semiconductor layer, thereby forming a quantum well.

[0027] The offset conduction band and / or valence band of the charge reservoir can be achieved by selecting different semiconductors for adjacent layers, thereby defining quantum wells in the conduction band and / or valence band. That is, the offset conduction band and / or valence band of the charge reservoir can be achieved by forming the charge reservoir with a semiconductor different from the semiconductor used to form the first charge accepting layer and the second semiconductor layer. In the case where the first charge accepting layer and / or the second charge accepting layer include more than one semiconductor, the offset conduction band and / or valence band of the charge reservoir can be achieved by forming the charge reservoir with a semiconductor different from the semiconductor used in the adjacent layers of the first charge accepting layer and / or the second semiconductor layer.

[0028] Thus, the charge reservoir can be formed of a narrower bandgap semiconductor arranged between two wider bandgap semiconductors, thereby providing a heterojunction structure. That is, the charge reservoir can be formed of a narrower bandgap semiconductor, and the adjacent first charge accepting layer and second charge accepting layer can be formed of a wider bandgap semiconductor. "Bandgap" refers to the energy gap between the valence band and the conduction band of a semiconductor.

[0029] The semiconductor of the charge reservoir and the semiconductor of the first charge accepting layer and the second charge accepting layer can be formed by any semiconductor that provides the required barrier, such as the required heterojunction. For example, the semiconductor can include a Group IV semiconductor such as Si, or an alloy of a Group IV semiconductor such as SiGe, or the semiconductor can include a Group II-VI semiconductor and its alloy, or the semiconductor can include other materials, such as known 2D materials. In a currently preferred embodiment, the semiconductor includes a Group III-V semiconductor or an alloy of a Group III-V semiconductor. For example, the charge reservoir can be formed of gallium arsenide (GaAs), and the first and / or second charge accepting layer can be formed of aluminum gallium arsenide (AlGaAs). Alternatively, the charge reservoir can be formed of indium arsenide (InAs), and the first and / or second charge accepting layer can be formed of indium gallium arsenide (InGaAs).

[0030] In addition, the charge reservoir and the first and / or second charge accepting layer can be formed by the same semiconductor material, and the required potential barrier can be provided by changing any constituent element of the semiconductor material. For example, the charge reservoir and the first charge accepting layer and the second charge accepting layer can all be formed by AlGaAs, and the Al fraction in the charge reservoir can be lower than the Al fraction in the first charge accepting layer and the second charge accepting layer. Alternatively, the charge reservoir and the first charge accepting layer and the second charge accepting layer can all be formed by InGaAs, and the Ga fraction in the charge reservoir can be lower than the Ga fraction in the first charge accepting layer and the second charge accepting layer.

[0031] The quantum well of the charge reservoir may have discrete internal energy levels for accommodating mobile charge carriers in the charge reservoir. The discrete energy levels of the charge reservoir may correspond to one or more confined internal states into which (and out of which) mobile charge carriers may enter.

[0032] The lowest energy state in which mobile charge carriers can reside in the conduction band of the first charge accepting layer and / or the second charge accepting layer can have an energy higher than the lowest discrete energy level of the charge storage reservoir. The first charge accepting layer and / or the second charge accepting layer can therefore be not occupied by mobile charge carriers in the absence of an input voltage, i.e., in the absence of a zero applied bias or a zero applied electric field. Therefore, in the absence of an input voltage, the first charge accepting layer and / or the second charge accepting layer can provide a high resistance to electric current. Therefore, in the absence of an input voltage, the first charge accepting layer and / or the second charge accepting layer can be non-conductive, i.e., insulating.

[0033] The application of an input voltage across a semiconductor device can change any one or any combination of a charge reservoir, a first charge accepting layer, and a second charge accepting layer. The shape and / or size of the conduction band of any one or any combination of the third charge reservoir, the first charge accepting layer, and the second charge accepting layer can be modified. Alternatively or additionally, the Fermi level of the logic gate can be modified. For example, the conduction band of any one or any combination of the charge reservoir, the first charge accepting layer, and the second charge accepting layer can become tilted across the applied electric field. Specifically, the increase or decrease in the conduction band height across any of these layers can be proportional to the distance across the applied electric field.

[0034] In response to the application of the first applied input voltage, the lowest energy state of at least a portion of the charge storage reservoir can have an energy higher than the conduction band minimum energy of at least a portion of the first charge accepting layer. In response to the application of the first applied input voltage, at least a portion of the conduction band minimum energy of the first charge accepting layer can have an energy lower than the Fermi energy of the first charge accepting layer. Therefore, in response to the application of the first applied input voltage, mobile charge carriers can flow from the charge storage reservoir into the first charge accepting layer.

[0035] The first charge accepting layer can thus be occupied by mobile charge carriers in response to the application of the first applied input voltage. Thus, the first charge accepting layer can provide a low resistance to current in response to the application of the first applied input voltage. Thus, the first charge accepting layer can become conductive in response to the application of the first applied input voltage.

[0036] Thus, in response to application of the first applied input voltage, the number of mobile charge carriers in the charge reservoir may decrease. Thus, in response to application of the first applied input voltage, the charge reservoir may become unpopulated by mobile charge carriers.

[0037] In response to the application of the first applied input voltage, the lowest energy state of the charge reservoir can have an energy lower than the conduction band minimum energy of the second charge accepting layer. In response to the application of the first applied input voltage, the conduction band minimum energy of the second charge accepting layer can have an energy higher than the Fermi energy of the second charge accepting layer.

[0038] Therefore, the second charge accepting layer can remain free of mobile charge carriers, i.e., mobile charge carriers will not flow from the charge reservoir into the second charge accepting layer in response to the application of the first applied input voltage. Therefore, in response to the application of the first applied input voltage, the second charge accepting layer can remain unoccupied by mobile charge carriers. Therefore, the second charge accepting layer can continue to provide high resistance to current in response to the application of the first applied input voltage. Therefore, in response to the application of the first applied input voltage, the second charge accepting layer can remain non-conductive, i.e., insulating.

[0039] In response to the application of the second applied input voltage, the lowest energy state of at least a portion of the charge storage reservoir can have an energy higher than the conduction band minimum energy of at least a portion of the second charge accepting layer. In response to the application of the second applied bias, at least a portion of the conduction band minimum energy of the second charge accepting layer can have an energy lower than the Fermi energy of the second charge accepting layer. Therefore, in response to the application of the second applied input voltage, mobile charge carriers can flow from the charge storage reservoir into the second charge accepting layer.

[0040] The second charge accepting layer can thus be occupied by mobile charge carriers in response to the application of the second applied input voltage. Therefore, the second charge accepting layer can provide low resistance to current in response to the application of the second applied input voltage. Therefore, the second charge accepting layer can become conductive in response to the application of the second applied input voltage.

[0041] Thus, in response to application of the second applied input voltage, the number of mobile charge carriers in the charge reservoir may decrease. Thus, in response to application of the second applied input voltage, the charge reservoir may become unpopulated by mobile charge carriers.

[0042] In response to the application of the second applied input voltage, the lowest energy state of the charge reservoir can have an energy lower than the conduction band minimum energy of the first charge accepting layer. In response to the application of the second applied input voltage, the conduction band minimum energy of the first charge accepting layer can have an energy higher than the Fermi energy of the first charge accepting layer.

[0043] Therefore, the first charge accepting layer can remain free of mobile charge carriers, that is, in response to the application of the second applied input voltage, mobile charge carriers may not flow from the charge reservoir into the first charge accepting layer. Therefore, in response to the application of the second applied input voltage, the first charge accepting layer can remain unoccupied by mobile charge carriers. Therefore, the first charge accepting layer can continue to provide high resistance to current in response to the application of the second applied input voltage. Therefore, in response to the application of the second applied input voltage, the first charge accepting layer can remain non-conductive, i.e., insulating.

[0044] The mobile charge carriers may be electrons or holes. In the case where the mobile charge carriers are electrons, the first applied input voltage may be a positive applied input voltage and the second applied input voltage may be a negative applied input voltage. Alternatively, the first applied input voltage may be a positive applied input voltage and the second applied input voltage may be a smaller positive applied input voltage. This may be the case, for example, where a positive input voltage is applied in a stationary state, i.e., a potential well of a charge reservoir is created. Further optionally, the second applied input voltage may be a negative applied input voltage and the first applied input voltage may be a smaller negative applied input voltage. This may be the case, for example, where a negative input voltage is applied in a stationary state, i.e., a potential well of a charge reservoir is created.

[0045] In the case where the mobile charge carriers are holes, the first applied input voltage may be a negative applied input voltage and the second applied input voltage may be a positive applied input voltage. Alternatively, the first applied input voltage may be a negative applied input voltage and the second applied bias voltage may be a smaller negative applied input voltage. This may be the case, for example, where a negative input voltage is applied in a stationary state, i.e., a potential well of a charge reservoir is created. Further optionally, the second applied input voltage may be a positive applied input voltage and the first applied input voltage may be a smaller positive applied input voltage. This may be the case, for example, where a positive input voltage is applied in a stationary state, i.e., a potential well of a charge reservoir is created.

[0046] The semiconductor device may also have a heterojunction at the interface between the first external charge barrier and the first charge accepting layer, and / or at the interface between the second charge accepting layer and the second external charge barrier. The external charge barrier may be formed of an insulator or semiconductor material, which defines a suitably large potential barrier relative to the first charge accepting layer and the second charge accepting layer, respectively. The external charge barrier may be formed of a dielectric material. The external charge barrier may be formed of a semiconductor material. The semiconductor may be an undoped semiconductor material. The external charge barrier may be formed of a III-V semiconductor material, such as aluminum arsenide (AlAs), or of a suitable oxide, such as silicon dioxide (SiO 2 ) or aluminum oxide (Al 2 O 3 ).

[0047] In an alternative embodiment, the semiconductor device may further include a first internal charge barrier disposed between the first charge accepting layer and the charge reservoir, and / or a second internal charge barrier disposed between the charge reservoir and the second charge accepting layer. The semiconductor device may have a heterojunction at an interface between any one or any combination of the first charge accepting layer and the first internal charge barrier, the first internal charge barrier and the charge reservoir, the charge reservoir and the second internal charge barrier, the second internal charge barrier and the second charge accepting layer. In this arrangement, the quantum well of the charge reservoir may be defined between the first internal charge barrier and the second internal charge barrier.

[0048] The internal charge barrier can be a charge trapping barrier, such as those known in U.S. Patent 10243086. In particular, the internal charge barrier can be formed as a potential barrier that prevents the passage of mobile charge carriers between the charge reservoir and the first charge accepting layer and / or between the charge reservoir and the second charge accepting layer. The internal charge barrier can be a resonant tunnel barrier. These features may be advantageous because the influence of the applied bias still exists even if the input voltage is no longer applied. For example, in the case where the first input voltage has been applied and the mobile charge carriers have moved to the first charge accepting layer, once the first applied input voltage is stopped, at least some of the mobile charge carriers will remain in the first charge accepting layer, and therefore the first charge accepting layer will remain conductive. Similarly, in the case where the second input voltage has been applied and the mobile charge carriers have moved to the second charge accepting layer, once the second applied input voltage is stopped, at least some of the mobile charge carriers will remain in the second charge accepting layer, and therefore the second charge accepting layer will remain conductive. This reduces the energy consumption of the logic gate and allows it to operate as a combined memory and logic device.

[0049] In this arrangement, the first charge accepting layer may also include a potential well, such as a quantum well, i.e., in addition to the quantum well of the charge storage reservoir. The quantum well of the first charge accepting layer may be defined between the first external charge barrier and the first internal charge barrier. The quantum well of the first charge accepting layer may be formed by the first charge accepting layer having an offset conduction band and / or valence band to form a heterojunction at the interface between the first charge accepting layer and the first external charge barrier and / or between the first charge accepting layer and the first internal charge barrier. For example, the first charge accepting layer may have a minimum energy state of mobile charge carriers that is lower than the conduction band minimum energy of the first external charge barrier and the conduction band minimum energy of the first internal charge barrier, thereby forming a quantum well.

[0050] In this arrangement, the second charge accepting layer may also include a potential well, such as a quantum well, i.e., in addition to the quantum well of the charge storage reservoir. The quantum well of the second charge accepting layer may be confined between the second external charge barrier and the second internal charge barrier. The quantum well of the second charge accepting layer may be formed by a second charge accepting layer having an offset conduction band and / or valence band, to form a heterojunction at the interface between the second charge accepting layer and the second external charge barrier and / or between the second charge accepting layer and the second internal charge barrier. For example, the second charge accepting layer may have a minimum energy state of mobile charge carriers that is lower than the conduction band minimum energy of the second external charge barrier and the conduction band minimum energy of the second internal charge barrier, thereby forming a quantum well.

[0051] The quantum well of the first charge accepting layer and / or the second charge accepting layer can be formed by the first charge accepting layer and / or the second charge accepting layer having an offset conduction band and / or valence band to form a heterojunction at the interface between those charge accepting layers and their respective potential barriers. The offset conduction band and / or valence band of the first charge accepting layer and / or the second charge accepting layer can be achieved by selecting different semiconductors for adjacent layers, thereby defining the quantum well in the conduction band and / or the valence band. That is, the offset conduction band and / or valence band of the first charge accepting layer and / or the second charge accepting layer can be achieved by forming the first charge accepting layer and / or the second charge accepting layer with a semiconductor different from the semiconductor used to form the adjacent charge barrier. In the case where the adjacent charge barrier includes more than one semiconductor, the offset conduction band and / or valence band of the first charge accepting layer and / or the second charge accepting layer can be achieved by forming the first charge accepting layer and / or the second charge accepting layer with a semiconductor different from the semiconductor used in the adjacent layer of the adjacent barrier.

[0052] Therefore, the first charge accepting layer and / or the second charge accepting layer can be formed by a narrower bandgap semiconductor arranged between two wider bandgap semiconductors, thereby providing a heterojunction structure. That is, the first charge accepting layer and / or the second charge accepting layer can be formed by a narrower bandgap semiconductor, and the adjacent charge barrier can be formed by a wider bandgap semiconductor. "Bandgap" refers to the energy gap between the valence band and the conduction band of a semiconductor.

[0053] The semiconductor of the first charge-accepting layer and / or the second semiconductor layer as well as the semiconductor of the charge barrier may be formed of any semiconductor that provides the required barrier, such as the required heterojunction.

[0054] The quantum well of the first charge accepting layer and / or the quantum well of the second charge accepting layer can have discrete internal energy levels for accommodating mobile charge carriers in these layers. The discrete energy levels of these layers can correspond to one or more confined internal states that mobile charge carriers can enter (and leave) the internal state.

[0055] The minimum energy state of the first charge accepting layer and / or the minimum energy state of the second charge accepting layer can have higher energy than the minimum energy state of the charge storage reservoir. The first charge accepting layer and / or the second charge accepting layer can therefore not be occupied by mobile charge carriers when no input voltage is applied, i.e., when zero bias is applied. Therefore, in the case where no input voltage is applied, the first charge accepting layer and / or the second charge accepting layer can provide high resistance to electric current. Therefore, in the case where no input voltage is applied, the first charge accepting layer and / or the second charge accepting layer can be non-conductive, i.e., insulating.

[0056] Applying an input voltage across a logic gate can modify any one or any combination of a charge reservoir, a first charge accepting layer, a second charge accepting layer, a first internal charge barrier, and a second internal charge barrier. The shape and / or size of the conduction band of any one or any combination of a charge reservoir, a first charge accepting layer, a second charge accepting layer, a first internal charge barrier, and a second internal charge barrier can be modified. Alternatively or additionally, the Fermi level of the logic gate can be modified. For example, the conduction band of any one or any combination of a charge reservoir, a first charge accepting layer, a second charge accepting layer, a first internal charge barrier, and a second internal charge barrier can become tilted across the applied electric field. Specifically, the increase or decrease in the conduction band height across any of these layers can be proportional to the distance across the applied electric field.

[0057] In response to the application of the first applied input voltage, the lowest energy state of the charge reservoir can have a higher energy than the lowest energy state of the first charge accepting layer. In response to the application of the first applied input voltage, at least a portion of the lowest energy state of the first charge accepting layer can have an energy lower than the Fermi energy of the first charge accepting layer. Therefore, in response to the application of the first applied input voltage, mobile charge carriers can flow from the charge reservoir into the first charge accepting layer.

[0058] The first charge accepting layer can thus be occupied in response to the application of the first applied input voltage. Thus, the first charge accepting layer can provide a low resistance to current in response to the application of the first applied input voltage. Thus, the first charge accepting layer can become conductive in response to the application of the first applied input voltage.

[0059] Thus, the number of mobile charge carriers in the charge reservoir may decrease with application of the first applied input voltage.Thus, in response to application of the first applied input voltage, the charge reservoir may become unpopulated by mobile charge carriers.

[0060] In response to the application of the first applied input voltage, the lowest energy state of the charge reservoir can have a lower energy than the lowest energy state of the second charge accepting layer. In response to the application of the first applied input voltage, the lowest energy state of the second charge accepting layer can have an energy higher than the Fermi energy of the second charge accepting layer.

[0061] Therefore, the second charge accepting layer can remain free of mobile charge carriers, i.e., mobile charge carriers will not flow from the charge reservoir into the second charge accepting layer in response to the application of the first applied input voltage. Therefore, in response to the application of the first applied input voltage, the second charge accepting layer can remain unoccupied by mobile charge carriers. Therefore, the second charge accepting layer can continue to provide high resistance to current in response to the application of the first applied input voltage. Therefore, in response to the application of the first applied input voltage, the second charge accepting layer can remain non-conductive, i.e., insulating.

[0062] In response to the application of the second applied input voltage, the lowest energy state of the charge reservoir can have an energy higher than the lowest energy state of the second charge accepting layer. In response to the application of the second applied input voltage, at least a portion of the lowest energy state of the second charge accepting layer can have an energy lower than the Fermi energy of the second charge accepting layer. Therefore, in response to the application of the second applied input voltage, mobile charge carriers can flow from the charge reservoir into the second charge accepting layer.

[0063] The second charge accepting layer can thus be occupied in response to the application of the second applied input voltage. Thus, the second charge accepting layer can provide a low resistance to current in response to the application of the second applied input voltage. Thus, the second charge accepting layer can become conductive in response to the application of the second applied input voltage.

[0064] Thus, in response to application of the first applied input voltage, the number of mobile charge carriers in the charge reservoir may decrease. Thus, in response to application of the second applied input voltage, the charge reservoir may become unpopulated by mobile charge carriers.

[0065] In response to the application of the second applied input voltage, the lowest energy state of the charge reservoir can have an energy lower than the lowest energy state of the first charge accepting layer. In response to the application of the second applied input voltage, the lowest energy state of the first charge accepting layer can have an energy higher than the Fermi energy of the first charge accepting layer.

[0066] Therefore, the first charge accepting layer can remain free of mobile charge carriers, that is, in response to the application of the second applied input voltage, mobile charge carriers may not flow from the charge reservoir into the first charge accepting layer. Therefore, in response to the application of the second applied input voltage, the first charge accepting layer can remain unoccupied by mobile charge carriers. Therefore, the first charge accepting layer can continue to provide high resistance to current in response to the application of the second applied input voltage. Therefore, in response to the application of the second applied input voltage, the first charge accepting layer can remain non-conductive, i.e., insulating.

[0067] The mobile charge carriers may be electrons or holes. In the case where the mobile charge carriers are electrons, the first applied input voltage may be a positive applied input voltage and the second applied input voltage may be a negative applied input voltage. Alternatively, the first applied input voltage may be a positive applied input voltage and the second applied input voltage may be a smaller positive applied input voltage. This may be the case, for example, where a positive input voltage is applied in a stationary state, i.e., a potential well of a charge reservoir is created. Further optionally, the second applied input voltage may be a negative applied input voltage and the first applied input voltage may be a smaller negative applied input voltage. This may be the case, for example, where a negative input voltage is applied in a stationary state, i.e., a potential well of a charge reservoir is created.

[0068] In the case where the mobile charge carriers are holes, the first applied input voltage may be a negative applied input voltage and the second applied input voltage may be a positive applied input voltage. Alternatively, the first applied input voltage may be a negative applied input voltage and the second applied bias voltage may be a smaller negative applied input voltage. This may be the case, for example, where a negative input voltage is applied in a stationary state, i.e., a potential well of a charge reservoir is created. Further optionally, the second applied input voltage may be a positive applied input voltage and the first applied input voltage may be a smaller positive applied input voltage. This may be the case, for example, where a positive input voltage is applied in a stationary state, i.e., a potential well of a charge reservoir is created.

[0069] The semiconductor device may include a planar layer. Any or all of the first charge accepting layer, the second charge accepting layer, the charge reservoir and the charge barrier may include a substantially planar layer. Thus, the semiconductor structure may have a planar layered arrangement, i.e., the semiconductor layer and / or the charge barrier may be substantially planar. Alternatively, the semiconductor device may be arranged such that the semiconductor device layers and / or the charge barrier extend at least partially around each other, for example in the form of nanowires. Thus, each individual semiconductor device layer and / or the charge barrier may be substantially cylindrical.

[0070] When the above-mentioned layers are substantially planar, the plane of each layer can be substantially parallel to the growth of the layer, and / or substantially parallel to the plane of the substrate. That is, the layers can grow vertically on the substrate, i.e. in a direction perpendicular to the plane of the substrate, and / or in a direction parallel to the normal of the substrate plane. In contrast, the different terminal regions (i.e., "pnp" or "npn" doped regions) of a conventional CMOS gate are arranged laterally on the substrate. Therefore, the above-mentioned features may be advantageous because the vertical growth of the layers makes the gate more scalable. The absence of any lateral doping can also eliminate the problem of "short channel effect".

[0071] The logic gate may operate as an inverter. Therefore, according to another aspect of the present invention, there is provided an inverter comprising a logic gate as described above.

[0072] The logic gate may form part of a logic gate array or sequence, configured to operate as a logic device or digital circuit. For example, as described above, the logic gate according to the present invention is effectively used as a traditional CMOS NOT gate. Accordingly, since traditional CMOS logic always includes paired nMOS and pMOS, i.e., an equal number of nMOS and pMOS transistors, the one or more logic gates described above may be configured to form a logic device, such as a NAND gate, a NOR gate, an OR gate, or an AND gate. Therefore, according to another aspect of the present invention, a logic device or digital circuit comprising one or more logic gates as described above is provided. The logic device may be a NAND gate, a NOR gate, an OR gate, or an AND gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] A possible embodiment of the present invention will now be described by way of example only with reference to the accompanying drawings, in which:

[0074] Figure 1 is a circuit diagram of a conventional CMOS NOT logic gate known in the prior art;

[0075] Figure 2a is a cross-sectional view of a logic device according to an embodiment of the present invention, wherein no bias is applied to the device;

[0076] Figure 2b yes Figure 2a A cross-sectional view of a logic device, wherein a positive bias is applied to the device;

[0077] Figure 2c yes Figure 2a A cross-sectional view of a logic device, wherein a negative bias is applied to the device;

[0078] Figure 3a is a schematic diagram of conduction band energy levels of a logic device according to a first embodiment of the present invention;

[0079] Figure 3b is a schematic diagram of conduction band energy levels of a logic device according to a second embodiment of the present invention;

[0080] Figure 4 is a cross-sectional view of a logic device according to an embodiment of the present invention, showing example materials used to form the logic device;

[0081] Figure 5a yes Figure 4 A simulated conduction band energy level diagram of a logic device, where no bias is applied to the device;

[0082] Figure 5b When a positive bias is applied to the device, Figure 4 Simulated conduction band energy level diagram of logic device;

[0083] Figure 5c is when a negative bias is applied to the device. Figure 4 Simulated conduction band energy level diagram of logic device;

[0084] Figure 6 yes Figure 4 A graph of electron density of a channel layer of a logic device versus a bias voltage applied to the device;

[0085] Figure 7a is a cross-sectional view of an inverter 200 implementing a logic device according to a first embodiment of the present invention;

[0086] Figure 7b is a cross-sectional view of an inverter 300 implementing a logic device according to second and third embodiments of the present invention;

[0087] Figure 7c is a cross-sectional view of an inverter 300 implementing a logic device according to a fourth embodiment of the present invention;

[0088] Figure 8a When a positive bias is applied to the device Figure 7a A cross-sectional view of an inverter 200;

[0089] Figure 8b When a negative bias is applied to the device Figure 7a 2 is a cross-sectional view of an inverter 200. DETAILED DESCRIPTION

[0090] Figure 2a to Figure 2c The movement of charge carriers across the logic device 100 is shown, depending on the bias applied to the logic device 100 .

[0091] Figure 2a 1 shows a cross-sectional view of a logic device 100. The logic device 100 includes a charge storage reservoir 110, a first channel layer 120 (referred to as a "first charge accepting layer" in the invention defined above), and a second channel layer 130.

[0092] (Referred to as the "second charge accepting layer" in the invention defined above.) In the absence of any applied bias, the charge carriers 140 of the logic device 100 reside in the charge reservoir 110. Where layers 120 and 130 are described as "channel" layers, this means that these layers are capable of accepting mobile charge carriers, thereby enabling them to become conductive and act as conventional channel layers in use.

[0093] Figure 2bThe same logic device 100 is shown when a positive bias voltage is applied. In response to the application of the positive bias voltage, the charge carriers 140 of the logic device 100 move from the charge reservoir 110 into the first channel layer 120 .

[0094] Figure 2c The same logic device 100 is shown when a negative bias is applied. In response to the application of the negative bias, the charge carriers 140 of the logic device 100 move from the charge reservoir 110 into the second channel layer 130 .

[0095] exist Figure 2a to Figure 2c In the example of , the charge carriers 140 are electrons. However, it is contemplated that the charge carriers 140 may instead be holes, in which case the logic device will operate in the opposite manner. That is, if the charge carriers 140 are holes, then in response to the application of a positive bias, the charge carriers 140 of the logic device 100 will move from the charge reservoir 110 to the second channel layer 130, and in response to the application of a negative bias, the charge carriers 140 of the logic device 100 will move from the charge reservoir 110 to the first channel layer 120.

[0096] Figure 3a and Figure 3b Shows that it is possible Figure 2a to Figure 2c Example conduction band minimum energy level diagram of logic device 100 illustrating the described behavior.

[0097] Figure 3a A first example of a logic device 100 is shown, wherein the charge reservoir 110 is made of a first material having a relatively low conduction band edge energy, and the first channel layer 120 and the second channel layer 130 are made of different materials having relatively high conduction band edge energy levels. Relatively low means that the conduction band edge energy of the charge reservoir 110 is lower than the conduction band edge energy of both the first channel layer 120 and the second channel layer 130. Relatively high means that the conduction band edge energy of both the first channel layer 120 and the second channel layer 130 is higher than the conduction band edge energy of the charge reservoir 110. Due to the described difference in conduction band edge energies, the first and second channels 120, 130 define an electric potential barrier on either side of the charge reservoir 110, so that the charge reservoir 110 forms a potential well.

[0098] In the absence of an applied bias, the charge reservoir 110 thus provides the charge carriers 140 with a lower energy state 150 than the first channel layer 120 and the second channel layer 130 , and the charge carriers 140 remain in the charge reservoir 110 .

[0099] When a positive bias is applied, the conduction band edge twists unidirectionally so that the first channel layer 120 provides a lower energy state for the charge carriers 140 than the charge reservoir 110 and the second channel layer 130 , and as a result, the charge carriers move from the charge reservoir 140 to the first channel layer 120 .

[0100] When a negative bias is applied, the conduction band edge twists in the opposite way so that the second channel layer 130 provides a lower energy state for the charge carriers 140 than the charge reservoir 110 and the first channel layer 120 , and as a result the charge carriers move from the charge reservoir 140 to the second channel layer 130 .

[0101] Figure 3b A second example is shown in which a quantum well is formed in each of the charge reservoir 110 , the first channel layer 120 , and the second channel layer 130 due to the presence of the charge barrier, but the quantum well of the charge reservoir 110 is much wider than those of the first channel layer 120 and the second channel layer 130 .

[0102] In the absence of an applied bias, the charge reservoir 110 thus provides an energy state 150 that is lower than the energy states 160 , 170 provided by the first channel layer 120 and the second channel layer 130 , and the charge carriers 140 remain in the charge reservoir 110 .

[0103] When a positive bias is applied, the conduction band edge twists unidirectionally so that the lowest energy state 160 of the first channel layer 120 becomes lower than the energy states 150 , 170 of the charge reservoir 110 and the second channel layer 130 , respectively, and as a result charge carriers move from the charge reservoir 140 to the first channel layer 120 .

[0104] When a negative bias is applied, the conduction band edge twists in the opposite way so that the lowest energy state 170 of the second channel layer 130 becomes lower than the energy states 150 , 160 of the charge reservoir 110 and the first channel layer 120 , respectively, and as a result charge carriers move from the charge reservoir 140 to the second channel layer 130 .

[0105] about Figure 5a to Figure 5c The provision of such energy states and band edge distortions is described in more detail, wherein the conduction and valence band edge energies on the logic device 100 are simulated in a one-dimensional model (vertically through the device) at 300K using a Schrodinger-Poisson solver in the effective mass approximation.

[0106] exist Figure 5a to Figure 5c In the energy diagram of FIG. 1 , the logic device 100 is Figure 4 The layered arrangement shown is formed. Figure 4In the embodiment, the charge reservoir 110 is formed of a 80 nm thick gallium arsenide (GaAs) layer, and the first channel layer 120 and the second channel layer 130 are formed of a 30 nm thick aluminum gallium arsenide (AlGaAs) layer on both sides of the charge reservoir 110. 0.18 Ga 0.82 As) layer is formed.

[0107] This arrangement was chosen because GaAs / AlGaAs is the most mature and best understood compound semiconductor system, and because changing the Al fraction in the AlGaAs layer changes the band gap relative to the GaAs layer and the conduction and valence band edges while causing only minimal changes in the lattice constant. This enables the growth of multilayer GaAs / Al x Ga 1-x As heterostructure materials, both the conduction band and valence band edges are designed as desired, with high quality and little or no strain. However, it is contemplated that other semiconductor materials, including other III-V semiconductor materials, may be used.

[0108] The insulating layer 180 is located outside the channel layers 120, 130, both of which are formed of a 20nm thick aluminum arsenide (AlAs) layer. Finally, placed outside the insulating layer 180 is a gate 190, through which a bias voltage can be applied to the device 100 in use. The entire device 100 can also be built on a substrate.

[0109] exist Figure 5a to Figure 5c In FIG. 1 , the x-axis represents the thickness of the logic device 100 (ie, Figure 4 As shown, the x-axis passes vertically through the device 100 from top to bottom), and the y-axis represents the energy of the band edge.

[0110] Figure 5a FIG. 1 shows a simulated schematic energy band diagram of the proposed logic device 100 without any bias applied. Figure 5a It can be seen that for the charge reservoir 110 (at least at the edges) and the channel layers 120, 130, the Fermi level is located within the band gap (i.e., between the conduction band and valence band edges), which means that the electrons 140 remain in the central portion of the charge reservoir 110, so that there are no mobile electrons in the channel layers 120 and 130, as previously described. Therefore, no current can flow in the channel layers 120 and 130 of the logic device 100, and the device 100 is in the "off" state.

[0111] Figure 5b FIG. 1 shows a simulated schematic band energy diagram of the proposed logic device 100 in the presence of a +3 V bias. As a result of the applied bias, the conduction band and valence band edges are vertically twisted so that the electron Fermi level is above the conduction band edge minimum in the first channel layer 120. Although this Figure 5bIt is not obvious in the figure, but a closer look shows that the electron Fermi level is higher than the conduction band edge minimum at the periphery of the first channel layer 120. Therefore, the electrons 140 of the logic device 100 move from the charge reservoir 110 to the first channel layer 120, making the first channel layer 120 highly conductive.

[0112] Instead, the Fermi level remains within the band gap of both the charge reservoir 110 (at least at the edges) and the second channel layer 130, meaning that no current can flow into the second channel layer 130. Equally important, the hole Fermi level remains within the band gap between the charge reservoir 110 and the channel layers 120, 130, preventing any hole transport during operation.

[0113] Figure 5c FIG. 1 shows a simulated schematic band energy diagram of the proposed logic device 100 in the presence of a -3 V bias. As a result of the applied bias, the conduction band and valence band edges are vertically twisted so that the electron Fermi level is above the conduction band edge minimum in the second channel layer 130. Although this Figure 5c It is not obvious in the figure, but a closer look shows that the electron Fermi level is higher than the conduction band edge minimum at the periphery of the second channel layer 130. Therefore, the electrons 140 of the logic device 100 move from the charge reservoir 110 to the first channel layer 130, making the first channel layer 130 highly conductive.

[0114] Instead, the Fermi level remains within the band gap of both the charge reservoir 110 (at least at the edges) and the first channel layer 120, meaning that no current can flow into the second channel layer 120. Importantly, the hole Fermi level remains within the band gap between the charge reservoir 110 and the channel layers 120, 130, preventing any hole transport during operation.

[0115] It should also be noted that due to the vertical symmetry of the layers (ignoring any substrate on which the device 100 is grown), applying equal and opposite biases to the top gates 190 will have equal and opposite effects on the operation of the device 100 .

[0116] Figure 6 The electron transport depending on the bias voltage applied to the device 100 is shown. Figure 6 , the x-axis represents the bias voltage applied to the device, and the y-axis represents the integrated electron density in each of the first channel layer 120 and the second channel layer 130 as a result of the bias voltage applied to the device 100 .

[0117] In the case of applying a negative bias, the second channel layer 130 has a high integrated electron density and is therefore highly conductive, and the first channel layer 120 has a very low integrated electron density and is therefore non-conductive. In the case of applying a positive bias, the second channel layer 130 has a very low integrated electron density, making it non-conductive, and the first channel layer 120 has a high integrated electron density, making it highly conductive.

[0118] Although there is a small electron density in the first channel layer 120 in the case of zero bias and negative bias, and a small electron density in the second channel layer 130 in the case of zero bias and positive bias, this is a result of simulation conditions. In a real device with a finite size typical of modern electronic devices, the number of mobile electrons in those channels under such conditions would be less than 1, and thus have no effect on the operation of the device.

[0119] Figure 7a A first embodiment is shown in which the logic device 100 described herein may be used as part of an inverter 200 . Figure 7a The inverter 200 includes a planar layered arrangement in which the charge reservoir 110 is sandwiched between the first channel layer 120 and the second channel layer 130, and the structure itself is sandwiched between the insulating layer 180. The gate 190 is applied on both sides of the insulating layer 190, and the input voltage V IN is provided to the top gate 190. The bottom gate 190 is grounded. The source and drain terminals are also provided to both the first channel layer 120 and the second channel layer 130. The driving voltage V DD The first channel layer 120 is provided with a voltage V through a drain terminal, and the drain terminal of the second channel layer 130 is grounded. The outlet voltage V is provided via the source terminals of the first channel layer 120 and the second channel layer 130. OUT .

[0120] Figure 7b 1 and 2 show cross sections of two further possible embodiments, in which the logic device 100 described herein may be used as part of an inverter 300, the inverter being provided in the form of a "FINFET" device and a nanowire, respectively. Since both forms would have the same cross section, both embodiments are referred to. Figure 7b Give a description.

[0121] In the second embodiment, Figure 7b The inverter 300 is connected with Figure 7aThe inverter 300 operates in the same manner as the inverter 200, but is provided in the form of a "FinFET" device in which the plane of the layers extends into the page. "FinFET" devices can be considered to have advantages over traditional planar devices in that the gate, and therefore the gate voltage, can be applied to three sides of the device, rather than just one side. In this regard, the inverter 300 includes a layered arrangement in which an inner gate 190 is surrounded by an insulating layer 180, which is in turn surrounded by a second channel layer 130, which is in turn surrounded by a charge reservoir 110, which is in turn surrounded by a first channel layer 120, which is in turn surrounded by an insulating layer 180, and the entire arrangement is surrounded by an outer gate 190. As in Figure 7a In the embodiment of the present invention, source terminals and drain terminals are provided to the first channel layer 120 and the second channel layer 130, and these terminals are grounded and also connected to the same Figure 7a The same way as in the embodiment provides the input voltage V IN , driving voltage V DD and the output voltage V OUT .

[0122] In the third embodiment, Figure 7b The inverter 300 is provided in the form of a nanowire. In a manner similar to a "FinFET", such a nanowire device can be considered superior to a traditional planar device as the gate, so that the electric field can be applied around the device. In this regard, the inverter 300 includes a cylindrical layered arrangement in which an inner gate 190 is surrounded by an insulating layer 180, which is in turn surrounded by a second channel layer 130, which is in turn surrounded by a charge reservoir 110, which is in turn surrounded by a first channel layer 120, which is in turn surrounded by an insulating layer 180, and the entire arrangement is surrounded by an outer gate 190. As in Figure 7a In the embodiment of the present invention, source terminals and drain terminals are provided to the first channel layer 120 and the second channel layer 130, and these terminals are grounded and also connected to the same Figure 7a The same way as in the embodiment provides the input voltage V IN , driving voltage V DD and the output voltage V OUT .

[0123] Figure 7c A fourth embodiment of the logic device 100 described herein is shown, which may be used as part of the inverter 300 . Figure 7c The inverter 300 is connected with Figure 7a The inverter 200 operates in the same manner as the inverter 200, but provides an alternative geometry for the top gate 190, wherein two separate top gates 190 are provided. This allows the voltage V IN can be simultaneously applied to the first charge accepting layer 120 (via Figure 7carrangement on the left hand side of the center) and the charge reservoir 110 (via Figure 7c This may be advantageous for the operation of the logic device 100, particularly if the logic device 100 forms part of a larger logic device or digital circuit.

[0124] Figure 8a and Figure 8b Shows the use of Figure 7a The inverter 200. Figure 8a In the process, a positive voltage is applied to the top gate 190 (V IN ) is applied to the device 200, electrons move from the charge reservoir 110 to the first channel layer 120, as described above with respect to the relative band edge energy diagram. This creates a low resistance state between the source and drain terminals of the first channel layer 120, and a relatively high resistance state between the source and drain terminals of the second channel layer 130. This enables current to flow through the first channel layer 120 at a low resistance, so that at V DD Any voltage applied to the device 200 is transmitted via V OUT Output.

[0125] On the contrary, Figure 8b In the process, negative voltage is applied to the top gate 190 (V IN ) is applied to the device 200, electrons move from the charge reservoir 110 into the second channel layer 130, as described above with respect to the relative band edge energy diagram. This creates a low resistance state between the source and drain terminals of the second channel layer 130, and a relatively high resistance state between the source and drain terminals of the first channel layer 120. This prevents any current from flowing through the first channel layer 120 and allows current to flow through the second channel layer 130 with low resistance, so that V OUT The voltage output at ground.

[0126] In this respect, the inverter device 200 functions similarly to a conventional CMOS logic device, i.e., the first channel layer 120 acts as a pMOS layer, and the second channel layer 130 acts as an nMOS layer. Similar to conventional CMOS logic devices, devices according to the present invention can be combined to form other digital logic gates, such as AND, NAND, OR, or NOR logic gates.

[0127] It is also foreseeable that Figure 7a , Figure 7b , Figure 8a and Figure 8b In an arrangement of , instead of using a metal gate 190 , a highly doped semiconductor may be used which will effectively function in the same manner as a metal gate.

Claims

1. A logic gate comprising a semiconductor device, the semiconductor device comprising a charge reservoir arranged between a first charge accepting layer and a second charge accepting layer, the first charge accepting layer defining a first current flow path, the first current flow path being connected at one end to a common output contact and at another end to a drive contact, and the second charge accepting layer defining a current flow path, the current flow path being connected at one end to the common output contact and at another end to a ground contact, the charge reservoir comprising a potential well having a lowest energy state of mobile charge carriers, the lowest energy state being at an energy lower than the energy of the lowest energy state of mobile charge carriers of both the first charge accepting layer and the second charge accepting layer, the logic gate further comprising a control gate and a ground electrode separated from the charge accepting layers by a non-conductive layer, the control gate and the ground electrode being configured to apply an input voltage across the semiconductor device so that mobile charge carriers confined within the charge reservoir are transferred to the first charge accepting layer at a first applied input voltage and to the second charge accepting layer at a second applied input voltage.

2. The logic gate according to claim 1, wherein: When no input voltage is applied, the first charge accepting layer and / or the second charge accepting layer is non-conductive.

3. The logic gate according to claim 2, wherein: The first charge accepting layer remains non-conductive in response to application of the second applied input voltage.

4. The logic gate according to claim 2, wherein: The second charge accepting layer remains non-conductive in response to application of the first applied input voltage.

5. A logic gate according to any preceding claim, wherein: The mobile charge carriers are electrons.

6. The logic gate according to claim 5, wherein: The first applied input voltage is a positive applied input voltage, and the second applied bias voltage is a negative applied input voltage.

7. A logic gate according to any preceding claim, wherein: The semiconductor device includes a planar layered arrangement.

8. The logic gate according to claim 7, wherein: The logic gate further comprises a substrate layer, and a plane of each layer is substantially parallel to a plane of the substrate.

9. A logic gate according to any preceding claim, wherein: The semiconductor device includes a heterostructure.

10. A logic gate according to any preceding claim, wherein: The charge reservoir includes a quantum well defined between the first charge accepting layer and the second semiconductor layer.

11. The logic gate according to claim 9 or 10, wherein: The quantum wells of the charge reservoir have discrete internal energy levels for accommodating mobile charge carriers in the charge reservoir.

12. A logic gate according to any preceding claim, wherein: The lowest energy state of mobile charge carriers in the conduction band of the first charge accepting layer and the conduction band of the second charge accepting layer has a higher energy than the lowest energy state of the charge reservoir.

13. A logic gate according to any preceding claim, wherein: In response to application of the first applied input voltage, the lowest energy state of at least a portion of the charge reservoirs has an energy higher than at least a portion of a conduction band energy of the first charge accepting layer.

14. A logic gate according to any preceding claim, wherein: In response to application of the first applied input voltage, at least a portion of the conduction band energy of the first charge accepting layer has an energy lower than the Fermi energy of the first charge accepting layer.

15. A logic gate according to any preceding claim, wherein: In response to application of the first applied input voltage, the lowest energy state of the charge reservoir has an energy lower than the conduction band energy of the second charge accepting layer.

16. A logic gate according to any preceding claim, wherein: In response to application of the first applied input voltage, a conduction band energy of the second charge accepting layer has energy higher than a Fermi energy of the second charge accepting layer.

17. A logic gate according to any preceding claim, wherein: In response to application of the second applied input voltage, the lowest energy state of at least a portion of the charge reservoirs has an energy higher than at least a portion of a conduction band energy of the second charge accepting layer.

18. A logic gate according to any preceding claim, wherein: In response to application of the second applied input voltage, at least a portion of the conduction band of the second charge accepting layer has an energy lower than the Fermi energy of the second charge accepting layer.

19. A logic gate according to any preceding claim, wherein: In response to application of the second applied input voltage, the lowest energy state of the charge reservoir has an energy lower than a conduction band energy of the first charge accepting layer.

20. A logic gate according to any preceding claim, wherein In response to application of the second applied input voltage, the conduction band energy of the first charge accepting layer has higher energy than the Fermi energy of the first charge accepting layer.

21. The logic gate according to any one of claims 1 to 11, wherein: The first charge accepting layer includes a potential well defined between a first outer charge potential barrier and a first inner charge potential barrier, and the second charge accepting layer includes a potential well defined between a second outer charge potential barrier and a second inner charge potential barrier.

22. The logic gate of claim 21, wherein: The potential well of the first semiconductor layer and / or the potential well of the second semiconductor layer is a quantum well having discrete internal energy levels for accommodating charge carriers in the first semiconductor layer and / or the second semiconductor layer.

23. The logic gate of claim 22, wherein: The lowest energy state of the first charge accepting layer and the lowest energy state of the second charge accepting layer have higher energy than the lowest energy state of the charge reservoir.

24. A logic gate according to claim 22 or 23, wherein: In response to application of the first applied input voltage, the lowest energy state of the charge reservoir has a higher energy than the lowest energy state of the first charge accepting layer.

25. A logic gate according to any one of claims 22 to 24, wherein: In response to application of the first applied input voltage, a lowest energy state of at least a portion of the first charge accepting layer has an energy lower than a Fermi energy of the first charge accepting layer.

26. A logic gate according to any one of claims 22 to 25, wherein: In response to application of the first applied input voltage, the lowest energy state of the charge reservoir has a lower energy than the lowest energy state of the second charge accepting layer.

27. A logic gate according to any one of claims 22 to 26, wherein: In response to application of the first applied input voltage, the lowest energy state of the second charge accepting layer has an energy higher than a Fermi energy of the second charge accepting layer.

28. A logic gate according to any one of claims 22 to 27, wherein: In response to application of the second applied input voltage, the lowest energy state of the charge reservoir has a higher energy than the lowest energy state of the second charge accepting layer.

29. A logic gate according to any one of claims 22 to 28, wherein: In response to application of the second applied input voltage, at least a portion of the lowest confined internal states of the second charge accepting layer have an energy lower than the Fermi energy of the second charge accepting layer.

30. A logic gate according to any one of claims 22 to 29, wherein: In response to application of the second applied input voltage, the lowest energy state of the charge reservoir has a lower energy than the lowest energy state of the first charge accepting layer.

31. A logic gate according to any one of claims 22 to 30, wherein: In response to application of the second applied input voltage, the lowest energy state of the first charge accepting layer has energy higher than the Fermi energy of the first charge accepting layer.

32. A logic device or digital circuit comprising one or more logic gates according to any preceding claim.

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