Method for manufacturing package substrate and package substrate using same

Abstract

The present specification relates to a method for manufacturing a package substrate and a package substrate using the same. The package substrate according to the present specification includes a core layer including a glass substrate having a first surface and a second surface facing each other, and a cavity portion penetrating the glass substrate, a cavity module disposed in the cavity portion, the cavity module includes a cavity element and a first insulating layer surrounding the cavity element, the first insulating layer being disposed on all surfaces of the cavity element other than one surface or on all surfaces of the cavity element, the first insulating layer includes a second insulating layer recessed into a remaining portion of the cavity portion except the cavity module, and the first insulating layer and the second insulating layer have different dielectric constants. As a result, the occurrence of fluctuations due to gaps between the elements and / or gaps between the cavity and the elements can be prevented, and the occurrence of leakage current can be prevented.

Description

Technical Field

[0001] This document relates to a package substrate, a semiconductor package, a method for manufacturing a package substrate, a method for manufacturing a semiconductor package, and the like. Background Art

[0002] When manufacturing electronic components, realizing circuits on semiconductor wafers is called the front-end (FE) process, and assembling the wafers into a state that can be used in actual products is called the back-end (BE) process. The back-end process includes the packaging process.

[0003] As the four core technologies of the semiconductor industry that have recently achieved rapid development of electronic products, there are semiconductor technology, semiconductor packaging technology, manufacturing process technology and software technology. Semiconductor technology is developing in various forms, such as line width of nanometer units below microns, more than 10 million cells, high-speed operation and release of a large amount of heat, but it has not yet been supported by relatively complete packaging of the above semiconductors. Therefore, the electrical performance of semiconductors sometimes depends on the packaging technology and the corresponding electrical connections, rather than on the performance of the semiconductor technology itself.

[0004] As the material of the packaging substrate, ceramic or resin is suitable. In the case of a ceramic substrate such as a silicon substrate, it is difficult to mount a high-performance high-frequency semiconductor element due to the high resistance value or high dielectric constant. In the case of a resin substrate, although relatively high-performance high-frequency semiconductor elements can be mounted, there are limitations in reducing the spacing of wiring.

[0005] Recently, glass substrates can be applied to high-end package substrates. By forming through holes on the glass substrate and applying conductive materials to the through holes, the wiring length between the element and the motherboard can be shortened, and excellent electrical characteristics can be achieved.

[0006] Also, the semiconductor package generates heat during operation, and sometimes additionally includes a heat sink for releasing the heat.

[0007] As related prior arts, there are U.S. Patent Publication US20220293560A1, Korean Patent Publication No. 10-2018-0142742, etc. Summary of the invention

[0008] Technical issues to be solved

[0009] The purpose of this embodiment is to provide a method for manufacturing a packaging substrate using a glass substrate, which can prevent undulation caused by gaps between cavity elements and / or gaps between a cavity portion and a cavity element, and a packaging substrate using the same.

[0010] In addition, the present embodiment aims to provide a method for manufacturing a packaging substrate and a packaging substrate using the same, which can efficiently manufacture a packaging substrate by forming a first insulating layer on all surfaces except one surface of a cavity element arranged in a cavity portion of a glass substrate or on all surfaces of the cavity element, and forming a second insulating layer stacked on the first surface and the second surface of the glass substrate.

[0011] Solutions to technical problems

[0012] In order to achieve the above-mentioned purpose, according to one embodiment, a packaging substrate includes a core layer, the core layer includes a glass substrate and a cavity portion, the glass substrate has a first surface and a second surface facing each other, the cavity portion penetrates the glass substrate, a cavity module is arranged in the cavity portion, the cavity module includes a cavity element and a first insulating layer surrounding the cavity element, the first insulating layer is arranged on all surfaces of the cavity element except one surface or on all surfaces of the cavity element, the second insulating layer is arranged on the portion of the cavity portion except the cavity module in a manner of being at least partially embedded, and the first insulating layer and the second insulating layer have different dielectric constants.

[0013] The dielectric constant of the first insulating layer may be lower than the dielectric constant of the second insulating layer.

[0014] The high-frequency relative dielectric constant Dk may be a relative dielectric constant at a high frequency of 5.8 GHz, and the difference between the high-frequency relative dielectric constant Dk1 of the first insulating layer and the high-frequency relative dielectric constant Dk2 of the second insulating layer may be greater than 0.1.

[0015] The dielectric loss rate of the first insulating layer may be Df1, the dielectric loss rate of the second insulating layer may be Df2, and the difference between Df1 and Df2 may be greater than 0.0001.

[0016] The first insulating layer may include liquid crystal polymer (LCP), epoxy molding compound (EMC), Ajinomoto build-up film (ABF) or modified polyimide (MPI).

[0017] The second insulating layer may include an insulating mixture.

[0018] The insulating mixture may include a mixture of inorganic particles and a polymer resin.

[0019] The connection electrode may be arranged on the above-mentioned cavity element.

[0020] The cavity components mentioned above may include passive components or active components.

[0021] The first insulating layer may be provided with a first insulating layer through hole penetrating the first insulating layer.

[0022] A part or the whole of the through hole of the first insulating layer may be filled with electrode material.

[0023] On the other hand, in order to achieve the above-mentioned purpose, a manufacturing method of a packaging substrate according to one embodiment includes the following steps: preparing a glass substrate and a cavity module arranged with a cavity portion; arranging the above-mentioned cavity module in the above-mentioned cavity portion; and stacking a second insulating layer on the above-mentioned glass substrate; the above-mentioned cavity module includes a cavity element and a first insulating layer surrounding the above-mentioned cavity element, and the above-mentioned first insulating layer is arranged on all surfaces of the above-mentioned cavity element except one surface or on all surfaces of the above-mentioned cavity element.

[0024] The first insulating layer and the second insulating layer may have different dielectric constants.

[0025] The first insulating layer may include liquid crystal polymer (LCP), epoxy molding compound (EMC), Ajinomoto built-up film (ABF) or modified polyimide (MPI).

[0026] The second insulating layer may include Ajinomoto built-up film (ABF) or epoxy molding compound (EMC).

[0027] The connection electrode may be formed on the above-mentioned cavity member.

[0028] Effects of the Invention

[0029] The method for manufacturing a package substrate and the package substrate using the same according to the present embodiment can greatly improve the quality of the package substrate by preventing the undulation phenomenon from occurring in the cavity portion of the embedded cavity element.

[0030] In addition, by improving the undulation phenomenon of the cavity portion, leakage current can be prevented from occurring in the cavity element including the passive element and / or the active element, thereby greatly improving the quality of the packaging substrate.

[0031] In addition, by forming a first insulating layer having a dielectric constant different from that of the second insulating layer on all surfaces of the cavity element except one surface or on all surfaces of the cavity element, a short circuit caused by contact between cavity elements arranged side by side can be prevented, and a short circuit that may occur unintentionally during the manufacturing process of forming a conductive layer on the side of the cavity portion can be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram for explaining the cross-sectional structure of a package substrate according to the present embodiment.

[0033] Figure 2 FIG. 1 is a schematic diagram illustrating a cross-sectional structure of a package substrate according to another embodiment.

[0034] Figure 3 Parts (a) and (b) of FIG. 1 are schematic diagrams each illustrating a portion of a package substrate according to the present embodiment in cross section.

[0035] Figure 4 The flowchart is a cross-sectional view of a process for producing a core distribution layer in a process for manufacturing a package substrate according to the present embodiment.

[0036] Figure 5 The flowchart is a cross-sectional view of a process for generating an insulating layer in a process for manufacturing a package substrate according to the present embodiment.

[0037] Figure 6 FIG. 4 is an example of a cross-sectional structure of a core layer of a package substrate produced according to this embodiment.

[0038] Figure 7 A flow chart illustrating a method for manufacturing a packaging substrate according to the present embodiment in cross section, wherein S represents forming a first insulating layer, P1 represents arranging elements, P2 represents forming a second insulating layer (upper part), P3 represents forming a second insulating layer (lower part), and P4 represents hardening (upper part / lower part).

[0039] Figure 8 A flow chart illustrating a method for manufacturing a packaging substrate according to another embodiment in cross section, wherein P1 represents an arrangement element, S represents forming a first insulating layer, P2 represents forming a second insulating layer (upper part), P3 represents a second insulating layer (lower part), and P4 represents hardening (upper part / lower part).

[0040] Description of Reference Numerals

[0041] 100: Semiconductor devices

[0042] 10: Motherboard

[0043] 30: Semiconductor Components

[0044] 32: First semiconductor element

[0045] 34: Second semiconductor element

[0046] 36: The third semiconductor element

[0047] 20: Package substrate

[0048] 21, 21a: Glass substrate

[0049] 22: Core layer

[0050] 223: Core insulation

[0051] 213: First Surface

[0052] 214: Second Surface

[0053] 23: Core through hole

[0054] 24: Core distribution layer

[0055] 241: Core distribution pattern

[0056] 26: Upper layer

[0057] 25: Upper distribution layer

[0058] 251: Upper distribution pattern

[0059] 23b: Blind hole

[0060] 253: Upper insulation layer

[0061] 27: Top connection layer

[0062] 271: Electrode connected above

[0063] 272: Connection pattern above

[0064] 28: Cavity

[0065] 281: Interior Space

[0066] 282: Cavity distribution layer

[0067] 40: Cavity components

[0068] 50: Connection

[0069] 51: Component connection

[0070] 52: Plate connection

[0071] 60: Overlay

[0072] 61: First insulation layer

[0073] 62: Second insulation layer

[0074] 63: Electrode DETAILED DESCRIPTION

[0075] The following detailed description is provided to help fully understand the method, device and / or system described herein. However, after understanding the disclosure of the application, various changes, modifications and equivalents of the method, device and / or system described herein will be apparent. For example, the order of operations described herein is merely an example and is not limited to the operations recorded herein. In addition to the operations that must be performed in a specific order, based on the understanding of the disclosure of the application, the order of operations can be changed. In addition, after understanding the disclosure of the application, the description of known features can be omitted to increase clarity and simplicity. However, the omission of these features and descriptions is not intended to be recognized as common sense.

[0076] The features described herein may be embodied in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many possible ways to implement the methods, devices and / or systems described herein, which will be apparent after understanding the disclosure of the present application.

[0077] Although terms such as "first", "second", and "third" may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections should not be limited by these terms. Rather, these terms are only used to distinguish one component, part, region, layer, or section from another component, part, region, layer, or section. Therefore, without departing from the teachings of the examples described herein, the first component, part, region, layer, or section mentioned in the examples may also be referred to as the second component, part, region, layer, or section.

[0078] Throughout the specifications, when an element such as a layer, a region or a substrate is described as being “on another element,” “connected to another element,” or “coupled to another element,” it may be directly “on another element,” “connected to another element,” or “coupled to another element,” or one or more other elements may be interposed therebetween. On the contrary, when an element is described as being “directly on another element,” “directly connected to another element,” or “directly coupled to another element,” no other element may be interposed therebetween. Likewise, expressions such as “between,” “immediately between,” “adjacent,” and “immediately adjacent” may also be interpreted as described above.

[0079] The terms used herein are only used for the purpose of describing specific examples, and are not used to limit the present disclosure. As used herein, the singular form is intended to also include the plural form, unless the context clearly states otherwise. As used herein, the term "and / or" includes any one of the items listed in the relevant list and any combination of any two or more items. As used herein, the terms "include", "comprise" and "have" specify the existence of stated features, numbers, operations, elements, parts and / or their combinations, but do not exclude the existence or addition of one or more other features, numbers, operations, elements, parts and / or their combinations. The use of the term "may" herein about examples or embodiments (for example, about the content that can be included or implemented in examples or embodiments) means that there is at least one example or embodiment in which such features are included or implemented, rather than all examples being limited to this.

[0080] In the present application, “B is placed on A” means that B is in direct contact with A or is placed on A with another layer or structure interposed therebetween, and thus should not be construed as being limited to B being in direct contact with A.

[0081] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs consistent with and after understanding the present disclosure. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless explicitly defined herein.

[0082] In one or more examples, the description of "A and / or B" means "A, B, or A and B."

[0083] In one or more examples, terms such as "first," "second," "A," or "B" are used to distinguish the same terms.

[0084] In one or more examples, unless otherwise specified, a singular expression is interpreted as including the singular or plural meaning as interpreted in the context.

[0085] Figure 1 2 is a schematic diagram for explaining a cross-sectional structure of a package substrate according to the present embodiment. Figure 2 2 is a schematic diagram for explaining a cross-sectional structure of a package substrate according to another embodiment. Figure 3 Parts (a) and (b) of FIG. 1 are schematic diagrams each illustrating a portion of a package substrate according to the present embodiment in cross section.

[0086] In order to achieve the above-mentioned purpose, the semiconductor device 100 according to the present embodiment includes: a semiconductor element part 30, in which one or more semiconductor elements 32, 34, 36 are located; a packaging substrate 20, which is electrically connected to the semiconductor element; and a motherboard 10, which is electrically connected to the packaging substrate 20, transmits external electrical signals to the semiconductor elements 32, 34, 36 and connects the above-mentioned semiconductor elements and the external electrical signals.

[0087] The package substrate 20 according to an embodiment includes: a core layer 22 ; an upper layer 26 located on one surface of the core layer 22 ; and a cavity portion 28 in which a cavity element 40 may be located.

[0088] The semiconductor element section 30 is an element mounted on a semiconductor device, and is mounted on the package substrate 20 via connection electrodes, etc. Specifically, as the semiconductor element section 30, for example, a computing element such as a CPU, a GPU (first element: 32, second element: 34), a storage element such as a memory chip (third element: 36), etc. can be applied, but any semiconductor element mounted on a semiconductor device can be applied without limitation.

[0089] The motherboard 10 may be a motherboard such as a printed circuit board or a printed wiring board.

[0090] The package substrate 20 may selectively further include a lower layer (not shown) located below the core layer.

[0091] The core layer 22 may include: a glass substrate 21 including a first region 221 and a second region 222, wherein the first region 221 has a first thickness 211, and the second region 222 is adjacent to the first region 221 and has a second thickness 212 thinner than the first thickness; a plurality of core through holes 23 penetrating the glass substrate 21 in the thickness direction; and a core distribution layer 24 located on the surface of the glass substrate 21 or the core through holes 23, and electrically connecting the first surface 213 of the glass substrate 21 and the second surface 214 facing the first surface through the core through holes 23.

[0092] The second region 222 of the core layer 22 may function as a cavity structure.

[0093] In the same region, the glass substrate 21 has a first surface 213 and a second surface 214 facing each other. The two surfaces are substantially parallel to each other, so that the glass substrate 21 has a certain thickness as a whole.

[0094] The inner space 281 formed by the thickness difference between the first region 221 and the second region 222 serves to accommodate a part or the whole of the cavity element 40 .

[0095] The glass substrate 21 may include a core through hole 23 penetrating the first surface 213 and the second surface 214. The core through hole 23 may be formed in both the first region 221 and the second region 222, and may be formed at a desired pitch and pattern.

[0096] As a packaging substrate for semiconductor devices, a stacked form of silicon substrate and organic substrate has been used in the past. Due to the characteristics of semiconductors, silicon substrates may generate parasitic elements when used in high-speed circuits, and have the disadvantage of relatively large power loss. In addition, organic substrates need to be large in area in order to form more complex distribution patterns, but this does not conform to the trend of manufacturing ultra-miniaturized electronic devices. In order to form a complex distribution pattern within a predetermined size, the pattern actually needs to be miniaturized, but due to the characteristics of materials such as polymers suitable for organic substrates, there are substantial limitations to pattern miniaturization.

[0097] In this embodiment, as a method for solving these problems, a glass substrate 21 is used as a support for the core layer 22. In addition, together with the glass substrate 21, a core through hole 23 formed through the glass substrate is also used, thereby providing a package substrate 20 with a shorter current length, more miniaturization, faster response, and less loss characteristics.

[0098] The glass substrate 21 is preferably a glass substrate suitable for semiconductors, for example, a borosilicate glass substrate, an alkali-free glass substrate, etc., but the present invention is not limited thereto.

[0099] The core through hole 23 penetrates the glass substrate 21. The core through hole 23 may be formed by removing a predetermined region of the glass substrate 21, and more specifically, may be formed by etching a plate-shaped glass using a physical and / or chemical method.

[0100] Specifically, when forming the core through hole 23, a method of forming a defect (groove) on the surface of the glass substrate by laser or the like and then performing chemical etching or laser etching may be used, but the present invention is not limited thereto.

[0101] Based on the unit area (1 cm×1 cm) of the glass substrate 21, the number of the core through holes 23 may be 100 to 3,000, 100 to 2,500, or 225 to 1,024. When the above spacing conditions are met, it is more conducive to forming a conductive layer, etc., and the performance of the package substrate can be improved.

[0102] The core distribution layer 24 includes a core distribution pattern 241 and a core insulation layer 223. The core distribution pattern 241 is a conductive layer that electrically connects the first surface and the second surface of the glass substrate through a core through hole, and the core insulation layer 223 surrounds the core distribution pattern. The core layer 22 is formed with a conductive layer through the core through hole to serve as an electrical channel across the glass substrate 21, thereby connecting the upper and lower parts of the glass substrate at a relatively short distance, and can have faster electrical signal transmission and low loss characteristics. For example, the conductive layer can be a copper plating layer, but the present invention is not limited to this.

[0103] The cavity 28 is substantially in the shape of a circle, a triangle, a quadrilateral, a hexagon, an octagon, a cross, etc., and its shape is not limited.

[0104] The shape of the cavity element 40 can be generally cylindrical, rectangular or polygonal.

[0105] The cavity portion 28 may include a cavity distribution pattern as a conductive layer electrically connecting the cavity element 40 and the core distribution layer 24 and an insulating layer surrounding the cavity distribution pattern.

[0106] On the other hand, the cavity portion according to another embodiment may be implemented in the form of penetrating the first surface 213 and the second surface 214 of the glass substrate 21. In this case, the cavity portion may be formed according to a process similar to that of forming the core through hole 23, and the area and shape of the cavity portion penetrating the glass substrate 21 may be different from those of the core through hole 23.

[0107] In this embodiment, the insulating layer may be formed after the cavity elements 40 are arranged in the cavity portion. That is, the insulating layer may also be formed in the cavity portion by the process of forming the core insulating layer 223 described above.

[0108] The core allocation pattern 241 may be formed as a pattern capable of being electrically connected to the above-mentioned cavity element 40 .

[0109] The cavity element 40 may include an active element such as a transistor or a power transmission element such as a multi-layer ceramic capacitor (MLCC), that is, a passive element.

[0110] As the above-mentioned cavity element 40, when an element such as a transistor is used to convert the electrical signal between the motherboard and the semiconductor element part into an appropriate level, the transistor is used in the path of the packaging substrate 20, so that a semiconductor device 100 with higher efficiency and speed can be provided.

[0111] In addition, power transmission elements such as multilayer ceramic capacitors (MLCCs) play an important role in the performance of semiconductor elements. Generally, more than 200 types of power transmission elements as passive components are applicable to semiconductor elements, and their performance is also affected by the characteristics of the conductive layer surrounding the element when transmitting power. In one embodiment, non-circular core vias can be applied to power transmission elements such as those described above where a low resistance conductive layer is required, instead of circular core vias.

[0112] On the other hand, the above-mentioned cavity element 40 may have a form in which a passive element such as a capacitor is inserted alone, or may be formed in a form embedded between insulator layers (cavity element insulating layers) so that the electrodes of the element group including a plurality of passive elements are exposed and then inserted into the cavity element. In the latter case, the workability of manufacturing the package substrate can be improved more smoothly, and it is more conducive to fully and reliably setting the insulating layer in the space between the complex elements.

[0113] The glass substrate 21 plays an intermediate role and a mediating role in connecting the semiconductor element portion 30 and the motherboard 10 to the upper and lower parts respectively, and the core through hole 23 serves as a passage for transmitting their electrical signals, thereby achieving smooth signal transmission.

[0114] The upper layer 26 is located on the first surface 213 .

[0115] The upper layer 26 may include an upper distribution layer 25 and an upper connection layer 27 located on the upper distribution layer 25 . The uppermost surface of the upper layer 26 may be protected by a cover layer 60 having an opening that allows direct contact between the connection electrodes of the semiconductor element.

[0116] The upper distribution layer 25 may include: an upper insulating layer 253 located on the first surface; and an upper distribution pattern 251, which is a conductive layer having a predetermined pattern and at least a portion of which is electrically connected to the core distribution layer 24, and the upper distribution pattern 251 is built into the upper insulating layer 253.

[0117] As the upper insulating layer 253 , any material as long as it is suitable as an insulating layer for a semiconductor element or a package substrate can be used. For example, epoxy resin including a filler can be used, but the present invention is not limited thereto.

[0118] The insulator layer may be formed by forming a coating and curing it, or may be formed by laminating an insulator film formed in an uncured or semi-cured state on the core layer 22 and curing it. At this time, if a reduced pressure lamination method or the like is adopted, the insulator is sunk into the space inside the core through hole 23, so that the process can be performed efficiently.

[0119] According to one embodiment, even if multiple insulating layers are stacked for application, it may be difficult to distinguish between the insulating layers, and the multiple insulating layers are collectively referred to as upper insulating layers. In addition, the core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, in which case, their boundaries may be substantially indistinguishable. Alternatively, according to another embodiment, the boundaries of the insulating layers may be generated by setting different pressures and temperatures for curing the multiple insulating layers.

[0120] The upper distribution pattern 251 refers to a conductive layer located in the upper insulating layer 253 in a predetermined shape, and can be formed, for example, in a build-up layer manner. Specifically, after forming an insulating layer, unnecessary portions of the insulating layer are removed, and then a conductive layer is formed by a method such as copper plating, and then unnecessary portions of the conductive layer are selectively removed, and then an insulating layer is formed again on the conductive layer, and then unnecessary portions are removed again, and then a conductive layer is formed by plating or other methods, and the above method is repeated, so that an upper distribution pattern 251 having a conductive layer formed in a desired pattern in a vertical or horizontal direction can be formed.

[0121] The upper distribution pattern 251 is located between the core layer 22 and the semiconductor element portion 30, and is therefore formed to include a fine pattern in at least a portion thereof, so as to smoothly transmit electrical signals with the semiconductor element portion 30 and fully accommodate the required complex pattern. At this time, the fine pattern refers to a pattern whose width and interval are less than 4 μm, or a pattern whose width and interval are less than 3.5 μm, or a pattern whose width and interval are less than 3 μm, or a pattern whose width and interval are less than 2.5 μm, or a pattern whose width and interval are 1 μm to 2.3 μm, respectively (hereinafter, the description of the fine pattern is the same).

[0122] The upper connection layer 27 includes an upper connection pattern 272 , at least a portion of which is electrically connected to the upper distribution pattern 251 and is located on the upper insulating layer 253 ; and an upper connection electrode 271 , which electrically connects the semiconductor element portion 30 and the upper connection pattern 272 .

[0123] The upper connection pattern 272 may be located on one side of the upper insulating layer 253, or may be embedded in a manner that at least a portion thereof is exposed on the upper insulating layer. For example, in the case where the upper connection pattern is located on one side of the upper insulating layer, the upper insulating layer may be formed by plating or the like, and in the case where the upper connection pattern is embedded in a manner that a portion thereof is exposed on the upper insulating layer, after forming a copper plating layer or the like, a portion of the insulating layer or the conductive layer may be removed by surface polishing, surface etching or the like.

[0124] Similar to the upper distribution pattern 251 described above, at least a portion of the upper connection pattern 272 may include a fine pattern. The upper connection pattern 272 including the fine pattern as described above allows more components to be electrically connected even in a narrow area, thereby making the electrical signal connection between components or with the outside smoother and enabling a more integrated package to be realized.

[0125] The upper surface connection electrode 271 may be directly connected to the semiconductor element portion 30 through a terminal or the like, or may be connected via an element connection portion 51 such as a solder ball or the like.

[0126] The cavity portion 28 may include a cavity distribution layer 282 and an inner space 281 . The cavity distribution layer 282 is located above and / or below the second region 222 and is electrically connected to the core distribution pattern 241 . The cavity element 40 is located in the inner space 281 .

[0127] Specifically, the thickness of the glass substrate 21 in the second region 222 is thinner than that in the first region 221, and the cavity element 40 can be located in the inner space 281 formed due to the thickness difference. In addition, the core through hole 23 and the core distribution layer 24 formed in the glass substrate 21 play a role of an electrical connection structure connecting the cavity element 40 and external elements.

[0128] In addition, as described above, a cavity portion in the form of penetrating the first region 221 instead of the second region 222 , ie, penetrating the first surface 213 and the second surface 214 of the glass substrate 1 may be formed, and the cavity element 40 may be arranged in the cavity portion.

[0129] The package substrate 20 is also connected to the motherboard 10. The terminals of the motherboard 10 can be directly connected to the core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22, and the motherboard 10 can be electrically connected via a board connection portion 52 such as a solder ball. In addition, the core distribution pattern 241 connected to the motherboard 10 can be connected to the motherboard 10 via a lower layer (not shown in the figure) located at the lower part of the core layer 22.

[0130] According to an example, except for the glass substrate 21 , the package substrate 20 between the semiconductor element portion 30 and the motherboard 10 may not substantially use any other additional substrate.

[0131] In the past, an interposer and an organic substrate were stacked together and applied to the connection portion between the element and the motherboard. It is understood that this multi-level structure is adopted for at least two reasons. One is that there are dimensional problems when directly bonding the fine pattern of the element to the motherboard, and the other is that during the bonding process or the driving process of the semiconductor device, the wiring may be damaged due to the difference in thermal expansion coefficient. In this embodiment, the above-mentioned problem is solved by applying a glass substrate having a thermal expansion coefficient similar to that of the semiconductor element and forming a fine pattern having a fine size sufficient for mounting the element on the first surface and the upper layer of the glass substrate.

[0132] A method of manufacturing a package substrate according to an embodiment of the present invention will be described below.

[0133] Figure 4 and Figure 5 FIG. 1 is a flow chart illustrating a manufacturing process of a package substrate according to the present embodiment in cross section.

[0134] First, if Figure 4 As shown in part (a), a glass substrate 21a having a flat first surface and a flat second surface is prepared, and a defect 21b (groove) is formed at a predetermined position on the glass surface in order to form a core through hole. The above-mentioned glass substrate can be a glass substrate suitable for a substrate of an electronic device, for example, an alkali-free glass substrate, etc., but the present invention is not limited to this. As a commercial product, products manufactured by manufacturers such as Corning, Schott, and AGC can be used. The above-mentioned defect (groove) can be formed by mechanical etching, laser irradiation, etc.

[0135] like Figure 4 As shown in part (b) of FIG. 1 , an etching step is performed to form a core through hole 23 in the glass substrate 21a having a defect 21b (groove) formed therein by a physical or chemical etching process. During the etching process, while the core through hole is formed in the defective portion of the glass substrate, the surface of the glass substrate 21a may also be etched. In order to prevent the etching of the glass surface, a mask film or the like may be applied, but considering the trouble of applying and removing the mask film, etc., the defective glass substrate itself may be etched, in which case the thickness of the glass substrate having the core through hole may be slightly thinner than the thickness of the original glass substrate.

[0136] Then, if Figure 4 As shown in parts (c) and (d) of FIG. 2 , the core layer manufacturing step can be performed by forming a conductive layer 21d on a glass substrate. Typically, the conductive layer can be a metal layer including copper metal, but the present invention is not limited thereto.

[0137] The surface of the glass (including the surface of the glass substrate and the surface of the core through hole) and the surface of the copper metal have different properties, so the adhesion is poor. In this embodiment, the adhesion between the glass surface and the metal is improved by two methods, a dry method and a wet method.

[0138] The dry method is a method for applying sputtering, that is, a method for forming a seed layer 21c on the glass surface and the inner diameter of the core through hole by metal sputtering. When forming the above-mentioned seed layer, a dissimilar metal such as titanium, chromium, nickel, etc. can be sputtered together with copper, etc. In this case, it is believed that the adhesion between glass and metal is improved by the surface morphology of the glass and the anchoring effect of the interaction of metal particles.

[0139] Wet method is the method for carrying out primer treatment, is the method for forming primer layer 21c by pre-treating with the compound substance with the functional group such as amine etc. According to the required adhesion degree, after pre-treating with silane coupling agent, primer treatment can be carried out with the compound or particle with amine functional group.As mentioned above, the support substrate of present embodiment needs to have the high performance of the degree that is enough to form fine pattern, even after primer treatment, also need to keep this state.Therefore, when this primer comprises nanoparticle, preferably suitable average diameter is the nanoparticle below 150nm, for example, the particle with amine group is preferably used as nanoparticle.For example, above-mentioned primer layer can be formed by being suitable for the adhesion improver made by the CZ series etc. of MEC company.

[0140] In the seed layer / primer layer 21c, the conductive layer can selectively form a metal layer with or without removing the portion where the conductive layer is not required to be formed. In addition, the seed layer / primer layer 21c selectively processes the portion where the conductive layer is required to be formed or the portion where the conductive layer is not required to be formed into an activated state or an inactivated state for metal plating to carry out subsequent processes. For example, the activation or inactivation treatment can use a light irradiation treatment or chemical treatment with a laser having a predetermined wavelength. When forming the metal layer, a copper plating method suitable for manufacturing semiconductor elements can be used, but the present invention is not limited thereto.

[0141] like Figure 4 As shown in part (e), when a portion of the core distribution layer is not needed, it can be removed, or metal plating can be performed after partially removing or inactivating the seed layer to form a conductive layer in a predetermined pattern, thereby forming an etching layer 21e of the core distribution layer.

[0142] Figure 5 A manufacturing step of forming an insulating layer and an upper distribution pattern according to one embodiment is described.

[0143] like Figure 5As shown in part (a), after forming the core distribution layer as the above-mentioned conductive layer, the core through hole can be subjected to an insulating layer forming step of filling the empty space with an insulating layer. At this time, the insulating layer applied can be an insulating layer manufactured in the form of a film, for example, it can be applied by a method of decompressing and laminating an insulating layer in the form of a film, etc. When decompressing and laminating in this way, the insulating layer is fully sunken into the empty space inside the above-mentioned core through hole to form a core insulating layer without void formation.

[0144] Figure 5 Parts (b) to (e) of FIG. 1 illustrate the upper layer manufacturing steps.

[0145] The upper layer manufacturing step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer can be formed by coating a resin composition for forming the insulating layer 23a or by stacking insulating films. Simply, it is preferred to stack insulating films. The stacking of insulating films can be performed by laminating insulating films and curing. At this time, if a reduced pressure lamination method is adopted, the insulating resin can be fully immersed in a layer where no conductive layer is formed inside the core through hole, etc. At least a portion of the above-mentioned upper insulating layer is also in direct contact with the glass substrate, so a layer with sufficient adhesion is suitable. Specifically, the above-mentioned glass substrate and the above-mentioned upper insulating layer preferably have a characteristic that the adhesion test value according to ASTM D3359 meets 4B or above.

[0146] The upper distribution pattern can be formed by repeatedly forming the above-mentioned insulating layer 23a, forming the conductive layer 23c in a predetermined pattern and etching unnecessary parts to form an etching layer 23d of the conductive layer, and the conductive layer formed adjacent to each other through the insulating layer is formed by performing a plating process after forming the blind hole 23b in the insulating layer. The blind hole can be formed by a dry etching method such as laser etching and plasma etching, a wet etching method using a mask layer and an etching solution, etc.

[0147] Thereafter, although not shown in the drawings, an upper connection layer and a cover layer may be formed.

[0148] The upper connection pattern and the upper connection electrode can also be formed by a process similar to the process of forming the upper distribution layer. Specifically, it can be formed by forming an etching layer of the insulating layer on the insulating layer 23e, and then forming a conductive layer thereon, and then forming an etching layer of the conductive layer, but it can also be formed by selectively forming only the conductive layer without using an etching method. An opening portion (not shown in the figure) is formed at a position corresponding to the upper connection electrode of the covering layer so that the upper connection electrode is exposed and directly connected to the element connection portion or the terminal of the element.

[0149] Once the upper layer is generated, the process of generating the lower layer by forming the lower connecting layer and the covering layer can be carried out. The lower distribution layer and / or the lower connecting layer can be formed in a similar manner to the upper connecting layer and the covering layer formation steps described above, and optionally, a covering layer (not shown in the figure) can also be formed.

[0150] As described above, the cavity element may be formed in the insulating layer by laminating an insulating film (e.g., Ajinomoto built-up film (ABF)), in which case the undulation phenomenon may occur. In particular, the undulation phenomenon in the cavity portion where the element is embedded may become serious due to the gap between the elements and / or the gap between the cavity portion and the element, etc. If the undulation phenomenon becomes serious, leakage current may occur in the cavity portion, which may be fatal to active elements, etc., which are susceptible to leakage current.

[0151] In addition, when a cavity element is arranged in a cavity portion having an electrode formed on the inner surface, or when a plurality of cavity elements are arranged in the cavity portion, the accuracy of the arrangement position may be reduced, or defects may occur due to substrate bending that occurs unintentionally during the manufacturing process. For example, due to the nature of elements in which electrodes are exposed between adjacent elements and / or between elements and electrodes, short circuits may occur due to contact with each other, which causes defects in the package substrate.

[0152] Therefore, the present specification proposes an embodiment that achieves the purpose of preventing the occurrence of undulation in the cavity of the embedded element to improve the effect of preventing leakage current and reduce defects in the package substrate. For example, according to one embodiment of the present specification, a process of forming an insulating layer by performing multiple times instead of once is proposed.

[0153] Figure 6 FIG. 4 is an example of a cross-sectional structure of a core layer of a package substrate produced according to this embodiment. Figure 6 is a diagram showing a package substrate conceptually simplified for explaining a core layer generated according to the present embodiment, and can be applied to reference Figures 1 to 3 The content of the description.

[0154] For example, the core layer 22 may include a glass substrate 21 having a first surface and a second surface facing each other and a core through hole penetrating the glass substrate 21. The electrode 63 may be formed on the surface of the glass substrate 21.

[0155] In addition, for example, Figure 6 The cavity portion 28 shown is formed to penetrate the first surface and the second surface of the glass substrate 21, and the cavity element 40 is arranged inside the cavity portion 28. As described above, the cavity element 40 may include both passive elements and active elements.

[0156] The cavity portion 28 may be formed simultaneously through the same forming step as the above-mentioned core through hole, or may be formed independently after forming the above-mentioned core through hole or before forming the above-mentioned core through hole.

[0157] In addition, if Figure 6 All surfaces except one surface or all surfaces of the cavity element 40 arranged inside the cavity portion 28 as shown may be surrounded by the first insulating layer 61. That is, for example, in Figure 6 The cavity portion shown may be provided with a cavity element 40, and the first insulating layer 61 may be formed on all surfaces except one surface or all surfaces of the cavity element 40. The cavity element and the first insulating layer surrounding the cavity element are collectively referred to as a cavity module.

[0158] For example, when the cavity element 40 has a hexahedral shape, five surfaces of the cavity element 40 except one surface (e.g., the bottom surface) may be surrounded by the first insulating layer 61. Alternatively, the edge of the upper surface of the cavity element 40 may be surrounded by the first insulating layer 61. In other words, the first insulating layer 61 may be formed at the edge of the upper surface of the cavity element 40.

[0159] For example, when the cavity element 40 has a cylindrical shape, the side surface and / or the upper surface of the cavity element 40 except the bottom surface may be surrounded by the first insulating layer 61. Alternatively, the edge of the upper surface of the cavity element 40 may be surrounded by the first insulating layer 61. In other words, the first insulating layer 61 may be formed at the edge of the upper surface of the cavity element 40.

[0160] For example, one or more connection electrodes may be formed in the bottom surface direction of the cavity element 40. Alternatively, for example, five surfaces of the cavity element 40 except the upper surface may be surrounded by the first insulating layer 61. Alternatively, for example, the edge of the bottom surface of the cavity element 40 may be surrounded by the first insulating layer 61. In other words, the first insulating layer 61 may be formed at the edge of the bottom surface of the cavity element 40. In this case, for example, one or more connection electrodes may be formed in the upper surface direction of the cavity element 40.

[0161] The first insulating layer 61 is formed on all surfaces except one surface of the cavity element 40, thereby preventing a short circuit caused by contact between the cavity elements arranged side by side. In addition, by forming the first insulating layer 61 on all surfaces except one surface of the cavity element 40 or on all surfaces of the cavity element 40, a short circuit that may be unintentionally generated during the manufacturing process of forming a conductive layer on the side of the cavity portion 28 can be prevented.

[0162] In addition, if Figure 6 The core layer 22 shown may include a second insulating layer 62 stacked on the first surface and the second surface. Figure 6 The remaining portion of the cavity portion 28 shown except for the cavity element 40 and the first insulating layer 61 may be filled with the second insulating layer 62 .

[0163] That is, after the cavity module is arranged in the cavity portion 28, there may be a remaining space inside the cavity portion, and the second insulating layer 62 may be formed therein. Figure 6 The core layer 22 shown may include a second insulating layer 62, which is sunken into the remaining portion of the cavity portion 28 except for the cavity module. For example, the second insulating layer 62 may be laminated and cured on the upper portion (e.g., first surface) of the glass substrate 21 and the lower portion (e.g., second surface) of the glass substrate 21, thereby generating a second insulating layer.

[0164] The cavity element 40 may be connected to a connection electrode.

[0165] The connection electrode may be disposed on an exposed surface of the cavity element 40 on which the first insulating layer 61 is not disposed.

[0166] The connection electrode may be arranged to penetrate the first insulating layer 61 of the above-mentioned cavity element 40. The connection electrode may have a blind hole form.

[0167] The first insulating layer may also be provided with a first insulating layer through hole (not shown in the figure) penetrating the first insulating layer. A part or all of the first insulating layer through hole may be filled with electrode material.

[0168] One end of the first insulating layer through hole may be in contact with the cavity element 40 , and the other end of the first insulating layer through hole may be exposed to the outside of the cavity portion 28 .

[0169] The first insulating layer through hole may be arranged in a shape that vertically penetrates the cavity portion 28 without directly contacting the cavity element 40 .

[0170] As the electrode material, a conductive material may be used, for example, a conductive metal may be used, specifically, copper, a copper alloy, silver, etc. may be used, but the present invention is not limited thereto.

[0171] The first insulating layer 61 and the second insulating layer 62 may be made of the same material or different materials. In the latter case, materials having different dielectric constants may be used.

[0172] For example, the first insulating layer 61 and the second insulating layer 62 may have different dielectric constants. For example, the dielectric constant of the first insulating layer 61 may be equal to or lower than the dielectric constant of the second insulating layer 62. In this case, there is an advantage that a sufficient insulating effect can be expected for each cavity element while substantially suppressing the occurrence of the undulation phenomenon in the cavity portion.

[0173] The first insulating layer 61 and the second insulating layer 62 may include insulating materials respectively.

[0174] Illustratively, the above-mentioned insulating material may be a polymer resin, a mixed material of a polymer resin and a filler (inorganic particles, organic particles, organic-inorganic composite particles, etc.), an inorganic deposition layer, etc.

[0175] For example, the polymer resin may be an acrylic resin, an epoxy resin or a modified resin thereof, and may be a material suitable for electronic devices for the purpose of molding, etc. For example, a liquid crystal polymer (LCP) may be used.

[0176] Exemplarily, the mixed material may be a mixture of acrylic resin and filler, a mixture of acrylic resin and epoxy resin and a mixture of filler, and a mixture of epoxy resin and filler. The filler may be an inorganic particle, for example, silica particles. As a commercial product, Ajinomoto deposited film (ABF), epoxy molding compound (EMC), modified polyimide (MPI), etc. may be used, but the present invention is not limited thereto.

[0177] Illustratively, the inorganic deposition layer may be a silicon oxide deposition layer or a silicon nitride deposition layer, etc., but the present invention is not limited thereto.

[0178] The first insulating layer 61 and the second insulating layer 62 may be made of materials having the same or different coefficients of thermal expansion (CTE). Preferably, a material having a smaller difference in CTE between the first insulating layer 61 and the second insulating layer 62 may be used.

[0179] The difference in thermal expansion coefficient between the material of the first insulating layer and the material of the second insulating layer may be 2 ppm / °C or less, 1.5 ppm / °C or less, 1 ppm / °C or less, or 0.5 ppm / °C or less. The difference in thermal expansion coefficient may be 0 ppm / °C or more, 0.1 ppm / °C or more, or 0.2 ppm / °C or more.

[0180] The thermal expansion coefficient of the first insulating layer 61 may be greater than 8 ppm / °C, greater than 10 ppm / °C, greater than 12 ppm / °C, or greater than 14 ppm / °C. The thermal expansion coefficient may be less than 20 ppm / °C, less than 18 ppm / °C, or less than 17 ppm / °C.

[0181] The thermal expansion coefficient of the second insulating layer 62 may be greater than 8 ppm / °C, greater than 10 ppm / °C, or greater than 12 ppm / °C, or less than 20 ppm / °C, less than 18 ppm / °C, less than 16 ppm / °C, or less than 14 ppm / °C.

[0182] The first insulating layer 61 and the second insulating layer 62 may be made of materials with different dielectric constants. Preferably, the materials of the insulating layers may be selected so that the dielectric constant of the first insulating layer 61 is lower than the dielectric constant of the second insulating layer 62.

[0183] The first insulating layer 61 and the second insulating layer 62 are preferably made of materials having different relative dielectric constants Dk at a high frequency of 5.8 GHz. For example, the difference between the Dk of the first insulating layer 61 and the Dk of the second insulating layer 62 may be greater than 0.1. The difference in Dk may be greater than 0.1, greater than 0.13, greater than 0.16, or greater than 0.2. The difference in Dk may be less than 1, less than 0.8, less than 0.6, less than 0.5, less than 0.4, less than 0.3, or less than 0.25.

[0184] The Dk of the first insulating layer 61 may be greater than or equal to 2.3, greater than or equal to 2.5, greater than or equal to 2.7, or greater than or equal to 2.9. The Dk may be less than or equal to 3.4, less than or equal to 3.2, or less than or equal to 3.1.

[0185] The Dk of the second insulating layer 62 may be greater than or equal to 3.0, greater than or equal to 3.1, or greater than or equal to 3.2. The Dk may be less than or equal to 3.6, less than or equal to 3.5, or less than or equal to 3.4.

[0186] The Dk of the first insulating layer 61 may be smaller than the Dk of the second insulating layer 62 .

[0187] The first insulating layer 61 and the second insulating layer 62 may be made of materials with the same or different dielectric loss factors Df. For example, a material in which the difference between the Df of the first insulating layer 61 and the Df of the second insulating layer 62 is 0.0001 or more may be used. The difference in Df may be 0.0001 or more, 0.0005 or more, or 0.001 or more. The difference in Df may be 0.02 or less.

[0188] The Df of the first insulating layer 61 may be 0.004 or less, 0.0038 or less, or 0.0036 or less. The Df may be 0.001 or more, 0.0015 or more, 0.0018 or more, or 0.002 or more.

[0189] The Df of the second insulating layer 62 may be 0.005 or less, 0.0048 or less, or 0.0046 or less. The Df may be 0.003 or more, 0.0032 or more, or 0.0034 or more.

[0190] The Df of the first insulating layer 61 may be smaller than the Df of the second insulating layer 62 .

[0191] For example, the second insulating layer 62 may be ABF, and the first insulating layer 61 may be LCP. For example, the second insulating layer 62 may be EMC, and the first insulating layer 61 may be LCP. For example, ABP having different dielectric constants may be applied to the second insulating layer 62 and the first insulating layer 61.

[0192] Regarding the formation of the first insulating layer 61 , as an example, an insulating layer may be formed on the surface of the cavity element 40 by applying a varnish type method, a selective lamination method, or a deposition method.

[0193] For the second insulating layer 62 , a common method of forming an insulating layer in a cavity of a package substrate may be applied, or a method applied in the formation of the first insulating layer 61 may be applied.

[0194] In addition, this specification proposes a method for generating Figure 6 A method for manufacturing a packaging substrate according to an embodiment disclosed in the disclosure.

[0195] For example, the following method for manufacturing a package substrate may be proposed: preparing a glass substrate 21 provided with a cavity portion 28 and a pre-processed cavity element 40, arranging the cavity element 40 in the cavity portion 28, and laminating a second insulating layer 62 on the glass substrate, wherein the first insulating layer 61 is formed on all surfaces except one surface of the cavity element 40 or on all surfaces of the cavity element 40. In addition, for example, the first insulating layer 61 and the second insulating layer 62 may have different dielectric constants.

[0196] Specifically, this specification proposes an example of generating a packaging substrate according to the following implementations.

[0197] As an embodiment, the following method may be proposed: before selecting and arranging the cavity element, a primary insulating layer is arranged on the cavity element (manufacturing of the cavity module); then, the cavity module is located in the cavity, and a second insulating layer is formed through a redistribution layer (RDL) process.

[0198] Figure 7 FIG. 1 is a flowchart for explaining an example of a method for manufacturing a package substrate according to the present embodiment in cross section.

[0199] The following will be Figure 7 The steps of forming the first insulating layer and the second insulating layer on the package substrate are described in more detail.

[0200] For example, Figure 7 As shown in part (a) of FIG. 1 , the first insulating layer 61 may be formed on a portion of the surface of the cavity element 40 except the upper surface or the bottom surface (step S). For example, the first insulating layer 61 may be formed on a portion of the surface of the cavity element 40 except the upper surface or the bottom surface by performing a sputtering, coating, or molding process on the cavity element 40.

[0201] In other words, part of the surface of the cavity element 40 except the upper surface or the bottom surface may be surrounded by the first insulating layer 61. For example, the five surfaces of the cavity element 40 except the bottom surface may be surrounded by the first insulating layer 61. Or, for example, the edge of the upper surface of the cavity element 40 may be surrounded by the first insulating layer 61. In other words, the first insulating layer 61 may be formed at the edge of the upper surface of the cavity element 40. In this case, for example, one or more connection electrodes may be formed in the bottom surface direction of the cavity element 40. Or, for example, the five surfaces of the cavity element 40 except the upper surface may be surrounded by the first insulating layer 61. Or, for example, the edge of the bottom surface of the cavity element 40 may be surrounded by the first insulating layer 61. In other words, the first insulating layer 61 may be formed at the edge of the bottom surface of the cavity element 40. In this case, for example, one or more connection electrodes may be formed in the upper surface direction of the cavity element 40.

[0202] The first insulating layer 61 is formed on a portion of the surface of the cavity element 40 other than the upper surface or the bottom surface, thereby preventing a short circuit caused by contact between the cavity elements arranged side by side. In addition, the first insulating layer 61 formed on a portion of the surface of the cavity element 40 other than the upper surface or the bottom surface can prevent a short circuit from being accidentally generated during the manufacturing process of forming a conductive layer on the side surface of the cavity portion 28. Since the specific description related to the formation of the first insulating layer in the cavity element is repeated in the above description, part of the description will be omitted.

[0203] The cavity element 40 may include a passive element and / or an active element. For example, a multilayer ceramic capacitor (MLCC) may be used as the cavity element 40. Alternatively, for example, an active element other than a passive element such as an MLCC may be used as the cavity element 40. In addition, for example, the first insulating layer 61 may include a liquid crystal polymer (LCP), an epoxy molding compound (EMC), an Ajinomoto deposited film (ABF), and / or a modified polyimide (MPI) described above.

[0204] Afterwards, if Figure 7 As shown in part (b), the glass substrate 21 can be attached to an adhesive film such as a polyimide tape (PI tape), and the cavity element 40 formed with the first insulating layer 61 can be selected and arranged by the cavity portion 28 (step P1, specifying the cavity unit position).

[0205] Next, if Figure 7 As shown in part (c) of FIG. 1 , a second insulating layer 62 may be laminated on the first surface (Lamination on top) (step P2). The second insulating layer 62 may be laminated on the entire first surface of the glass substrate 21. When curing (pre-curing) is performed, as shown in FIG. Figure 7 As shown in part (d) of FIG. 2 , the second insulating layer 62 may be sunken into the inner space of the cavity 28. For example, the second insulating layer 62 may include an insulating mixture, and the insulating mixture may include inorganic particles and a polymer resin. For example, the second insulating layer 62 may include the epoxy molding compound (EMC) and / or the Ajinomoto build-up film (ABF) described above.

[0206] The adhesive film may be removed in a subsequent process as needed. For example, the adhesive film may be an adhesive film whose adhesive force may be reduced due to ultraviolet irradiation or the like. The adhesive force of the adhesive film is reduced by irradiating ultraviolet light directly or through the glass substrate, and the adhesive film can be easily removed from the glass substrate. In addition, the position of the cavity element can be fixed by curing the pre-cured second insulating layer, and if the degree of bending is controlled below a certain level, it can be applied to the subsequent process without fixing the adhesive film.

[0207] Next, if Figure 7 As shown in part (e) of FIG. 1 , a second insulating layer 62 may be laminated on the second surface (Lamination on bottom) (step P3). The second insulating layer 62 may be laminated on the entire second surface of the glass substrate 21. When curing (pre-curing) is performed, as shown in FIG. Figure 7As shown in part (f) of FIG. 1 , the second insulating layer 62 may be sunken into the inner space of the cavity portion 28 (step P4 ).

[0208] Therefore, according to Figure 7 As an embodiment, a method for manufacturing a packaging substrate can be proposed, wherein a core through hole is formed in a glass substrate 21 including a first surface and a second surface facing each other, and a cavity portion 28 is formed that penetrates the first surface and the second surface of the glass substrate 21; a cavity module having a first insulating layer 61 formed on all surfaces except one surface of a cavity element 40 or on all surfaces of the cavity element 40 is arranged in the cavity portion 28; and a second insulating layer 62 is stacked on the first surface and the second surface.

[0209] As an embodiment, a method for manufacturing a packaging substrate can be proposed, which comprises forming a core through hole in a glass substrate 21 including a first surface and a second surface facing each other, and forming a cavity portion 28 penetrating the first surface and the second surface of the glass substrate 21; forming a first insulating layer 61 on all surfaces of the cavity element 40 except one surface or on all surfaces of the cavity element 40; arranging the cavity elements 40 having the first insulating layer 61 formed on all surfaces of the cavity portion 28 except one surface or on all surfaces of the cavity portion 28; and stacking a second insulating layer 62 on the first surface and the second surface.

[0210] As another embodiment, the following method may be proposed: a cavity element is selected and arranged in a cavity; then, a first insulating layer is coated (or arranged) on the cavity element, and the first insulating layer coated on a specific surface (e.g., the top or bottom surface) of the cavity element is etched, followed by a re-distribution layer (RDL) process to form a second insulating layer.

[0211] Figure 8 FIG. 1 is a flow chart illustrating a method for manufacturing a package substrate according to another embodiment of the present invention in cross section.

[0212] The following will be Figure 8 The steps of forming the first insulating layer and the second insulating layer on the package substrate are described in more detail.

[0213] For example, Figure 8As shown in part (a) of FIG. 2 , the glass substrate 21 may be attached to an adhesive film such as a polyimide tape (PI tape), and the cavity element 40 may be selected and arranged in the cavity portion 28 (P1). The cavity element 40 may include a passive element and / or an active element. For example, a multilayer ceramic capacitor (MLCC) may be used as the cavity element 40. Alternatively, for example, an active element other than a passive element such as an MLCC may be used as the cavity element 40.

[0214] Afterwards, if Figure 8 As shown in part (b) of the embodiment, the first insulating layer 61 may be formed on a partial surface of the cavity element 40 arranged in the cavity portion 28 except for the upper surface or the bottom surface (step S). For example, the first insulating layer 61 may be formed on a partial surface of the cavity element 40 except for the upper surface or the bottom surface by performing a sputtering, coating or molding process on the cavity element 40 in the cavity portion 28. A partial surface of the cavity element 40 arranged in the cavity portion 28 except for the upper surface or the bottom surface may be surrounded by the first insulating layer 61. For example, five surfaces of the cavity element 40 except for the upper surface may be surrounded by the first insulating layer 61. Or, for example, the edge of the upper surface of the cavity element 40 may be surrounded by the first insulating layer 61. In other words, the first insulating layer 61 may be formed at the edge of the upper surface of the cavity element 40. In this case, for example, one or more connection electrodes may be formed in the bottom surface direction of the cavity element 40. Or, for example, five surfaces of the cavity element 40 except for the upper surface may be surrounded by the first insulating layer 61. Alternatively, for example, the edge of the bottom surface of the cavity element 40 may be surrounded by the first insulating layer 61. In other words, the first insulating layer 61 may be formed at the edge of the bottom surface of the cavity element 40. In this case, for example, one or more connection electrodes may be formed in the upper direction of the cavity element 40.

[0215] The first insulating layer 61 is formed on all surfaces except one surface of the cavity element 40, thereby preventing short circuits caused by contact between the cavity elements arranged side by side. In addition, the first insulating layer 61 formed on a portion of the surface of the cavity element 40 except the upper surface or the bottom surface can prevent short circuits that are unintentionally generated during the manufacturing process of forming a conductive layer on the side surface of the cavity portion 28.

[0216] The first insulating layer 61 may include the above-mentioned liquid crystal polymer (LCP), epoxy molding compound (EMC), Ajinomoto deposited film (ABF) or modified polyimide (MPI). A more detailed description of the cavity element and the first insulating layer overlaps with the above description, so the detailed description will be omitted.

[0217] Next, if Figure 8 As shown in part (c) of FIG. 1 , a second insulating layer 62 may be laminated on the first surface (Lamination on top) (step P2). The second insulating layer 62 may be laminated on the entire first surface of the glass substrate 21. When curing (pre-curing) is performed, as shown in FIG. Figure 8 As shown in part (d) of FIG. 2 , the second insulating layer 62 may be sunken into the inner space of the cavity portion 28. For example, the second insulating layer 62 may include an insulating mixture, and the insulating mixture may include inorganic particles and a polymer resin. For example, the second insulating layer 62 may include the Ajinomoto stacked film (ABF) described above. Since the specific description of each insulating layer is repeated in the above content, the detailed description will be omitted.

[0218] The adhesive film may be removed in a subsequent process as needed. For example, the adhesive film may be an adhesive film whose adhesive force may be reduced due to ultraviolet irradiation or the like. The adhesive force of the adhesive film may be reduced by irradiating ultraviolet light directly or through the glass substrate, and the adhesive film may be easily removed from the glass substrate. In addition, the position of the cavity element may be fixed by curing the pre-cured second insulating layer, and if the degree of bending is controlled below a certain level, it may be suitable for subsequent processes without fixing the adhesive film.

[0219] Next, if Figure 8 As shown in part (e) of FIG. 1 , a process of laminating the second insulating layer 62 on the second surface (Lamination on bottom) (step P3) may be performed. The second insulating layer 62 may be laminated on the entire second surface of the glass substrate 21, and when curing (pre-curing) is performed, as shown in FIG. Figure 8 As shown in part (f) of FIG. 1 , the second insulating layer 62 may be sunken into the inner space of the cavity portion 28 (step P4 ).

[0220] Therefore, according to Figure 8 As an embodiment, a method for manufacturing a packaging substrate can be proposed, which includes forming a core through hole in a glass substrate 21 including a first surface and a second surface facing each other, and forming a cavity portion 28 that penetrates the first surface and the second surface of the glass substrate 21; arranging cavity elements 40 in the above-mentioned cavity portion 28, and forming a first insulating layer 61 on a portion of the surface of the arranged cavity elements 40 except the bottom surface; and stacking a second insulating layer 62 on the above-mentioned first surface and the above-mentioned second surface.

[0221] The method for manufacturing a package substrate and the package substrate using the same according to the above-described embodiments can prevent the undulation phenomenon caused by the gap between elements and / or the gap between the cavity portion and the element, and can prevent leakage current from occurring in the cavity portion.

[0222] Above, this specification is described with reference to the embodiments illustrated in the accompanying drawings, but this is only an example, and a person skilled in the art should understand that various changes and modifications of the embodiments can be made. In other words, the scope of this specification is not limited to the above-mentioned embodiments, but various changes or modifications made by a person skilled in the art using the basic concepts of the embodiments defined in the attached claims belong to the scope of the embodiments. Therefore, the true technical protection scope of this specification should be determined according to the technical ideas of the attached claims.

Claims

1. A packaging substrate, characterized in that: The core layer includes a glass substrate and a cavity portion, the glass substrate has a first surface and a second surface facing each other, and the cavity portion penetrates the glass substrate. A cavity module is arranged in the cavity portion. The cavity module comprises a cavity element and a first insulating layer surrounding the cavity element. The first insulating layer is arranged on all surfaces except one surface of the cavity element or on all surfaces of the cavity element, The second insulating layer is arranged in a manner of at least partially being embedded in the portion of the cavity portion other than the cavity module. The first insulating layer and the second insulating layer have different dielectric constants.

2. The packaging substrate according to claim 1, characterized in that: The dielectric constant of the first insulating layer is lower than the dielectric constant of the second insulating layer.

3. The packaging substrate according to claim 1, characterized in that: The high-frequency relative dielectric constant Dk is the relative dielectric constant at a high frequency of 5.8Ghz. A difference between a high-frequency relative dielectric constant Dk1 of the first insulating layer and a high-frequency relative dielectric constant Dk2 of the second insulating layer is greater than or equal to 0.

1.

4. The packaging substrate according to claim 1, characterized in that: The dielectric loss rate of the first insulating layer is Df1, The dielectric loss rate of the second insulating layer is Df2, The difference between the above-mentioned Df1 and the above-mentioned Df2 is 0.0001 or more.

5. The packaging substrate according to claim 1, characterized in that: The first insulating layer includes liquid crystal polymer (LCP), epoxy molding compound (EMC), Ajinomoto built-up film (ABF) or modified polyimide (MPI).

6. The packaging substrate according to claim 1, characterized in that: The second insulating layer comprises an insulating mixture. The above-mentioned insulating mixture includes a mixture of inorganic particles and polymer resin.

7. The packaging substrate according to claim 1, characterized in that: The connection electrodes are arranged on the above-mentioned cavity element.

8. The packaging substrate according to claim 1, characterized in that: The above-mentioned cavity components include passive components or active components.

9. The packaging substrate according to claim 1, characterized in that: The first insulating layer is also provided with a first insulating layer through hole penetrating the first insulating layer. A part or all of the through holes in the first insulating layer are filled with electrode materials.

10. A method for manufacturing a packaging substrate, characterized in that: The steps include: preparing a glass substrate having a cavity portion and a cavity module; Arranging the cavity modules in the cavity portion; and Laminating a second insulating layer on the glass substrate; The cavity module comprises a cavity element and a first insulating layer surrounding at least a portion of the cavity element. The first insulating layer is disposed on all surfaces except one surface of the cavity element or on all surfaces of the cavity element.

11. The method for manufacturing a packaging substrate according to claim 10, wherein: The first insulating layer and the second insulating layer have different dielectric constants.

12. The method for manufacturing a packaging substrate according to claim 10, wherein: The first insulating layer includes liquid crystal polymer (LCP), epoxy molding compound (EMC), Ajinomoto built-up film (ABF) or modified polyimide (MPI).

13. The method for manufacturing a packaging substrate according to claim 10, wherein: The second insulating layer includes Ajinomoto built-up film (ABF) or epoxy molding compound (EMC).

14. The method for manufacturing a packaging substrate according to claim 10, wherein: The connection electrode is formed on the above-mentioned cavity member.

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