Serial high-speed interface packaging method and system based on FPGA

Abstract

The invention belongs to the technical field of FPGA ASerDes serial interfaces, and discloses a serial high-speed interface packaging method and system based on an FPGA. A user interface module is designed, and the user interface module is used as a channel for data interaction between a user module and the SRIOIP core; a maintenance module is designed and used for carrying out maintenance operation on the RapidIO device through a read-write transaction; a request module is designed and used for executing a request test sequence, request packet packaging, a request response verification function and response packet analysis; designing a target module for responding to the request transaction packet of the initiating device; an SRIO communication software framework is designed for caching transmission data and solving rate matching of a user clock domain and an SRIO clock domain. According to the method, the use efficiency of the RapidIO bus and the simplicity and convenience of operation are improved, and the use efficiency and the development speed can be improved by packaging according to the method.

Description

Technical Field

[0001] The present invention belongs to the technical field of FPGASerDes serial interface, and in particular relates to a serial high-speed interface packaging method and system based on FPGA. Background Art

[0002] RapidIO bus technology was originally proposed by Freescale and Mercury as an interconnection technology standard based on packet switching technology. It meets the needs of high bandwidth and low latency between internal devices of high-performance embedded systems. Currently, RapidIO bus technology has become the industry standard for communication and interconnection technology between embedded system chips and backplanes.

[0003] Compared with other high-speed bus technologies, the RapidIO serial bus technology has the following characteristics: (1) It has a flexible topology and supports point-to-point and point-to-multipoint communication; (2) It has the characteristics of high bandwidth, high reliability, low latency and few pins; (3) It supports maintenance and error management mechanisms. Based on the above advantages, RapidIO serial bus interconnection technology has been widely used in various industries.

[0004] Through the above analysis, the problems and defects of the existing technology are as follows: the existing technology Xilinx's own SRIOIP and solution have complex peripheral interfaces and many control signals, which are difficult for developers to use and have low development and use efficiency. Summary of the invention

[0005] In order to overcome the problems existing in the related art, the disclosed embodiment of the present invention provides a serial high-speed interface packaging method and system based on FPGA, and specifically relates to a RapidIO interface packaging design method based on FPGAk7 series.

[0006] The technical solution is as follows: a serial high-speed interface packaging method based on FPGA, the method comprising:

[0007] S1, design the user interface module, which is used as a channel for data interaction between the user module and the SRIOIP core;

[0008] S2, designing a maintenance module for performing maintenance operations on RapidIO devices through read and write transactions;

[0009] S3, designing the request module, which is used to execute the request test sequence, request packet encapsulation, request response verification function and execute response packet parsing;

[0010] S4, designing a target module for responding to a request transaction packet of the initiating device;

[0011] S5, design the SRIO communication software framework to cache the transmitted data and solve the rate matching between the user clock domain and the SRIO clock domain.

[0012] Further, in step S1, the user interface module includes:

[0013] The configuration module is responsible for performing maintenance operations and error management on the RapidIO device;

[0014] The request module is responsible for initiating requests and responses to the logic layer according to the needs of the user module. When the RapidIO device acts as a host device, it is responsible for initiating requests and verifying responses.

[0015] When the target module acts as a slave module, it is responsible for generating target requests and checking the corresponding target responses;

[0016] The user module is responsible for sending and receiving RapidIO device control signals and data processing functions; the FIFO buffer is used to complete the rate matching of user data between the user interface and the SRIO IP core.

[0017] Further, in step S2, when a write transaction operation is performed, the address and data are written to the channel of the maintenance port; after the write transaction is executed, the SRIO logic layer receives a response to the corresponding operation;

[0018] When performing a read transaction, the address and command to be read are written; after the read transaction is completed, the SRIO logic layer receives a response to the corresponding operation and receives the read data at the same time.

[0019] Further, in step S2, performing maintenance operations on the RapidIO device through read and write transactions includes:

[0020] S201, first, the user submits a maintenance request for updating or reading the local register of the SRIO endpoint through the maintenance port;

[0021] S202, the logic layer of the local SRIO endpoint forwards the request transaction packet to the configuration structure of the SRIO endpoint;

[0022] S203, the configuration structure parses the address of the current maintenance request, and forwards the transaction to the corresponding configuration register according to the parsed request address;

[0023] S204, after the read or update operation is performed on the local configuration register, the configuration register generates a response and returns it to the configuration structure;

[0024] S205, after the configuration structure receives the response sent by the configuration register, the configuration structure forwards the response to the logic layer of the SRIO endpoint;

[0025] S206, after receiving the response, the logic layer of the SRIO endpoint parses the information in the packet and transmits it to the corresponding channel.

[0026] Further, in step S3, the request module is composed of a request test sequence module, a request packet encapsulation module, a request response verification module, and a response packet parsing module;

[0027] The request test sequence module generates a test instruction sequence and sends NWRITE, SWRITE and other test transaction requests to the target device according to the requirements;

[0028] The request packet encapsulation module classifies the reconstruction configuration file data and the reconstruction waveform number according to the RapidIO packet format according to the RapidIO transaction type, and sends the packet to the logic layer of the local endpoint through the AXI4-Stream interface;

[0029] The request response verification module is responsible for verifying the information of the request that needs to return a response and checking whether the returned response is correct;

[0030] The response packet parsing module is responsible for parsing the received response transaction packet, and then obtaining the status information and reading data in the response packet.

[0031] Further, in step S4, the target module is composed of a target device automatic return response module, a target device request packet parsing module and a target device response packet encapsulation module;

[0032] The target device request packet parsing module parses the transaction packet received by the target device, parses the reconstructed data and the reconstructed waveform number and stores them in the FIFO cache;

[0033] The target device automatic return response module generates a response corresponding to the request transaction according to the information provided by the target device request packet parsing module;

[0034] The target device response packet encapsulation module frames the response generated by the target device automatic return response module, and then transmits the response to the SRIO logic layer through the AXI4-Stream interface.

[0035] Further, in step S5, the SRIO communication software framework includes a request module, a target module, an SRIO IP core, a send FIFO module and a receive FIFO module;

[0036] The request module code and the target module code are automatically generated when the SRIO IP core is generated. The send FIFO module and the receive FIFO module cache the transmission data and complete the rate matching between the user clock domain and the SRIO clock domain.

[0037] Further, the sending FIFO module realizes the caching of the sending data and the rate matching of the sending end clock domain and the SRIO clock domain by calling the asynchronous FIFO; the asynchronous FIFO in the sending FIFO module instantiates the FIFOIP core inside the FPGA, sets the input bit width, output bit width, depth, write clock, and read clock; the instantiation of the sending FIFO module specifically includes:

[0038] When the FIFO write enable signal send_wr_en is high, the write data send_din is written into the FIFO in synchronization with the send_clk clock;

[0039] When the FIFO read enable signal send_rd_en is high, the data send_dout is read from the FIFO;

[0040] When the initialization signal, data valid signal and SRIOIP core ready signal are valid at the same time, the link initialization and transmission path handshake are successful, and the send_rd_en signal is high. When the data packet sending completion signal is pulled high, send_rd_en becomes low.

[0041] When writing configuration data to FIFO, pull send_wr_en high. If FIFO is full or data writing is completed, pull send_wr_en low.

[0042] Further, the receiving FIFO module caches the configuration data parsed from the data packet in an asynchronous FIFO. The asynchronous FIFO in the receiving FIFO module instantiates the FIFOIP core inside the FPGA, sets the input bit width, output bit width, depth, write clock, and read clock; the instantiated sending FIFO module includes:

[0043] When the channel handshake is detected to be successful and a data packet arrives, receive_wr_en becomes high level, and the valid data receive_din parsed from the data packet is written into the FIFO; when the FIFO is not empty and the read enable receive_rd_en is high level, the data is read from the FIFO;

[0044] In SRIO communication, the parsed test data is verified; on the premise that the SRIO interface transmission test data is verified to be correct and SRIO stable communication is achieved, the configuration data is transmitted, and the valid data parsed from the data packet is stored in the FIFO, thereby realizing the function of the SRIO interface to transmit configuration data.

[0045] Another object of the present invention is to provide a serial high-speed interface packaging system based on FPGA, comprising:

[0046] User interface module, used for the channel for data interaction between user module and SRIOIP core;

[0047] A maintenance module, used to perform maintenance operations on RapidIO devices through read and write transactions;

[0048] The request module is used to execute the request test sequence, request packet encapsulation, request response verification function and execute response packet parsing;

[0049] The target module is used to respond to the request transaction packet of the initiator device;

[0050] SRIO communication software framework, used to cache transmission data and solve the rate matching between the user clock domain and the SRIO clock domain.

[0051] Combining all the above technical solutions, the beneficial effects of the present invention are as follows: RapidIO interconnection architecture can meet the requirements of high-performance embedded industry, and it adopts a three-layer hierarchical system interface, namely, a logical layer, a transport layer and a physical layer. The three-layer hierarchical system architecture improves the flexibility and scalability of the RapidIO interconnection system.

[0052] In order to use the serial bus more efficiently, it is necessary to conduct in-depth research and implementation of the serial RapidIO bus interface. Based on the Xilinx SRIOGen2.0 EndPoint solution, the present invention designs and implements a serial RapidIO bus interface implementation scheme. Xilinx's own SRIO IP and solution have complex peripheral interfaces and many control signals, which are difficult for developers to use and have low development and use efficiency. The present invention encapsulates the peripheral AXI bus interface into an external FIFO interface, and finally implements the read and write operations on the FIFO through layer-by-layer encapsulation, thereby improving the use efficiency and simplicity of the RapidIO bus. Encapsulation according to the method of use of the present invention can improve the use efficiency and development speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the present disclosure;

[0054] Figure 1 It is a flow chart of a serial high-speed interface packaging method based on FPGA provided by an embodiment of the present invention;

[0055] Figure 2 is a software flow chart of test data verification provided by an embodiment of the present invention;

[0056] Figure 3 It is a schematic diagram of a serial high-speed interface packaging system based on FPGA provided by an embodiment of the present invention;

[0057] In the figure: 1. User interface module; 2. Maintenance module; 3. Request module; 4. Target module; 5. SRIO communication software framework. DETAILED DESCRIPTION

[0058] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific implementation disclosed below.

[0059] Embodiment 1, as Figure 1 As shown, the FPGA-based serial high-speed interface packaging method provided by the embodiment of the present invention includes:

[0060] S1, design the user interface module, which is used as a channel for data interaction between the user module and the SRIOIP core;

[0061] The user interface module is the transfer station for data transmission in the overall design scheme. The user interface module consists of three submodules: request module, target module and configuration module.

[0062] Specifically, a configuration module is designed, and the configuration module is mainly responsible for maintenance operations and error management of RapidIO devices.

[0063] Design the request module, which is mainly responsible for initiating requests and responses to the logic layer according to the needs of the user module. When this RapidIO device is a host device, the request module is responsible for initiating requests and verifying responses.

[0064] Design the target module. When the target module acts as a slave module, the target module is mainly responsible for generating target requests and checking corresponding target responses.

[0065] The user module is the starting and ending point of the overall design. It is mainly responsible for sending and receiving RapidIO device control signals and data processing functions. It uses FIFO buffers to solve the rate matching problem between the user interface and the SRIO IP core.

[0066] S2, designing a maintenance module for performing maintenance operations on RapidIO devices through read and write transactions;

[0067] When performing a write transaction, the address and data need to be written to the channel of the maintenance port. After the write transaction is completed, the SRIO logic layer will receive a response to the corresponding operation.

[0068] When performing a read transaction, write the address and command to be read. After the read transaction is completed, the SRIO logic layer will receive the response of the corresponding operation and the read data. The maintenance port can only receive one read transaction or one write transaction at a time.

[0069] Among them, in the local maintenance transaction flow transmission mechanism, the user reads or updates the local configuration register through the maintenance port. The execution process is as follows:

[0070] S201, first, the user submits a maintenance request for updating or reading the local register of the SRIO endpoint through the maintenance port;

[0071] S202, the logic layer of the local SRIO endpoint forwards the request transaction packet to the configuration structure of the SRIO endpoint;

[0072] S203, the configuration structure parses the address of the current maintenance request, and forwards the transaction to the corresponding configuration register according to the parsed request address;

[0073] S204, after the read or update operation is performed on the local configuration register, the configuration register generates a response and returns it to the configuration structure;

[0074] S205, after the configuration structure receives the response sent by the configuration register, the configuration structure forwards the response to the logic layer of the SRIO endpoint;

[0075] S206, after receiving the response, the logic layer of the SRIO endpoint parses the information in the packet and transmits it to the corresponding channel;

[0076] S3, designing the request module, which is used to execute the request test sequence, request packet encapsulation, request response verification function and execute response packet parsing;

[0077] In the present invention, the request module is composed of four parts: a request test sequence module, a request packet encapsulation module, a request response verification module, and a response packet parsing module;

[0078] Design a request test sequence module, which generates a test instruction sequence and sends NWRITE, SWRITE and other test transaction requests to the target device as required.

[0079] Design a request packet encapsulation module. The request packet encapsulation module classifies the RapidIO transaction type, frames the reconstructed configuration file data and the reconstructed waveform number according to the RapidIO packet format, and sends the packet to the logic layer of the local endpoint through the AXI4-Stream interface.

[0080] Design the request response verification module, which is mainly responsible for verifying the information of the request that needs to be responded to and checking whether the returned response is correct;

[0081] Design a response packet parsing module, which is mainly responsible for parsing the received response transaction packet, and then obtaining the status information and reading data in the response packet.

[0082] S4, designing a target module for responding to the request transaction packet of the initiating device; the target module is designed according to the target request interface and the target response interface received by the SRIO logic layer. In the present invention, the target module is composed of a target device automatic return response module, a target device request packet parsing module and a target device response packet encapsulation module.

[0083] First, the target device request packet parsing module is designed. The target device request packet parsing module parses the transaction packet received by the target device, parses the reconstructed data and the reconstructed waveform number and stores them in the FIFO cache;

[0084] Designing a target device automatic return response module, which generates a response corresponding to the request transaction according to the information provided by the target device request packet parsing module;

[0085] The target device response packet encapsulation module is designed. The target device response packet encapsulation module frames the response generated by the target device automatic return response module, and then transmits the response to the SRIO logic layer through the AXI4-Stream interface.

[0086] S5, design the SRIO communication software framework to cache the transmission data and solve the rate matching between the user clock domain and the SRIO clock domain;

[0087] The SRIO communication software framework mainly includes request module, target module, SRIOIP core, send FIFO module and receive FIFO module.

[0088] The request module mainly performs data packet encapsulation, and the target module unpacks the data packet. The request module code and the target module code are automatically generated when the SRIO IP core is generated. The send FIFO module and the receive FIFO module cache the transmission data and solve the rate matching between the user clock domain and the SRIO clock domain.

[0089] The present invention focuses on designing the above two modules: the sending FIFO module and the receiving FIFO module.

[0090] The transmit FIFO module implements the buffering of transmit data and the rate matching between the transmit clock domain and the SRIO clock domain by calling the asynchronous FIFO. The asynchronous FIFO in this transmit FIFO module instantiates the FIFOIP core inside the FPGA and sets the input bit width, output bit width, depth, write clock, and read clock. The instantiation of the transmit FIFO module is as follows:

[0091] Fifosend_fifo(

[0092] .rst(rst),

[0093] .wr_clk(send_clk),

[0094] .rd_clk(send_login_clk),

[0095] .din(send_din),

[0096] .wr_en(send_wr_en),

[0097] .rd_en(send_rd_en),

[0098] .dout(send_dout),

[0099] .full(send_full),

[0100] .empty(send_empty), );

[0102] Specifically include:

[0103] send_clk is the synchronous clock of data input, which serves as the write clock of FIFO. When the FIFO write enable signal send_wr_en is at a high level, the write data send_din is written into FIFO under the synchronization of send_clk clock; the logic layer clock send_login_clk of SRIO serves as the read clock of FIFO. When the read enable signal send_rd_en of FIFO is at a high level, the data send_dout is read out from FIFO; when the initialization signal, data valid signal and SRIOIP core preparation signal are valid at the same time, it indicates that the link initialization and transmission path handshake are successful. At this time, the send_rd_en signal is at a high level. When a data packet is sent and the completion signal is pulled high, send_rd_en becomes a low level. When writing configuration data into FIFO, send_wr_en is pulled high. If the FIFO is full or the data writing is completed, send_wr_en is pulled low. The present invention initially transmits continuous test data that increases by 1 from zero. When the receiving end successfully communicates through error-free verification, the configuration data is transmitted.

[0104] The receiving FIFO module caches the configuration data parsed from the data packet in an asynchronous FIFO. The asynchronous FIFO in the receiving FIFO module instantiates the FIFOIP core inside the FPGA, sets the input bit width, output bit width, depth to 4096, write clock, and read clock. The sending FIFO module is instantiated as follows.

[0105] Fiforeceive_fifo(

[0106] .rst(rst),

[0107] .wr_clk(receive_clk),

[0108] .rd_clk(receive_login_clk),

[0109] .din(receive_din),

[0110] .wr_en(receive_wr_en),

[0111] .rd_en(receive_rd_en),

[0112] .dout(receive_dout),

[0113] .full(receive_full),

[0114] .empty(receive_empty), );

[0116] Specifically include:

[0117] When the channel handshake is detected to be successful and a data packet arrives, receive_wr_en becomes high, and the valid data receive_din parsed from the data packet is written into the FIFO. When the FIFO is not empty and the read enable receive_rd_en is high, the data is read from the FIFO. In order to ensure stable SRIO communication, the parsed test data is first verified. Since the test data is incremented by 1 from zero, the same standard data is generated at the receiving end at the same time, and verification is performed when the receive enable is valid. The software flow of the test data verification is as follows: Figure 2 shown.

[0118] On the premise that the SRIO interface transmission test data is verified to be correct and SRIO stable communication is achieved, the configuration data is transmitted, and the valid data parsed from the data packet is stored in the FIFO to realize the function of SRIO interface transmission configuration data.

[0119] Embodiment 2, as Figure 3 As shown, the FPGA-based serial high-speed interface packaging system provided by the embodiment of the present invention includes:

[0120] User interface module 1, used for the channel for data interaction between the user module and the SRIOIP core;

[0121] Maintenance module 2, used for performing maintenance operations on RapidIO devices through read and write transactions;

[0122] Request module 3, used to execute request test sequence, request packet encapsulation, request response verification function and execute response packet parsing;

[0123] The target module 4 is used to respond to the request transaction packet of the initiator device;

[0124] The SRIO communication software framework 5 is used to cache the transmission data and solve the rate matching between the user clock domain and the SRIO clock domain.

[0125] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0126] Since the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present invention, their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0127] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated in one processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment.

[0128] An embodiment of the present invention further provides a computer device, which includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor implements the steps of any of the above-mentioned method embodiments when executing the computer program.

[0129] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0130] An embodiment of the present invention further provides an information data processing terminal, which, when executed on an electronic device, provides a user input interface to implement the steps in the above method embodiments. The information data processing terminal is not limited to mobile phones, computers, and switches.

[0131] An embodiment of the present invention further provides a server, which is used to provide a user input interface to implement the steps in the above method embodiments when executed on an electronic device.

[0132] An embodiment of the present invention provides a computer program product. When the computer program product runs on an electronic device, the electronic device can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0133] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the camera / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a disk or an optical disk.

[0134] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered within the protection scope of the present invention.

Claims

1. A serial high-speed interface packaging method based on FPGA, characterized in that: The method includes: S1, design the user interface module, which is used as a channel for data interaction between the user module and the SRIOIP core; S2, designing a maintenance module for performing maintenance operations on RapidIO devices through read and write transactions; S3, designing the request module, which is used to execute the request test sequence, request packet encapsulation, request response verification function and execute response packet parsing; S4, designing a target module for responding to a request transaction packet of the initiating device; S5, design the SRIO communication software framework to cache the transmitted data and solve the rate matching between the user clock domain and the SRIO clock domain.

2. The FPGA-based serial high-speed interface packaging method according to claim 1, characterized in that: In step S1, the user interface module includes: The configuration module is responsible for performing maintenance operations and error management on the RapidIO device; The request module is responsible for initiating requests and responses to the logic layer according to the needs of the user module. When the RapidIO device acts as a host device, it is responsible for initiating requests and verifying responses. When the target module acts as a slave module, it is responsible for generating target requests and checking the corresponding target responses; The user module is responsible for sending and receiving RapidIO device control signals and data processing functions; the FIFO buffer is used to complete the rate matching of user data between the user interface and the SRIO IP core.

3. The FPGA-based serial high-speed interface packaging method according to claim 1, characterized in that: In step S2, when a write transaction operation is performed, the address and data are written to the channel of the maintenance port; After the write transaction is executed, the SRIO logic layer receives the response of the corresponding operation; When performing a read transaction, the address and command to be read are written; after the read transaction is completed, the SRIO logic layer receives a response to the corresponding operation and receives the read data at the same time.

4. The FPGA-based serial high-speed interface packaging method according to claim 1, characterized in that: In step S2, performing maintenance operations on the RapidIO device through read and write transactions includes: S201, first, the user submits a maintenance request for updating or reading the local register of the SRIO endpoint through the maintenance port; S202, the logic layer of the local SRIO endpoint forwards the request transaction packet to the configuration structure of the SRIO endpoint; S203, the configuration structure parses the address of the current maintenance request, and forwards the transaction to the corresponding configuration register according to the parsed request address; S204, after the read or update operation is performed on the local configuration register, the configuration register generates a response and returns it to the configuration structure; S205, after receiving the response sent by the configuration register, the configuration structure forwards the response to the logic layer of the SRIO endpoint through the configuration structure; S206, after receiving the response, the logic layer of the SRIO endpoint parses the information in the packet and transmits it to the corresponding channel.

5. The FPGA-based serial high-speed interface packaging method according to claim 1, characterized in that: In step S3, the request module is composed of a request test sequence module, a request packet encapsulation module, a request response verification module, and a response packet parsing module; The request test sequence module generates a test instruction sequence and sends NWRITE and SWRITE test transaction requests to the target device according to the requirements; The request packet encapsulation module classifies the reconstruction configuration file data and the reconstruction waveform number according to the RapidIO packet format according to the RapidIO transaction type, and sends the packet to the logic layer of the local endpoint through the AXI4-Stream interface; The request response verification module is responsible for verifying the information of the request that needs to return a response and checking whether the returned response is correct; The response packet parsing module is responsible for parsing the received response transaction packet, and then obtaining the status information and reading data in the response packet.

6. The FPGA-based serial high-speed interface packaging method according to claim 1, characterized in that: In step S4, the target module is composed of a target device automatic return response module, a target device request packet parsing module and a target device response packet encapsulation module; The target device request packet parsing module parses the transaction packet received by the target device, parses the reconstructed data and the reconstructed waveform number and stores them in the FIFO cache; The target device automatic return response module generates a response corresponding to the request transaction according to the information provided by the target device request packet parsing module; The target device response packet encapsulation module frames the response generated by the target device automatic return response module, and then transmits the response to the SRIO logic layer through the AXI4-Stream interface.

7. The FPGA-based serial high-speed interface packaging method according to claim 1, characterized in that: In step S5, the SRIO communication software framework includes a request module, a target module, an SRIO IP core, a send FIFO module and a receive FIFO module; The request module code and the target module code are automatically generated when the SRIO IP core is generated. The send FIFO module and the receive FIFO module cache the transmission data and complete the rate matching between the user clock domain and the SRIO clock domain.

8. The FPGA-based serial high-speed interface packaging method according to claim 7, characterized in that: The sending FIFO module realizes the caching of the sending data and the rate matching of the sending end clock domain and the SRIO clock domain by calling the asynchronous FIFO; the asynchronous FIFO in the sending FIFO module instantiates the FIFOIP core inside the FPGA, sets the input bit width, output bit width, depth, write clock, and read clock; the instantiation of the sending FIFO module specifically includes: When the FIFO write enable signal send_wr_en is high, the write data send_din is written into the FIFO in synchronization with the send_clk clock; When the FIFO read enable signal send_rd_en is high, the data send_dout is read from the FIFO; When the initialization signal, data valid signal and SRIOIP core ready signal are valid at the same time, the link initialization and transmission path handshake are successful, and the send_rd_en signal is high. When the data packet sending completion signal is pulled high, send_rd_en becomes low. When writing configuration data to FIFO, pull send_wr_en high. If FIFO is full or data writing is completed, pull send_wr_en low.

9. The FPGA-based serial high-speed interface packaging method according to claim 7, characterized in that: The receiving FIFO module caches the configuration data parsed from the data packet in an asynchronous FIFO. The asynchronous FIFO in the receiving FIFO module instantiates the FIFOIP core inside the FPGA, and sets the input bit width, output bit width, depth, write clock, and read clock. The instantiated transmit FIFO module includes: When the channel handshake is detected to be successful and a data packet arrives, receive_wr_en becomes high level, and the valid data receive_din parsed from the data packet is written into the FIFO; when the FIFO is not empty and the read enable receive_rd_en is high level, the data is read from the FIFO; In SRIO communication, the parsed test data is verified; on the premise that the SRIO interface transmission test data is verified to be correct and SRIO stable communication is achieved, the configuration data is transmitted, and the valid data parsed from the data packet is stored in the FIFO, thereby realizing the function of the SRIO interface to transmit configuration data.

10. A serial high-speed interface packaging system based on FPGA, characterized in that: The system implements the FPGA-based serial high-speed interface packaging method according to any one of claims 1 to 9, and the system comprises: A user interface module (1) is used as a channel for data interaction between the user module and the SRIOIP core; A maintenance module (2), used for performing maintenance operations on the RapidIO device through read and write transactions; Request module (3), used to execute request test sequence, request packet encapsulation, request response verification function and execute response packet parsing; A target module (4), configured to respond to a request transaction packet from the initiator device; The SRIO communication software framework (5) is used to cache the transmission data and solve the rate matching between the user clock domain and the SRIO clock domain.

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