Peak current detection circuit applied to BUCK

Abstract

The invention provides a peak current detection circuit applied to BUCK, and the circuit detects the current IL flowing through an inductor of a BUCK chip through detecting the potential of an SW output end between an upper power tube and a lower power tube of the BUCK chip, so as to carry out the detection of the peak current of the BUCK chip. The peak current detection circuit comprises a reference current source, a current mirror circuit, a biasing circuit, a reference voltage circuit, a trimming circuit and a high-voltage protection circuit which are connected. According to the invention, tiny voltage change of the SW is converted into obvious current change for detection through the MOS tube which works in a saturation region and has relatively large transconductance, so that the sensitivity of circuit detection is improved; the DMOS is introduced through reasonable design, the circuit is protected from being burnt by large voltage, and the circuit is suitable for wide input voltage. The current detection circuit can be applied to the condition of wide input voltage, and the current detection sensitivity is high; in practical application, the circuit can work normally under the input of 3-40V.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a peak current detection circuit applied to a BUCK. Background Art

[0002] Peak current detection is of great significance in the operation of power management chips. For power management chips BUCK, the input voltage spans a wide range, from a few volts to tens of volts, so a detection circuit suitable for a wide input voltage is very important in practical applications. In addition, the sensitivity of peak current detection is also crucial. Too low sensitivity can lead to reduced chip performance at best, or even burnout of the chip.

[0003] Therefore, it is very important to design a peak current detection circuit that can meet wide input range and has high sensitivity. Summary of the invention

[0004] The present invention is to solve the problem of peak current detection sensitivity of BUCK, and provides a peak current detection circuit applied to BUCK. The MOS tube with large transconductance working in the saturation region converts the small voltage change of SW into a significant current change for detection, thereby improving the sensitivity of circuit detection; through the introduction of DMOS by reasonable design, the circuit is protected from being burned by large voltage, and is suitable for wide input voltage. The present invention can be applied to the situation of wide input voltage, and the current detection sensitivity is high; in practical applications, the circuit can work normally under 3-40V input.

[0005] The present invention provides a peak current detection circuit applied to BUCK, which detects the current I flowing through the inductor of the BUCK chip by detecting the potential of the SW output terminal between the upper tube and the lower tube of the power tube of the BUCK chip. L To detect the peak current of the BUCK chip, the drain of the power tube is connected to the PVIN pin of the BUCK chip, the source of the power tube is connected to the SW output terminal, one end of the BUCK chip inductor is connected to the SW output terminal, and the other end outputs VOUT and connects to the capacitor C L Rear grounding;

[0006] The peak current detection circuit includes a reference current source and a current mirror circuit connected thereto, a bias circuit, a reference voltage circuit, and a trimming circuit respectively connected to the output end of the current mirror circuit, an input comparison circuit connected to the reference voltage circuit and the SW output end, and a high-voltage protection circuit connected to the input comparison circuit, and the bias circuit, the reference voltage circuit, and the input comparison circuit are all connected to the PVIN pin of the BUCK chip;

[0007] The reference current source provides a reference current I0, and the current mirror circuit copies the reference current I0 to the bias circuit, the reference voltage circuit and the trimming circuit in proportion. The bias circuit provides a static operating point, and the reference voltage circuit provides a reference voltage for comparison. The input comparison circuit compares the voltage and determines whether the peak current of the BUCK chip exceeds a preset value. The trimming circuit is connected to the Trim pin and trims the peak current detection circuit. The high-voltage protection circuit prevents high voltage from damaging components in the input comparison circuit.

[0008] The current mirror circuit includes NMOS tubes NM1, NM2, NM3, and NM4 whose gates are interconnected; the gate and drain of tube NM1 are interconnected and connected to a reference current source, and the source is grounded; the sources of tubes NM2, NM3, and NM4 are all grounded, the drain of tube NM2 is connected to a bias circuit, the drain of tube NM3 is connected to a trimming circuit, and the drain of tube NM4 is connected to a reference voltage circuit; the currents flowing through tubes NM1, NM2, NM3, and NM4 are I1, I2, I3, and I4 respectively;

[0009] The reference voltage circuit includes a resistor R1 connected to the PVIN pin and an NDMOS tube NMd2 connected to the other end of the resistor R1. The current of the resistor R1 is I5. The gate of the tube NMd2 is connected to the working voltage VDD, the drain is connected to the resistor R1, and the source is connected to the drain of the tube NM4.

[0010] The point between the resistor R1 and the tube NMd2 is point C. The input comparison circuit determines whether the peak current of the BUCK chip exceeds the preset value by comparing the potential between point C and the SW output terminal. When the output OC_OUT of the input comparison circuit is high, the peak current of the BUCK chip exceeds the preset value. When the output OC_OUT of the input comparison circuit is low, the peak current of the BUCK chip is lower than the preset value.

[0011] The high voltage protection circuit is a PDMOS tube.

[0012] The peak current detection circuit applied to BUCK described in the present invention, as a preferred embodiment, the input comparison circuit includes NMOS tubes NM7 and NM8 whose drains are respectively connected to the PVIN pin, PMOS tubes PM3 and PM4 whose sources are respectively connected to the PVIN pin, a comparator U1 connected to the tubes PM3 and PM4 respectively, a resistor R2 whose one end is connected to the drain of the tube PM3 and the other end is grounded, and a resistor R3 whose one end is connected to the drain of the tube PM4 and the other end is grounded;

[0013] The gate of tube NM7 is connected to point C, and the source is connected to the gate and drain of tube PM3; the intersection of the drain of tube PM3, the positive input terminal of comparator U1, and the connection point of resistor R2 is point A, and the intersection of the drain of tube PM4, the negative input terminal of comparator U1, and the connection point of resistor R3 is point B; the gate of tube NM8 is connected to the SW output terminal, and the source is connected to the gate and drain of tube PM4;

[0014] Pipe PM3 and pipe PM4 provide static working points for pipe NM7 and pipe NM8 respectively;

[0015] R2=R3=R0, the current flowing through tube NM7 and tube PM3 is combined and then flows through resistor R2, the current is I A The current flowing through tubes NM8 and PM4 is combined and then flows through resistor R3. The current is I B ;

[0016] The potential at point C is PVIN-I5*R1, and the potential at the SW output is PVIN-I L R top , where R top is the on-resistance of the power tube of the BUCK chip;

[0017] When the potential of the SW output terminal is greater than the potential of point C, PVIN-I L R top >PVIN-I5*R1, I B >I A , the potential at point B is greater than that at point A, and the current flowing through the inductor does not exceed I5*R1 / R top , the output OC_OUT is low level;

[0018] When the potential of the SW output terminal is lower than the potential of point C, PVIN-I L R top <PVIN-I5*R1, I A >I B , the potential at point A is greater than the potential at point B, and the current flowing through the inductor exceeds I5*R1 / R top , the output OC_OUT is high level;

[0019] The peak current detected by the peak current detection circuit is I5*R1 / R top .

[0020] The peak current detection circuit applied to BUCK described in the present invention, as a preferred embodiment, the high voltage protection circuit includes a PDMOS tube PMd1 connected between point C and tube NM7, a PDMOS tube PMd2 connected between the SW output end and tube NM8, a PDMOS tube PMd4 connected between tube PM3 and point A, and a PDMOS tube PMd5 connected between tube PM4 and point B;

[0021] The drain of tube PMd1 is connected to point C, the source is connected to the gate of tube NM7, and the gate is connected to the source of tube NM7; the drain of tube PMd2 is connected to the SW output terminal, the source is connected to the gate of tube NM8, and the gate is connected to the source of tube NM8; the drain of tube PMd4 is connected to point A, the source is connected to the drain of tube PM3, and the gate is connected to the bias circuit; the drain of tube PMd5 is connected to point B, the source is connected to the drain and gate of tube PM4, and the gate is connected to the gate of tube PMd4 and the bias circuit;

[0022] The PMd1 and PMd2 tubes protect the NM7 and NM8 tubes respectively. The PMd4 and PMd5 tubes protect the NM7, PM3, NM8 and PM4 tubes respectively.

[0023] The currents flowing through tubes NM7 and PM3 are combined and then flow through tube PMd4 and resistor R2 in sequence. The current is I A The currents flowing through tube NM8 and tube PM4 are combined and then flow through tube PMd5 and resistor R3 in sequence. The current is I B .

[0024] The peak current detection circuit applied to BUCK described in the present invention, as a preferred embodiment, the bias circuit includes a PMOS tube PM2, a PDMOS tube PMd3 and a NDMOS tube NMd1 connected to the PVIN pin in sequence;

[0025] The source of tube PM2 is connected to the PVIN pin, and the drain and gate are connected to the source of tube PMd3; the gate and drain of tube PMd3 are connected to the drain of tube NMd1, and the gate of tube PMd3 is connected to the gate of tube PMd4 and the gate of tube PMd5;

[0026] The gate of transistor NMd1 is connected to the voltage VDD, and the source is connected to the drain of transistor NM2.

[0027] The peak current detection circuit applied to BUCK described in the present invention is preferably in the following manner: I1=I2=kI3=I4=I0, wherein k is a proportionality coefficient.

[0028] The peak current detection circuit applied to BUCK described in the present invention, as a preferred embodiment, the trimming circuit includes a PMOS tube PM1 whose gate is connected to the Trim pin, the source of the tube PM1 is connected to the source of the tube NMd2, and the drain is connected to the drain of the tube NM3;

[0029] When the Trim pin outputs a high level, the tube PM1 is turned off, and the current I5=I4=I0 flowing through the tube NMd2 and the resistor R1. The peak current detected is I0*R1 / R top ;

[0030] When the Trim pin outputs a low level, the tube PM1 is turned on, and the current flowing through the tube NMd2 and the resistor R1 is:

[0031]

[0032] The peak current detection circuit applied to BUCK described in the present invention is, as a preferred embodiment, when the Trim pin outputs a low level, the detected peak current is:

[0033]

[0034] The peak current preset value is increased by:

[0035]

[0036] The peak current detection circuit applied to BUCK described in the present invention can, as a preferred embodiment, further add at least one trimming circuit to perform multi-step trimming by adjusting the k value.

[0037] The peak current detection circuit applied to BUCK described in the present invention is preferably configured such that the gate of the upper tube of the power tube is connected to the upper tube driver and the source is connected to the drain of the lower tube of the power tube, the gate of the lower tube of the power tube is connected to the lower tube driver and the source is grounded, and the source of the upper tube of the power tube and the drain of the lower tube of the power tube are both connected to the SW output terminal.

[0038] The present invention has the following advantages:

[0039] The present invention provides a peak current detection circuit applied to BUCK, which converts the tiny voltage change of SW into a significant current change for detection by a MOS tube with a large transconductance working in the saturation region, thereby improving the sensitivity of circuit detection; by introducing DMOS through reasonable design, the circuit is protected from being burned by a large voltage, and is suitable for a wide input voltage. The present invention can be applied to the case of a wide input voltage, and the current detection sensitivity is high; in practical applications, the circuit can work normally under an input of 3 to 40V. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A circuit framework diagram of a BUCK chip for a peak current detection circuit applied to a BUCK;

[0041] Figure 2 The figure is a specific circuit diagram of a peak current detection circuit applied to BUCK. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0043] Example 1

[0044] like Figure 1 , 2 As shown in FIG. 1 , a peak current detection circuit for BUCK is shown. The principle of this circuit is that the potential of SW corresponds to the current flowing through the inductor. When the upper tube of the power tube is turned on and the lower tube is turned off, the current flowing through the upper tube of the power tube is equal to the current flowing through the inductor, that is, I top =I L Therefore, the potential of SW is PVIN-I L R top , I L is the current flowing through the inductor, R top is the on-resistance of the upper power tube, see Figure 1 If PVIN, R to The value of p means that SW and I L Detecting the voltage value of SW is to detect the inductor current I L .

[0045] Current Source is a reference current source, and the current magnitude of the current source is I0.

[0046] NM1, NM2, NM3, and NM4 form a current mirror circuit, and the currents flowing through them are I1, I2, I3, and I4 respectively. And the size parameters satisfy the relationship:

[0047]

[0048] k is the proportional coefficient, then I1=I2=kI3=I4=I0.

[0049] NM2, NMd1, PMd3, and PM2 form a bias circuit. NMd1 is an NDMOS, and its gate voltage is VDD, which is the operating voltage of the chip's internal module. NMd1 can prevent large voltages from appearing on the source and drain of NM2 and PM2 to protect the components. The gate and drain of PMd3 are connected together to provide a bias voltage for PMd1 and PMd2.

[0050] NM4, NMd2, and R1 provide reference voltage. NMd2 is NDMOS, and its gate voltage is VDD. NMd2 can prevent large voltage from appearing in the source and drain of NM4, NM3, and PM1, thus protecting the components. The current flowing through NMd2 and R1 is I5, and the resistance value of R1 is R1, so the voltage across R1 is I5*R1, and the potential at point C is PVIN-I5*R1. If the values ​​of PVIN and R1 are known, the corresponding relationship between the potential at point C and I5 can be known.

[0051] NM7, PM3, NM8, PM4, R2, R3, and U1 form an input comparison circuit for comparing the potentials of SW and point C. The resistance values ​​of R2 and R3 are R2 and R3 respectively.

[0052] The gates of NM7 and NM8 are the inputs of the comparison circuit, and the input is a voltage signal. The gate voltage of NM7 and NM8 is less than the drain voltage, so they work in the saturation region. According to the characteristics of MOS tubes, NM7 and NM8 working in the saturation region have large transconductance, which can convert small voltage changes of the gate into significant current changes. After the conversion of this circuit, the voltage signal that was originally difficult to measure becomes a current signal that is easy to measure, so the circuit has high sensitivity.

[0053] PMd1 and PMd2 are PDMOS, which can block large voltage input to NM7 and NM8, thereby protecting NM7 and NM8.

[0054] PM3 and PM4 provide static working points for NM7 and NM8.

[0055] The current flowing through NM7 and PM3 is combined and then flows through PMd4 and R2. The current is I A The current flowing through NM8 and PM4 is combined and then flows through PMd5 and R3. The current is I B , take R2=R3=R0, so the voltage across the resistors R2 and R3 is R0*I respectively A 、R0*I B , the potential at point A is R0*I A , then the potential at point B is R0*I B PMd4 and PMd5 are PDMOS, which can prevent large voltage from appearing on the source and drain of NM7, PM3, NM8, and PM4, thus protecting the components.

[0056] Comparator U1 is used to compare the potentials of point A and point B. When the potential of point A is greater than the potential of point B, the output OC_OUT is high, indicating that the peak current exceeds the preset value. When the potential of point A is less than the potential of point B, the output OC_OUT is low, indicating that the peak current is lower than the preset value.

[0057] When SW is greater than the potential at point C, that is, PVIN-I L R top >PVIN-I5*R1, there is I A <I B , the potential at point A is less than that at point B, and the current flowing through the inductor does not exceed I5*R1 / R top , the output OC_OUT is low level. When SW is less than the potential at point C, that is, PVIN-I L R top <PVIN-I5*R1, there is IA >I B , the potential at point A is greater than the potential at point B, and the current flowing through the inductor exceeds I5*R1 / R top , the output OC_OUT is high level. Therefore, the peak current detected is I5*R1 / R top .

[0058] PM1 and NM3 form a trimming circuit. When Trim is high, PM1 is turned off, and the current flowing through NMd2 and R1 is I5=I4=I0, so the peak current detected is I0*R1 / R top When Trim is at a low level, PM1 is turned on, and the current flowing through NMd2 and R1 is:

[0059]

[0060] The peak current detected is:

[0061]

[0062] The peak current preset value is increased by:

[0063]

[0064] When applied, the value of k can be adjusted according to actual conditions, and more adjustment branches and control circuits can be added to achieve multi-stage adjustment.

[0065] In practical applications, this circuit can work normally under 3~40V input and has high current sensitivity.

[0066] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A peak current detection circuit applied to a BUCK, characterized in that: The current I flowing through the BUCK chip inductor is detected by detecting the potential of the SW output terminal between the upper and lower power tubes of the BUCK chip. L To detect the peak current of the BUCK chip, the drain of the power tube is connected to the PVIN pin of the BUCK chip, the source of the power tube is connected to the SW output end, one end of the BUCK chip inductor is connected to the SW output end, and the other end outputs VOUT and is connected to the capacitor C L Rear grounding; The peak current detection circuit includes a reference current source and a current mirror circuit connected thereto, a bias circuit, a reference voltage circuit, and a trimming circuit respectively connected to the output end of the current mirror circuit, an input comparison circuit connected to the reference voltage circuit and the SW output end, and a high-voltage protection circuit connected to the input comparison circuit, wherein the bias circuit, the reference voltage circuit, and the input comparison circuit are all connected to the PVIN pin of the BUCK chip; The reference current source provides a reference current I0, the current mirror circuit copies the reference current I0 to the bias circuit, the reference voltage circuit and the trimming circuit in proportion, the bias circuit provides a static operating point, the reference voltage circuit provides a reference voltage for comparison, the input comparison circuit compares the voltage and determines whether the peak current of the BUCK chip exceeds a preset value, the trimming circuit is connected to the Trim pin and trims the peak current detection circuit, and the high-voltage protection circuit prevents high voltage from damaging components in the input comparison circuit; The current mirror circuit comprises NMOS tubes NM1, NM2, NM3, and NM4 whose gates are interconnected; the gate and drain of tube NM1 are interconnected and connected to the reference current source, and the source is grounded; the sources of tubes NM2, NM3, and NM4 are all grounded, the drain of tube NM2 is connected to the bias circuit, the drain of tube NM3 is connected to the trimming circuit, and the drain of tube NM4 is connected to the reference voltage circuit; the currents flowing through tubes NM1, NM2, NM3, and NM4 are I1, I2, I3, and I4 respectively; The reference voltage circuit includes a resistor R1 connected to the PVIN pin and an NDMOS tube NMd2 connected to the other end of the resistor R1. The current of the resistor R1 is I5. The gate of the tube NMd2 is connected to the working voltage VDD, the drain is connected to the resistor R1, and the source is connected to the drain of the tube NM4. The point between the resistor R1 and the tube NMd2 is point C. The input comparison circuit determines whether the peak current of the BUCK chip exceeds the preset value by comparing the potential between point C and the SW output end; when the output OC_OUT of the input comparison circuit is at a high level, the peak current of the BUCK chip exceeds the preset value; when the output OC_OUT of the input comparison circuit is at a low level, the peak current of the BUCK chip is lower than the preset value.

2. The peak current detection circuit applied to a BUCK according to claim 1, characterized in that: The input comparison circuit includes NMOS tubes NM7 and NM8 whose drains are respectively connected to the PVIN pin, PMOS tubes PM3 and PM4 whose sources are respectively connected to the PVIN pin, a comparator U1 connected to tubes PM3 and PM4 respectively, a resistor R2 whose one end is connected to the drain of tube PM3 and the other end is grounded, and a resistor R3 whose one end is connected to the drain of tube PM4 and the other end is grounded; The gate of tube NM7 is connected to point C, and the source is connected to the gate and drain of tube PM3; the intersection of the drain of tube PM3, the positive input terminal of comparator U1, and the connection point of resistor R2 is point A, and the intersection of the drain of tube PM4, the negative input terminal of comparator U1, and the connection point of resistor R3 is point B; the gate of tube NM8 is connected to the SW output terminal, and the source is connected to the gate and drain of tube PM4; Pipe PM3 and pipe PM4 provide static working points for pipe NM7 and pipe NM8 respectively; R2=R3=R0, the current flowing through tube NM7 and tube PM3 is combined and then flows through resistor R2, the current is I A The current flowing through tubes NM8 and PM4 is combined and then flows through resistor R3. The current is I B ; The potential at point C is PVIN-I5*R1, and the potential at the SW output is PVIN-I L R top , where R top is the on-resistance of the power tube of the BUCK chip; When the potential of the SW output terminal is greater than the potential of point C, PVIN-I L R top >PVIN-I5*R1, I B >I A , the potential at point B is greater than that at point A, and the current flowing through the inductor does not exceed I5*R1 / R top , the output OC_OUT is low level; When the potential of the SW output terminal is less than the potential of point C, PVIN - I L R top When <PVIN - I5 * R1, I A >I B , the potential of point A is greater than the potential of point B, and the current flowing through the inductor exceeds I5 * R1 / R top , and the output OC_OUT is at a high level; The peak current detected by the peak current detection circuit is I5*R1 / R top .

3. The peak current detection circuit applied to BUCK according to claim 2, characterized in that: The high-voltage protection circuit includes a PDMOS tube PMd1 connected between point C and tube NM7, a PDMOS tube PMd2 connected between the SW output terminal and tube NM8, a PDMOS tube PMd4 connected between tube PM3 and point A, and a PDMOS tube PMd5 connected between tube PM4 and point B; The drain of tube PMd1 is connected to point C, the source is connected to the gate of tube NM7, and the gate is connected to the source of tube NM7; the drain of tube PMd2 is connected to the SW output terminal, the source is connected to the gate of tube NM8, and the gate is connected to the source of tube NM8; the drain of tube PMd4 is connected to point A, the source is connected to the drain of tube PM3, and the gate is connected to the bias circuit; the drain of tube PMd5 is connected to point B, the source is connected to the drain and gate of tube PM4, and the gate is connected to the gate of tube PMd4 and the bias circuit; The PMd1 and PMd2 tubes protect the NM7 and NM8 tubes respectively. The PMd4 and PMd5 tubes protect the NM7, PM3, NM8 and PM4 tubes respectively. The currents flowing through tubes NM7 and PM3 are combined and then flow through tube PMd4 and resistor R2 in sequence. The current is I A The currents flowing through tube NM8 and tube PM4 are combined and then flow through tube PMd5 and resistor R3 in sequence. The current is I B .

4. The peak current detection circuit applied to a BUCK according to claim 3, characterized in that: The bias circuit includes a PMOS tube PM2, a PDMOS tube PMd3 and a NDMOS tube NMd1 which are sequentially connected to the PVIN pin; The source of tube PM2 is connected to the PVIN pin, and the drain and gate are connected to the source of tube PMd3; the gate and drain of tube PMd3 are connected to the drain of tube NMd1, and the gate of tube PMd3 is connected to the gate of tube PMd4 and the gate of tube PMd5; The gate of transistor NMd1 is connected to the voltage VDD, and the source is connected to the drain of transistor NM2.

5. The peak current detection circuit applied to BUCK according to claim 2, characterized in that: I1=I2=kI3=I4=I0, where k is the proportionality coefficient.

6. The peak current detection circuit applied to BUCK according to claim 5, characterized in that: The trimming circuit includes a PMOS tube PM1 whose gate is connected to the Trim pin, a source of the tube PM1 connected to the source of the tube NMd2, and a drain connected to the drain of the tube NM3; When the Trim pin outputs a high level, the tube PM1 is turned off, and the current I5=I4=I0 flowing through the tube NMd2 and the resistor R1. The peak current detected is I0*R1 / R top ; When the Trim pin outputs a low level, the tube PM1 is turned on, and the current flowing through the tube NMd2 and the resistor R1 is:

7. The peak current detection circuit applied to a BUCK according to claim 6, characterized in that: When the Trim pin outputs a low level, the peak current detected is: The peak current preset value is increased by:

8. The peak current detection circuit applied to a BUCK according to claim 6, characterized in that: By adjusting the k value, at least one more adjustment circuit may be added to perform multi-step adjustment.

9. The peak current detection circuit applied to a BUCK according to claim 1, characterized in that: The gate of the upper power tube is connected to the upper tube driver, the source is connected to the drain of the lower power tube, the gate of the lower power tube is connected to the lower tube driver, the source is grounded, and the source of the upper power tube and the drain of the lower power tube are both connected to the SW output end.

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