Hysteresis comparator circuit based on double-gate field effect transistor and integrated chip

Abstract

The invention relates to the technical field of integrated circuits, and discloses a hysteresis comparator circuit based on a double-gate field effect transistor and an integrated chip, the hysteresis comparator circuit comprises at least two cascaded phase inverters, each phase inverter at least comprises an input tube and a load tube, the input tube is connected with the load tube, and the load tube is connected with the input tube. The drain electrode of the input tube is connected with the source electrode of the load tube, a connection node is configured as the output end of the phase inverter, and at least one of the input tube and the load tube of each phase inverter is a double-gate field effect tube; the feedback electric wire is connected between the second grid electrode of the double-grid field effect transistor in the first-stage phase inverter and the output ends of the other phase inverters, so that signals on the first grid electrode and the second grid electrode of the double-grid field effect transistor change in an in-phase mode, and positive feedback for achieving the hysteretic effect is formed. According to the hysteresis comparator, the common modulation effect of the two grid electrodes of the double-grid field effect transistor is utilized to form the hysteresis effect, the on-chip integration difficulty of the hysteresis comparator is reduced, and the flexibility of the hysteresis comparator is improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a hysteresis comparator circuit and an integrated chip based on a dual-gate field effect transistor. Background Art

[0002] Spiking Neural Networks (SNNs) have attracted extensive attention in the field of neural computing and brain-like computing in recent years. Compared with traditional artificial neural networks (ANNs), SNNs have unique advantages in processing tasks in complex, dynamic and uncertain environments. As a key circuit module in SNNs, the hysteresis comparator with a simple structure and adjustable threshold window can be used to implement the integrate-and-fire (IF) circuit of the neuron model to simulate the membrane potential generation of biological neurons.

[0003] In the related art, an analog comparison circuit composed of an operational amplifier is generally used to form a comparator with a hysteresis effect. The hysteresis comparator constructed in this way has a complex feedback circuit and is difficult to implement on-chip applications in SNNs. Another implementation method in the related art is to use the hysteresis electrical characteristics of a memristor, but the hysteresis comparator constructed in this way cannot adjust the hysteresis threshold by electrical means. Summary of the invention

[0004] The present application provides a hysteresis comparator circuit and an integrated chip based on a dual-gate field effect transistor, which solves the technical problem that the circuit structure of the current hysteresis comparator is complex and difficult to integrate on a chip. In the comparator circuit, the common modulation effect of the two gates of the dual-gate field effect transistor is utilized to form a negative feedback of the hysteresis effect, which reduces the difficulty of on-chip integration of the hysteresis comparator applied to a pulse neural network and improves the flexibility of the hysteresis comparator.

[0005] In order to achieve the above objectives, the main technical solutions adopted in this application include:

[0006] In a first aspect, an embodiment of the present application provides a hysteresis comparator circuit based on a dual-gate field effect transistor, the hysteresis comparator circuit comprising:

[0007] At least two cascaded inverters, each of the inverters comprises at least one input tube and one load tube, wherein the drain of the input tube is connected to the source of the load tube, and the connection node is configured as the output end of the inverter, and at least one of the input tube and the load tube of each inverter is a dual-gate field effect tube;

[0008] A feedback conductor is connected between the second gate of the dual-gate field effect transistor in the first-stage inverter and the output end of other inverters, so that the signals on the first gate and the second gate of the dual-gate field effect transistor change in phase to form positive feedback to achieve hysteresis effect.

[0009] The hysteresis comparator circuit proposed in the embodiment of the present application connects the output end of the subsequent cascade inverter to the second gate of the double-gate field effect transistor in the first-stage inverter through a feedback conductor, so that the signals on the first gate and the second gate of the double-gate field effect transistor change in phase, thereby forming a positive feedback mechanism to realize the hysteresis effect, and uses the positive feedback of the in-phase signal to control the dynamic change of the threshold voltage of the double-gate field effect transistor, thereby generating different flip voltages in the process of the input signal from low to high or from high to low, forming a hysteresis effect. Compared with the traditional hysteresis circuit structure, the hysteresis comparator proposed in the present application avoids the complex gain control and feedback adjustment of the operational amplifier, and can more efficiently meet the operation requirements of bionic simulation systems such as SNNs, and the hysteresis comparator proposed in the present application reduces the number of circuit transistors, greatly simplifies the complexity of the integrated chip circuit layout, and is therefore conducive to high integration on the chip applied to the pulse neural network, so that the hysteresis comparator has the characteristics of high integration and low power consumption.

[0010] Optionally, in some embodiments of the present application, the hysteresis comparator circuit includes a first-stage inverter, the first-stage inverter includes a first input tube and a first load tube, and the configuration of the feedback electrical conductor is determined according to the number of gates of the first input tube and the first load tube of the first-stage inverter.

[0011] Optionally, in some embodiments of the present application, when the first input tube is a dual-gate field effect tube, the output end of the 2n-stage inverter in the hysteresis comparator circuit is connected to the second gate of the first input tube to form a first feedback conductor, so as to achieve that the gate signal on the first gate of the first input tube and the feedback signal on the second gate of the first input tube change in phase, n=1, 2, 3,…, N.

[0012] The embodiment of the present application can selectively set the first input tube as a dual-gate field effect tube, and form positive feedback through the first feedback electrical conductor between the first input tube and the output end of the even-numbered inverter, which not only simplifies the circuit structure and reduces the difficulty of on-chip integration, but also improves the flexibility of implementing the positive feedback process.

[0013] Optionally, in some embodiments of the present application, when the first load tube is a dual-gate field effect tube, the output end of the 2n+1th inverter in the hysteresis comparator circuit is connected to the second gate of the first load tube to form a second feedback conductor, so as to achieve the same phase change of the gate signal on the first gate of the first load tube and the feedback signal on the second gate of the first load tube, n=1, 2, 3, ..., N.

[0014] The embodiment of the present application can selectively set the first load tube as a dual-gate field effect tube, and form positive feedback through the second feedback electrical conductor between the first load tube and the output end of the odd-numbered inverter, which not only simplifies the circuit structure and reduces the difficulty of on-chip integration, but also improves the flexibility of implementing the positive feedback process.

[0015] Optionally, in some embodiments of the present application, when the number of cascaded inverters in the hysteresis comparator circuit is an even number, the first input tube is a dual-gate field effect tube.

[0016] In the embodiment of the present application, when the number of inverter cascades is an even number, the first input tube is set to a dual-gate field effect tube, so that an extra gate is used to form a positive feedback between the last-stage inverter and the first-stage inverter, thereby simplifying the circuit structure for realizing the hysteresis effect and facilitating on-chip integration.

[0017] Optionally, in some embodiments of the present application, when the number of cascaded inverters in the hysteresis comparator circuit is an odd number, the first load tube is a dual-gate field effect tube.

[0018] In the embodiment of the present application, when the number of inverter cascades is an odd number, the first load tube is set to a dual-gate field effect tube, so that an extra gate is used to form a positive feedback between the last-stage inverter and the first-stage inverter, thereby simplifying the circuit structure for realizing the hysteresis effect and facilitating on-chip integration.

[0019] Optionally, in some embodiments of the present application, the third input tube in at least one inverter in the hysteresis comparator circuit is a dual-gate field effect tube, and the second gate of the third input tube is configured to adjust the hysteresis window width of the hysteresis comparator circuit according to the connected bias voltage.

[0020] In the hysteresis comparator circuit proposed in the embodiment of the present application, at least one input tube is set as a dual-gate field effect tube, so that the other gate of the input tube can be used to access the bias voltage, so that the hysteresis window width can be flexibly adjusted electrically, thereby improving the applicability and adjustability of the hysteresis comparator.

[0021] Optionally, in some embodiments of the present application, when the load tube is a single-gate field effect tube, the first gate of the load tube is connected to one of the source and the drain of the load tube.

[0022] Optionally, in some embodiments of the present application, the hysteresis comparator circuit further includes a power supply wire group, the power supply wire group includes a first power supply wire and a second power supply wire, wherein the drain of the load tube in each of the inverters is connected to the first power supply wire, and the source of the input tube in each of the inverters is connected to the second power supply wire;

[0023] The power supply wire group is configured to select one of the first power line and the second power line to provide an input signal for the hysteresis comparator circuit, wherein the input signal is sent to the first gate of the first input tube in the first-stage inverter.

[0024] The embodiment of the present application uses a power supply wire group to flexibly select any one of the first power line and the second power line as the input signal to use different input voltage requirements, thereby improving the adaptability of the hysteresis comparator circuit, reducing the need for additional input signal path design, and greatly simplifying the circuit structure.

[0025] Optionally, in some embodiments of the present application, the gate of the input tube of the first-stage inverter is configured as the input end of the hysteresis comparator, and the connection node between the input tube and the load tube in the last even-numbered inverter is configured as the output end of the hysteresis comparator.

[0026] In a second aspect, an embodiment of the present application provides an integrated chip, the integrated chip comprising:

[0027] An integrated circuit unit, wherein the integrated circuit unit comprises the hysteresis comparator circuit described in the above embodiment.

[0028] The integrated chip proposed in the embodiment of the present application, by using a hysteresis comparator circuit composed of a dual-gate structure, constitutes a positive feedback mechanism to realize the hysteresis effect, thereby generating different flip voltages in the process of the input signal from low to high or from high to low, forming a hysteresis effect. Compared with the traditional hysteresis circuit structure, the integrated chip proposed in the present application avoids the complex gain control and feedback adjustment of the operational amplifier, can more efficiently meet the computing requirements of bionic simulation systems such as SNNs, and reduces the number of circuit transistors, greatly simplifies the complexity of the integrated chip circuit layout, and has the characteristics of low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 A schematic diagram of the circuit structure of a hysteresis comparator in the related art;

[0031] Figure 2 A schematic diagram of the structure of a hysteresis comparator circuit based on a dual-gate field effect transistor proposed in an embodiment of the present application;

[0032] Figure 3 A schematic diagram of the structure of a hysteresis comparator circuit proposed in one embodiment of the present application;

[0033] Figure 4 A schematic diagram of the structure of a hysteresis comparator circuit proposed in another embodiment of the present application;

[0034] Figure 5 A schematic diagram of an IF circuit proposed in an embodiment of the present application;

[0035] Figure 6 A schematic diagram of the structure of a hysteresis comparator circuit proposed in another embodiment of the present application;

[0036] Figure 7 A schematic diagram of the structure of a hysteresis comparator circuit proposed in another embodiment of the present application;

[0037] Figure 8 A schematic diagram of an IF circuit proposed in another embodiment of the present application;

[0038] Fig. 9 A device interface diagram proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0040] A hysteresis comparator is a comparator with a hysteresis loop transmission characteristic, which has two threshold voltages. For a comparator with a single threshold voltage, if the input signal has a slight interference near the threshold voltage, the output voltage will fluctuate accordingly. For a hysteresis comparator, since it has two different threshold voltages, the input voltage has a larger noise margin to maintain the comparison state of the output voltage, making the output of the hysteresis comparator more stable. Comparators with such dynamic threshold voltages can be used in many fields, such as power management, temperature control, signal processing, motor control, and sensor interface applications, and have high anti-interference capabilities, thereby reducing the risk of system instability caused by signal noise.

[0041] In some related technologies, a hysteresis comparator is generally constructed based on the hysteresis effect realized by an operational amplifier and a resistor, such as Figure 1 As shown, the positive input terminal of the operational amplifier OPA is connected to the reference potential V through the resistor R1. REF , the negative input terminal of the operational amplifier OPA is connected to the input voltage V IN The operational amplifier OPA is used to compare the signals at the positive input and the negative input and output a digital signal V OUT In order to suppress the instability of the digital signal caused by the noise of the two input signal terminals, a feedback resistor R2 is introduced from the output terminal to the positive input terminal so that the reference potential V REF Affected by the high and low potentials of the output signal, there are two threshold voltages V UTP and V LTP , thus forming a hysteresis comparator. Such a comparator has stable performance and the threshold voltage V UTP and V LTP The reference voltage V REF , resistors R1 and R2. However, its circuit structure is relatively complex, and a high-performance, high-gain operational amplifier OPA is required to ensure feedback stability. This circuit design is suitable for high-precision signal processing and control systems, but it is too complex and difficult to implement for bionic analog electronic systems, such as on-chip applications in pulse neural networks.

[0042] In other related technologies, the current-voltage curve of the memristor exhibits hysteresis characteristics and the resistance value is adjustable, so a single memristor device can realize the function of a hysteresis comparator. When the input signal voltage gradually increases and reaches the upper threshold voltage, the memristor changes from a high-resistance state to a low-resistance state, the loop current increases, and the output voltage signal becomes higher; and when the input signal voltage gradually decreases and reaches the lower threshold voltage, the memristor changes from a low-resistance state to a high-resistance state, the loop current decreases, and the output voltage signal becomes lower. Although this implementation method can be realized using only memristors and resistors and has a simple structure, the hysteresis comparator built on memristors cannot adjust the hysteresis threshold by electrical means.

[0043] The hysteresis comparator circuit provided in the embodiment of the present application can be applied to the integrated chip of bionic simulation systems such as SNNs, especially in SNNs, to realize the integral emission circuit of the neuron model and the frequency coding and time coding of the sensor signal, etc., to simulate the membrane potential generation of biological neurons, so as to improve the computing efficiency and stability of the network.

[0044] The hysteresis comparator circuit based on the dual-gate field effect transistor provided in this embodiment is as follows: Figure 2 As shown, at least two cascaded inverters 10 and a feedback electrical conductor 20 are included.

[0045] Each inverter 10 includes at least one input tube and one load tube, wherein the drain of the input tube is connected to the source of the load tube, and the connection node is configured as the output end of the inverter 10, and at least one of the input tube and the load tube of each inverter 10 is a dual-gate field effect tube.

[0046] The feedback wire 20 is connected between the second gate of the dual-gate field effect tube in the first-stage inverter and the output terminals of other inverters, so that the signals on the first gate and the second gate of the dual-gate field effect tube change in phase to form positive feedback to achieve hysteresis effect.

[0047] It should be noted that, in the embodiment of the present application, the hysteresis comparator circuit is composed of INV1, INV2, INV3, ..., INV 2n A total of 2n inverters 10 cascaded, or composed of INV1, INV2, INV3, ..., INV 2n and INV 2n+1 A total of 2n+1 stages of inverters 10 are cascaded, that is, the hysteresis comparison circuit includes more than two inverters 10, wherein the number of the inverters 10 can be an even number or an odd number.

[0048] The hysteresis comparator circuit proposed in the embodiment of the present application connects the output end of the cascade inverter behind to the second gate of the double-gate field effect tube in the first-stage inverter through a feedback conductor, so that the signals on the first gate and the second gate of the double-gate field effect tube change in phase, thereby forming a positive feedback mechanism to realize the hysteresis effect, and uses the positive feedback of the in-phase signal to control the dynamic change of the threshold voltage of the double-gate field effect tube, so as to generate different flip voltages in the process of the input signal from low to high or from high to low, forming a hysteresis effect. Compared with the traditional hysteresis circuit structure, the hysteresis comparator proposed in the present application avoids the complex gain control and feedback adjustment of the operational amplifier, and can more efficiently meet the computing requirements of bionic simulation systems such as SNNs. And the hysteresis comparator proposed in the present application reduces the number of circuit transistors, uses the double-gate field effect tube as the input tube and feedback tube of the direction device at the same time, greatly simplifies the complexity of the integrated chip circuit layout, and is therefore conducive to high integration on the chip applied to the pulse neural network, so that the hysteresis comparator has the characteristics of high integration and low power consumption.

[0049] The first stage inverter INV1 includes a first input tube and a first load tube, and the configuration of the feedback wire 20 is determined according to the number of gates of the first input tube M1 and the first load tube M2 of the first stage inverter INV1.

[0050] Specifically, when the first input tube M1 is a dual-gate field effect tube, the 2n-th stage inverter INV in the hysteresis comparator circuit 2n The output end of is connected to the second gate of the first input tube M1 to form a first feedback wire, so as to realize that the gate signal on the first gate of the first input tube and the feedback signal on the second gate of the first input tube change in phase, n=1, 2, 3, ..., N. In the case where the first load tube M2 is a dual-gate field effect transistor, the 2n+1th stage inverter INV in the hysteresis comparator circuit 2n+1 The output end of is connected to the second gate of the first load tube M2 to form a second feedback conductor, so as to realize that the gate signal on the first gate of the first load tube M2 and the feedback signal on the second gate of the first load tube M2 change in phase, n=1, 2, 3, ..., N. The first feedback conductor and the second feedback conductor are as follows Figure 2 As shown by the red solid line in the middle, the two feedback electrical conductors 20 can exist simultaneously or separately, and the voltage carried on the two feedback electrical conductors 20 has the same change direction as the voltage carried on the other gate of the connected dual-gate field effect transistor, that is, the two voltages increase or decrease simultaneously.

[0051] Therefore, in the embodiment of the present application, the first input tube can be selectively set as a dual-gate field effect tube, and positive feedback is formed through the first feedback electrical conductor between the first input tube and the output end of the even-numbered inverter. The first load tube can also be selectively set as a dual-gate field effect tube, and positive feedback is formed through the second feedback electrical conductor between the first load tube and the output end of the odd-numbered inverter. This not only simplifies the circuit structure and reduces the difficulty of on-chip integration, but also improves the flexibility of implementing the positive feedback process.

[0052] It should be noted that, in some embodiments of the present application, the gate of the input tube of the first-stage inverter INV1 is configured as the input terminal of the hysteresis comparator, and the last even-numbered inverter INV 2N The connection node between the input tube and the load tube is configured as the output terminal of the hysteresis comparator.

[0053] In some embodiments of the present application, Figure 2 As shown, the hysteresis comparator circuit further includes a power supply wire group, wherein the power supply wire group includes a first power line L DD and the second power line L SS , wherein the drain of the load tube in each inverter 10 is connected to the first power line L DD The source of the input tube in each inverter 10 is connected to the second power line L SS connect.

[0054] The power supply wire group is configured to select the first power line L DD and the second power line L SS One of them provides the input signal V for the hysteresis comparator circuit IN , you can also choose other signal sources as the input signal V IN , where the input signal V IN It is sent to the first gate of the first input tube in the first-stage inverter INV1.

[0055] In the embodiment of the present application, the first power line L DD The upper carrier voltage signal V DD , the second power line L SS The upper load voltage signal V SS The first gate of the first input tube in the first-stage inverter INV1 is used as the input conductor L of the hysteresis comparator circuit. IN , select the first power line L DD and the second power line L SS One of the input electrical conductors L IN Connection to provide input signal V IN .

[0056] The embodiment of the present application uses a power supply wire group to flexibly select any one of the first power line and the second power line as the input signal, so as to use different input voltage requirements and quickly switch the source of the input signal in different application scenarios, thereby improving the adaptability of the hysteresis comparator circuit. In addition, the circuit design of providing the input signal by the power supply wire group reduces the need for additional input signal path design, that is, there is no need to set up an additional input signal generation circuit, thereby greatly simplifying the circuit structure and making the hysteresis comparator circuit easier to integrate on chip.

[0057] It should be noted that, in the embodiment of the present application, the above input signal V IN You can also select other signal sources for configuration, that is, the input signal V IN Not limited to the first power line L DD The upper carrier voltage signal V DD and the second power line L SS The upper load voltage signal V SS , or other voltage signals.

[0058] In some embodiments of the present application, the first gate of each load tube is connected to one of the source and the drain of the load tube, that is, regardless of whether the load tube is a dual-gate field effect tube, the first gate of the load tube in each inverter 10 can be connected to its own source or drain. Since the gain effect achieved by connecting the first gate of the load tube to the source is better, the following description of the embodiments of the present application takes the case where the first gate of the load tube is connected to the source as an example, but this does not mean that the first gate of the load tube in the embodiments of the present application can only be connected to the source.

[0059] In some embodiments of the present application, when the number of cascaded inverters in the hysteresis comparator circuit is an even number, the first input tube M1 is a dual-gate field effect tube. When the number of cascaded inverters in the hysteresis comparator circuit is an odd number, the first load tube M2 is a dual-gate field effect tube. The following will be specifically described in conjunction with the corresponding implementation methods for the cases where the number of cascaded inverters is an even number and an odd number.

[0060] In some embodiments of the present application, Figure 3 and Figure 4 The structure of the hysteresis comparator circuit is shown in the case where the cascade number of inverters is an even number.

[0061] Among them, the first input tube M1 is set as a dual-gate field effect tube, so the output end of the 2n-stage inverter is connected to the second gate of the first input tube M1 to form a first feedback conductor 21, so as to realize that the gate signal on the first gate of the first input tube M1 and the feedback signal on the second gate of the first input tube M1 change in the same phase, n=1, 2, 3, ..., N.

[0062] In addition, when the first load tube M2 is a dual-gate field effect tube, the output end of the 2n+1th stage inverter is connected to the second gate of the first load tube M2 to form a second feedback electrical conductor 22, so as to realize that the gate signal on the first gate of the first load tube M2 and the feedback signal on the second gate of the first load tube M2 change in the same phase, n=1, 2, 3, ..., N.

[0063] It should be noted that if Figure 3 and Figure 4 The circuit structure of the hysteresis comparator with two inverters cascaded is schematically shown, but it does not mean that the circuit can only be composed of two stages of inverters.

[0064] like Figure 3 and Figure 4 As shown, the hysteresis comparator circuit includes a first-stage inverter 101 and a second-stage inverter 102 in cascade connection, wherein the first-stage inverter 101 includes a first input tube M1, and the second-stage inverter 102 includes a second input tube M3, wherein the first input tube M1 is a dual-gate field effect tube. The output end of the first-stage inverter 101 is connected to the first gate of the second input tube M3 to realize the cascade connection between the first-stage inverter 101 and the second-stage inverter 102. A first feedback wire 21 (such as Figure 3 and Figure 4 The gate signal on the first gate of the first input tube M1 and the feedback signal on the second gate of the first input tube M1 are changed in phase.

[0065] Furthermore, the second input tube M3 is a dual-gate field effect tube, wherein the bias voltage V B Used to adjust the hysteresis window width of the hysteresis comparator circuit.

[0066] Specifically, Figure 3 An embodiment in which both the first input tube M1 and the first load tube M2 of the first-stage inverter 101 are dual-gate field effect tubes is shown. Figure 4 Another embodiment is shown in which the first input tube M1 of the first stage inverter 101 is a dual-gate field effect tube. When the number of inverter cascades in the hysteresis comparator circuit is an even number, the first input tube M1 in the first stage inverter 101 is used as the connection end of the first feedback wire 21, so the first input tube M1 must be set as a dual-gate field effect tube, and the first load tube M2 in the first stage inverter 101 can be a single-gate field effect tube or a dual-gate field effect tube. In addition, the second input tube M3 in the second stage inverter 102 is used as the bias voltage V BTherefore, the second input tube M3 must be set as a dual-gate field effect tube, and the second load tube M4 in the second-stage inverter 102 can be a single-gate field effect tube or a dual-gate field effect tube. The first-stage output wire L connected between the output end of the first-stage inverter 101 and the first gate of the second input tube M3 O1 The first output voltage V O1 The first feedback conductor 21 carries the second output voltage V O2 .

[0067] Below is the input signal V IN =V SS For example, Figure 3 and Figure 4 The working principle of the hysteresis comparator circuit shown is explained.

[0068] At the input signal V IN =V SS In the case of , the first input tube M1 is turned off, the first load tube M2 is turned on, and the first output conductor L O1 The voltage V O1 =V DD . High level V O1 The second input tube M3 is turned on, so the voltage V on the first feedback conductor 21 is O2 =V SS The low level V O2 The first feedback signal V is fed back to the second gate of the first input tube M1 via the first feedback wire 21, so that the first input tube M1 is in a deep cut-off state. IN In the process of gradually changing from low level to high level, the first input tube M1 is gradually turned on so that V O1 The pull-down current of the second input tube M3 gradually decreases, and under the pull-up action of the second load tube M4, the voltage V on the first feedback wire 21 decreases. O2 Gradually increasing, gradually increasing V O2 This also causes the threshold voltage of the first input tube M1 to decrease, and the pull-down current of the first input tube M1 gradually increases, making V O1 Faster drop to low level V SS reaches a stable state. Similarly, when the input signal V IN In the process of gradually changing from high level to low level, the first input tube M1 is gradually turned off so that V O1 The pull-down current of the second input tube M3 gradually increases, and the current of the second load tube M4 is constant. The voltage V on the first feedback wire 21 is O2 Gradually decreasing. Gradually decreasing V O2 This in turn increases the threshold voltage of M1, and the pull-down current of M1 gradually decreases, making V O1Increases faster to a high level V DD Therefore, the second stage output voltage V O2 The first feedback wire 21 is fed back to the second gate of the first input tube M1, forming a signal that changes in phase with the signal of the first gate of the first input tube M1, that is, forming positive feedback to achieve the hysteresis effect. O2 Before the state changes from high to low, the threshold voltage of the first input tube M1 is always at a small value. O2 Before the state changes from low to high, the threshold voltage of the first input tube M1 is always at a relatively large value. Therefore, the flip voltages corresponding to the two state transitions are different, thereby causing a hysteresis effect.

[0069] The embodiment of the present application proposes a hysteresis comparator circuit composed of two cascaded inverters, and the output signal of the second-stage inverter 102 is fed back to the second gate of the first input tube M1 in the first-stage inverter 101 through the first feedback wire 21, so that the two gates of the first input tube M1 produce a positive feedback effect of the same-phase change of the gate voltage, thereby forming a hysteresis effect. Therefore, the embodiment of the present application uses the hysteresis comparator formed by the cascaded inverter and the dual-gate field effect transistor, which greatly simplifies the circuit structure and reduces the number of transistors, thereby reducing the difficulty of on-chip integration of the hysteresis comparator and reducing the power consumption of the circuit.

[0070] In addition, in the hysteresis comparator circuit proposed in the embodiment of the present application, the second input tube M3 is set as a dual-gate field effect tube, so that the other gate of the second input tube M3 is connected to the bias voltage V B , so that the hysteresis window width can be flexibly adjusted electrically, thereby improving the applicability and adjustability of the hysteresis comparator and giving the hysteresis comparator great design freedom.

[0071] Further, Figure 5 It shows the use of Figure 4 The IF circuit composed of the hysteresis comparator circuit shown in the figure is used to illustrate an application scenario of the embodiment of the present application. IN As the input conductor carries the input voltage V IN , respectively connected to the drain of the transistor M7, the first gate of the first input tube M1 and one end of the current source I1, and the other end of the current source I1 is connected to the first power line L DD The capacitor C is connected between the source and drain of the transistor M7, and the source of the transistor M7 is connected to the second power line L SS , the gate of transistor M7 is connected to the output end of the last even-numbered inverter, that is, the output end of the hysteresis comparator. Figure 5Taking the case of two inverters cascaded as an example, the gate of transistor M7 is connected to the output end of the second-stage inverter INV2. If the number of inverter cascades is 4, the gate of transistor M7 is connected to the output end of the fourth-stage inverter INV4. The same applies to the case of other even-numbered inverter cascades. It should be noted that transistor M7 can be a single-gate thin-film transistor or a dual-gate thin-film transistor. In the embodiment of the present application, a single-gate thin-film transistor is taken as an example. In addition, the current source I1 can also be a sensor that provides a current output.

[0072] Below Figure 5 The working principle of the IF circuit shown in the figure is as follows: When the current generated by the current source I1 charges the capacitor C, the input voltage V IN Gradually increases, when V IN Increases to the upper threshold voltage V of the hysteresis comparator TP When the second stage output voltage V O2 From low level to high level, transistor M7 is turned on, and the input voltage V IN starts to decrease, during which time V O2 remains high until V IN Reduced to the lower threshold voltage V TN When V O2 From high level to low level, a complete pulse is generated. O2 After it becomes low level, transistor M7 is turned off, and current source I1 continues to charge capacitor C, making the input voltage V IN The frequency of the pulse output is closely related to the current of the current source I1 and the size of the capacitor C.

[0073] Therefore, the hysteresis comparator circuit structure proposed in the embodiment of the present application is simple and easy to integrate on-chip. Compared with the related technology, it is easier to integrate with the sensor to realize the integrated circuit of the single-chip system, which is conducive to the realization of on-chip pulse neural network.

[0074] In some embodiments of the present application, Figure 6 and Figure 7 The structure of the hysteresis comparator circuit is shown in the case where the cascade number of inverters is an odd number.

[0075] Among them, the first load tube M2 is set as a dual-gate field effect tube, so the output end of the 2n+1th stage inverter is connected to the second gate of the first load tube M2 to form a second feedback conductor 22, so as to realize that the gate signal on the first gate of the first load tube M2 and the feedback signal on the second gate of the first load tube M2 change in the same phase, n=1, 2, 3, ..., N.

[0076] In addition, the first input tube M1 is set as a dual-gate field effect tube, so the output end of the 2n-stage inverter is connected to the second gate of the first input tube M1 to form a first feedback conductor 23, so as to realize that the gate signal on the first gate of the first input tube M1 and the feedback signal on the second gate of the first input tube M1 change in the same phase, n=1, 2, 3, ..., N.

[0077] like Figure 6 As shown, the hysteresis comparator circuit includes a first-stage inverter 101, a second-stage inverter 102 and a third-stage inverter 103. It should be noted that: Figure 6 The hysteresis comparator circuit including three-stage inverters is schematically shown, but it does not mean that the circuit can only be composed of three-stage inverters. Among them, the first-stage inverter 101 includes a first input tube M1 and a first load tube M2, the second-stage inverter 102 includes a second input tube M3 and a second load tube M4, and the third-stage inverter 103 includes a third input tube M5 and a third load tube M6. The first load tube M2, the second input tube M3 and the third input tube M5 are configured as dual-gate field effect tubes. The first input tube M1, the second input tube M3 and the third input tube M5 can be single-gate field effect tubes or dual-gate field effect tubes. Here, the dual-gate field effect tube is used as an example for description.

[0078] The first-stage output conductor L connected between the output end of the first-stage inverter 101 and the first gate of the second input tube M3 O1 The first output voltage V O1 The second-stage output conductor L connected between the output end of the second-stage inverter 102 and the first gate of the third input tube M5 O2 The second output voltage V O2 , the second feedback conductor 22 (such as Figure 6 The third output voltage V O3 .

[0079] Therefore, in the embodiment of the present application, when the number of inverter cascades is an odd number, the first load tube can be set as a dual-gate field effect tube, and positive feedback can be formed through the second feedback electrical conductor between the first load tube and the output end of the odd-numbered inverter, which not only simplifies the circuit structure and reduces the difficulty of on-chip integration, but also improves the flexibility of implementing the positive feedback process.

[0080] Below is the input signal V IN =V SS For example, Figure 7 The working principle of the hysteresis comparator circuit shown is explained.

[0081] At the input signal V IN =V SSIn the case of , the first input tube M1 is turned off, the first load tube M2 is turned on, and the first output conductor L O1 The voltage V O1 =V DD . High level V O1 The second input tube M3 is turned on, so the second output conductor L O2 The second output voltage V O2 =V SS The low level V O2 The third input tube M5 is turned off, so the third output voltage V O3 =V DD This high level V O3 The second feedback wire 22 is fed back to the second gate of the first load tube M2, so that the threshold voltage of the first load tube M2 is reduced and the pull-up resistance is smaller. IN In the process of gradually changing from low level to high level, the first input tube M1 is gradually turned on so that V O1 The pull-down current of the second input tube M3 gradually decreases, and under the pull-up action of the second load tube M4, the second-stage output conductor L O2 The voltage V O2 Gradually increasing. Gradually increasing V O2 This causes the third input tube M5 to gradually open, and the voltage V on the second feedback conductor 22 O3 Gradually decreases. O3 The threshold voltage of the first load tube M2 increases, and the pull-up current of the first load tube M2 decreases gradually, which leads to V O1 Faster drop to low level V SS reaches a stable state. Similarly, when V IN In the process of gradually changing from high level to low level, the first input tube M1 is gradually turned off so that V O1 The pull-down current of the second input tube M3 gradually increases, and the current of the second load tube M4 is constant. O2 The voltage V O2 Gradually decreasing. Gradually decreasing V O2 This causes the third input tube M5 to be gradually turned off, and the voltage V on the second feedback conductor 22 O3 Gradually increasing. Gradually increasing V O3 This also causes the threshold voltage of the first load tube M2 to decrease, and the pull-up current of the first load tube M2 gradually increases, so that V O1 Increases faster to a high level V DD Therefore, the third-stage output voltage V O3The second feedback wire 22 is connected to the second gate of the first load tube M2 of the first stage inverter 101, and a signal that changes in phase with the signal of the first gate of the first load tube M2 is constructed, that is, a positive feedback is formed to realize the hysteresis effect. O3 Before the state changes from high to low, the threshold voltage of the first load tube M2 is always at a small value. O3 Before the state changes from low to high and before the state is flipped, the threshold voltage of the first load transistor M2 is always at a relatively large value, so the flip voltages corresponding to the two state transitions are different, thereby causing a hysteresis effect.

[0082] In other embodiments of the present application, Figure 7 The figure shows the case where the first input tube M1 is a dual-gate field effect tube and the first input tube M1 and the first load tube M2 both participate in forming a feedback electrical conductor, wherein, when the first input tube M1 is a dual-gate field effect tube, the output end of the 2n-stage inverter is connected to the second gate of the first input tube M1 to form a first feedback electrical conductor 23, so as to realize that the gate signal on the first gate of the first input tube M1 and the feedback signal on the second gate of the first input tube M1 change in phase, n=1, 2, 3, ..., N.

[0083] like Figure 7 As shown, the hysteresis comparator circuit includes a first-stage inverter 101, a second-stage inverter 102 and a third-stage inverter 103. It should be noted that: Figure 7 The hysteresis comparator circuit including three-stage inverters is schematically shown, but it does not mean that the circuit can only be composed of three-stage inverters. Among them, the first-stage inverter 101 includes a first input tube M1 and a first load tube M2, the second-stage inverter 102 includes a second input tube M3 and a second load tube M4, and the third-stage inverter 103 includes a third input tube M5 and a third load tube M6. The second input tube M3 and the third input tube M5 can be single-gate field effect tubes or dual-gate field effect tubes. Here, the dual-gate field effect tube is taken as an example for description.

[0084] The first-stage output conductor L connected between the output end of the first-stage inverter 101 and the first gate of the second input tube M3 O1 The first output voltage V O1 The second-stage output conductor L connected between the output end of the second-stage inverter 102 and the first gate of the third input tube M5 O2 The second output voltage V O2 , the first feedback conductor 23 (such as Figure 7 The third output voltage V O3 .

[0085] The operation process of the hysteresis comparator circuit when the first input tube M1 is a dual-gate field effect tube is the same as that of the embodiment corresponding to the case where the number of inverters is two. Figure 3 and Figure 4 The working process of the embodiment shown in the figure illustrates that by replacing the second stage inverter with the 2nth stage inverter constituting the first feedback electric wire 23, the positive feedback constituting the hysteresis effect can be derived, which will not be described in detail here.

[0086] Therefore, in the embodiment of the present application, when the number of inverter cascades is an odd number, the first load tube can be set as a dual-gate field effect tube, and the first input tube can be selectively set as a dual-gate field effect tube, and positive feedback can be formed by forming a first feedback electrical conductor 23 between the first input tube and the output end of the even-numbered inverter, and positive feedback can be formed by forming a second feedback electrical conductor 22 between the first load tube and the output end of the odd-numbered inverter, and only the second feedback electrical conductor 22 can be set, and the first feedback electrical conductor 23 and the second feedback electrical conductor 22 can be set at the same time, thereby not only simplifying the circuit structure and reducing the difficulty of on-chip integration, but also improving the flexibility of realizing the positive feedback process.

[0087] In some embodiments of the present application, the third input tube in at least one inverter in the hysteresis comparator circuit is a dual-gate field effect tube, and the second gate of the third input tube is configured to adjust the hysteresis window width of the hysteresis comparator circuit according to the connected bias voltage.

[0088] Specifically, under the premise that there is at least one dual-gate field effect transistor in each inverter, the second-stage inverter 102 may also be composed of a second input tube M3 configured as a single-gate field effect transistor and a second load tube M4 configured as a dual-gate field effect transistor. Similarly, the third-stage inverter 103 may also be composed of a third input tube M5 configured as a single-gate field effect transistor and a third load tube M6 configured as a dual-gate field effect transistor. However, it is necessary to ensure that at least one of the second input tube M3 and the third input tube M5 is a dual-gate field effect transistor as the third input tube, so as to adjust the hysteresis window width of the hysteresis comparator circuit according to the bias voltage connected.

[0089] For example, in Figure 6 In another embodiment of the hysteresis comparator circuit shown in FIG. 1 , the second gate of the first input tube M1 is connected to the bias voltage V B1 , the second gate of the second input tube M3 is connected to the bias voltage V B2 , the second gate of the third input tube M5 is connected to the bias voltage V B3 .exist Figure 7 In one embodiment of the hysteresis comparator circuit shown in FIG. 1 , the second gate of the second input tube M3 is connected to the bias voltage V B1 , the second gate of the third input tube M5 is connected to the bias voltage VB2 .

[0090] Therefore, in the hysteresis comparator circuit proposed in the embodiment of the present application, at least one input tube is set as a dual-gate field effect tube, so that the other gate of the input tube is connected to the bias voltage, and the bias voltage V B1 、V B2 and V B3 , the width of the hysteresis window, the upper threshold voltage and the lower threshold voltage of the comparator can be adjusted, so that the hysteresis window width can be flexibly adjusted electrically, thereby improving the applicability and adjustability of the hysteresis comparator and giving the hysteresis comparator great design freedom.

[0091] Likewise, Figure 8 It shows the use of Figure 7 The IF circuit composed of the hysteresis comparator circuit shown in the figure is used to illustrate an application scenario of the embodiment of the present application. IN As the input conductor carries the input voltage V IN , respectively connected to the drain of the transistor M7, the first gate of the first input tube M1 and one end of the current source I1, and the other end of the current source I1 is connected to the first power line L DD The capacitor C is connected between the source and drain of the transistor M7, and the source of the transistor M7 is connected to the second power line L SS The gate of transistor M7 is connected to the output of the second inverter, that is, the output of the last even-numbered inverter, that is, the output of the hysteresis comparator. It should be noted that transistor M7 can be a single-gate thin film transistor or a double-gate thin film transistor. In the embodiment of the present application, a single-gate thin film transistor is used as an example. In addition, the current source I1 can also be a sensor that provides a current output.

[0092] Below Figure 8 The working principle of the IF circuit shown in the figure is as follows: When the current generated by the current source I1 charges the capacitor C, the input voltage V IN Gradually increases, when V IN Increases to the upper threshold voltage V of the hysteresis comparator TP When the second output voltage V O2 From low level to high level, transistor M7 is turned on, and the input voltage V IN starts to decrease, during which time V O2 remains high until V IN Reduced to the lower threshold voltage V TN When V O2 From high level to low level, a complete pulse is generated. O2 After it becomes low level, transistor M7 is turned off, and current source I1 continues to charge capacitor C, making the input voltage V INThe current of the current source I1 and the capacitance C are closely related.

[0093] Therefore, the hysteresis comparator circuit structure proposed in the embodiment of the present application is simple and easy to integrate on-chip. Compared with the related technology, it is easier to integrate with the sensor to realize the integrated circuit of the single-chip system, which is conducive to the realization of on-chip pulse neural network.

[0094] Furthermore, in an embodiment of the present application, the above-mentioned dual-gate field effect transistor is composed of a channel region, a drain region and a source region, wherein a gate is placed near the channel region, the drain region is connected to the drain, the source region is connected to the source, and the channel region material is at least one of amorphous silicon, polycrystalline silicon or metal oxide semiconductor.

[0095] Fig. 9 The device interface diagram of the above-mentioned dual-gate field effect transistor, single-gate field effect transistor and capacitor element is shown. Specifically, a layer of insulating material 202 is deposited on the surface of the substrate material 201, and then a conductive material 203 is deposited on the insulating material 202. After patterning, this layer of conductive material 203 will serve as the bottom gate 203A of the dual-gate transistor and the bottom electrode 203B of the capacitor. Then, the insulating material 204 is deposited to isolate the electrode material and the active layer. After the active layer material 205 is deposited and patterned, it will serve as the channel 205A of the dual-gate transistor, the channel 205B of the single-gate transistor and the upper plate 205C of the capacitor. Immediately after depositing a layer of insulating material 206, a layer of conductive material is deposited and patterned to form the top gate 207A of the dual-gate thin film transistor and the top gate 207B of the single-gate thin film transistor. The last layer of insulating material is covered on the surface 207 to form a new insulating layer 208. After the opening, new conductive material 209 is deposited and patterned to form a source 209A and a drain 209B of a dual-gate thin film transistor, a source 209C and a drain 209D of a single-gate thin film transistor, and an upper plate electrode 209E of a capacitor.

[0096] The dual-gate field effect transistor input four-port device in the embodiment of the present application has a source port, a drain port and two parallel gate ports. Compared with the single-gate thin-film transistor in the related art, the dual-gate field effect transistor provides an additional gate port, which can introduce an in-phase signal path without the need for additional transistors, and independently control the voltage to adjust the comparison threshold window width and size, thereby reducing the number of transistors in the hysteresis comparator, greatly simplifying the circuit structure, and making it easy to achieve on-chip integration.

[0097] Correspondingly, an embodiment of the present application further provides an integrated chip, which includes: an integrated circuit unit, wherein the integrated circuit unit includes the hysteresis comparator circuit described in the above embodiment.

[0098] The specific configuration of each of the above modules and units and further functional description are the same as those of the above corresponding embodiments and will not be repeated here.

[0099] The integrated chip proposed in this embodiment, by using a hysteresis comparator circuit composed of a dual-gate structure, constitutes a positive feedback mechanism to realize the hysteresis effect, thereby generating different flip voltages in the process of the input signal from low to high or from high to low, forming a hysteresis effect. Compared with the traditional hysteresis circuit structure, the integrated chip proposed in this application avoids the complex gain control and feedback adjustment of the operational amplifier, can more efficiently meet the computing requirements of bionic simulation systems such as SNNs, and reduces the number of circuit transistors, greatly simplifies the complexity of the integrated chip circuit layout, and has the characteristics of low power consumption.

[0100] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0101] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0102] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0103] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

[0104] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A hysteresis comparator circuit based on a dual-gate field effect transistor, characterized in that: The hysteresis comparator circuit comprises: At least two cascaded inverters, each of the inverters comprises at least one input tube and one load tube, wherein the drain of the input tube is connected to the source of the load tube, and the connection node is configured as the output end of the inverter, and at least one of the input tube and the load tube of each inverter is a dual-gate field effect tube; A feedback conductor is connected between the second gate of the dual-gate field effect transistor in the first-stage inverter and the output end of other inverters, so that the signals on the first gate and the second gate of the dual-gate field effect transistor change in phase to form positive feedback to achieve hysteresis effect.

2. The hysteresis comparator circuit according to claim 1, characterized in that: The hysteresis comparator circuit includes a first-stage inverter, which includes a first input tube and a first load tube. The configuration of the feedback wire is determined according to the number of gates of the first input tube and the first load tube of the first-stage inverter.

3. The hysteresis comparator circuit according to claim 2, characterized in that: In the case where the first input tube is a dual-gate field effect tube, the output end of the 2n-stage inverter in the hysteresis comparator circuit is connected to the second gate of the first input tube to form a first feedback conductor, so as to realize that the gate signal on the first gate of the first input tube and the feedback signal on the second gate of the first input tube change in the same phase, n=1, 2, 3, ..., N.

4. The hysteresis comparator circuit according to claim 2, characterized in that: In the case where the first load tube is a dual-gate field effect tube, the output end of the 2n+1th inverter in the hysteresis comparator circuit is connected to the second gate of the first load tube to form a second feedback conductor, so as to realize that the gate signal on the first gate of the first load tube and the feedback signal on the second gate of the first load tube change in phase, n=1, 2, 3, ..., N.

5. The hysteresis comparator circuit according to claim 2 or 3, characterized in that: When the number of cascaded inverters in the hysteresis comparator circuit is an even number, the first input tube is a dual-gate field effect tube.

6. The hysteresis comparator circuit according to claim 2 or 4, characterized in that: When the number of cascaded inverters in the hysteresis comparator circuit is an odd number, the first load transistor is a dual-gate field effect transistor.

7. The hysteresis comparator circuit according to claim 1 or 2, characterized in that: The third input tube in at least one inverter in the hysteresis comparator circuit is a dual-gate field effect tube, and the second gate of the third input tube is configured to adjust the hysteresis window width of the hysteresis comparator circuit according to the input bias voltage.

8. The hysteresis comparator circuit according to claim 1, characterized in that: In the case that the load tube is a single-gate field effect tube, the first gate of the load tube is connected to one of the source and the drain of the load tube.

9. The hysteresis comparator circuit according to claim 1, characterized in that: The hysteresis comparator circuit further includes a power supply wire group, the power supply wire group includes a first power supply wire and a second power supply wire, wherein the drain of the load tube in each of the inverters is connected to the first power supply wire, and the source of the input tube in each of the inverters is connected to the second power supply wire; The power supply wire group is configured to select one of the first power line and the second power line to provide an input signal for the hysteresis comparator circuit, wherein the input signal is sent to the first gate of the first input tube in the first-stage inverter.

10. The hysteresis comparator circuit according to claim 1, characterized in that: The gate of the input tube of the first-stage inverter is configured as the input end of the hysteresis comparator, and the connection node of the input tube and the load tube in the last even-numbered inverter is configured as the output end of the hysteresis comparator.

11. An integrated chip, characterized in that: The integrated chip comprises: An integrated circuit unit, wherein the integrated circuit unit comprises the hysteresis comparator circuit according to any one of claims 1-10.

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