Bandwidth calibration circuit of active filter and bandwidth calibration method of active filter

Abstract

The invention provides a bandwidth calibration circuit of an active filter and a bandwidth calibration method of the active filter. The bandwidth calibration circuit of the active filter comprises a frequency divider, a detection module and a control module, wherein the frequency divider is used for carrying out frequency division on an input clock signal, generating at least two paths of switching signals and transmitting the switching signals to the detection module; the detection module is used for responding to the at least two paths of switching signals, detecting whether the bandwidth parameter of the active filter reaches a preset parameter range, and if not, sending a driving signal to the control module; and the control module is used for calibrating a control signal based on the driving signal, and the control signal is used for controlling on-off of a capacitor in the active filter. Through the bandwidth calibration circuit, it is ensured that the active filter always operates within the optimal performance range, the bandwidth calibration precision and efficiency are improved, the calibration process is simplified, the flexibility and reliability of the system are enhanced, the bandwidth calibration circuit is suitable for various application scenes, and the overall performance and stability of the active filter are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a bandwidth calibration circuit of an active filter and a bandwidth calibration method of an active filter. Background Art

[0002] With the rapid development of modern communication technology, radio frequency equipment is increasingly used in multiple fields. As a key component to ensure signal purity and stability, the performance of active filters has a direct impact on communication quality.

[0003] Currently, the industry uses a variety of modes to calibrate the changes in active filter bandwidth, such as series resistor arrays, sampling output frequency, and multi-way selection switches. These methods control the resistance value or monitor the working status of the filter to adapt to the impact of environmental changes and manufacturing deviations.

[0004] However, all of the above technical solutions have certain drawbacks. For example, the non-ideal switches of the series resistor array will reduce the calibration accuracy; the frequency sampling method increases the extra power consumption and is susceptible to interference; and the multi-way selection switch requires a larger chip area to prevent signal crosstalk. Therefore, in order to meet the requirements of chip volume and calibration accuracy at the same time, it is urgent to design a new bandwidth calibration circuit. Summary of the invention

[0005] In view of this, the embodiments of this specification provide a bandwidth calibration circuit of an active filter and a bandwidth calibration method of an active filter to solve the technical defects existing in the prior art.

[0006] According to a first aspect of the embodiments of this specification, a bandwidth calibration circuit for an active filter is provided, comprising: a frequency divider, a detection module and a control module; wherein: A frequency divider, used for dividing the input clock signal to generate at least two switch signals for transmission to the detection module; A detection module, for detecting whether a bandwidth parameter of the active filter reaches a preset parameter range in response to at least two switch signals, and if not, sending a driving signal to the control module; The control module is used to calibrate the control signal based on the drive signal, and the control signal is used to control the on and off of the capacitor in the active filter.

[0007] According to a second aspect of an embodiment of this specification, a bandwidth calibration method for an active filter is provided, which is applied to a bandwidth calibration circuit of the active filter, wherein the bandwidth calibration circuit includes a frequency divider, a detection module, and a control module; the method includes: The frequency divider divides the input clock signal to generate at least two switch signals to be transmitted to the detection module; The detection module detects whether the bandwidth parameter of the active filter reaches a preset parameter range in response to at least two switch signals, and sends a driving signal to the control module if it does not; The control module calibrates the control signal based on the driving signal, and the control signal is used to control the on and off of the capacitor in the active filter.

[0008] According to a third aspect of an embodiment of this specification, a radio frequency device is provided, comprising the above-mentioned bandwidth calibration circuit of the active filter and the active filter; the bandwidth calibration circuit of the active filter is used to send a control signal to the active filter; the active filter is used to control the on and off of the capacitor based on the control signal.

[0009] According to a fourth aspect of the embodiments of this specification, a communication device is provided, including the above-mentioned radio frequency device.

[0010] The present invention provides a bandwidth calibration circuit for an active filter, comprising: a frequency divider, a detection module and a control module; wherein the frequency divider is used to divide the input clock signal, generate at least two switch signals and transmit them to the detection module; the detection module is used to detect whether the bandwidth parameter of the active filter reaches a preset parameter range in response to the at least two switch signals, and if not, send a drive signal to the control module; the control module is used to calibrate the control signal based on the drive signal, and the control signal is used to control the on-off of the capacitor in the active filter. At least two switch signals are generated by the frequency divider, and the bandwidth parameter of the active filter is detected by the detection module and compared with the preset parameter range. If it is not reached, the drive signal is sent to the control module, and the control module generates a control signal based on the drive signal / calibrates the control signal. The calibrated control signal can stabilize the bandwidth parameter within the preset parameter range, which not only improves the accuracy and efficiency of bandwidth calibration, simplifies the calibration process, but also enhances the flexibility and reliability of the system, is suitable for a variety of application scenarios, significantly improves the overall performance and stability of the active filter, and reduces the need for external manual intervention through the automated calibration process, thereby improving the signal purity and reliability of the communication system. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of a bandwidth calibration circuit of an active filter provided as an optional embodiment of the present specification; Figure 2 A schematic diagram of the structure of a frequency divider circuit in a bandwidth calibration circuit of an active filter provided in an optional embodiment of the present specification; Figure 3 A schematic diagram of a circuit structure of a capacitor array provided as an optional embodiment of this specification; Figure 4A schematic diagram of the circuit structure of a detection module in a bandwidth calibration circuit of an active filter provided in an optional embodiment of the present specification; Figure 5 A schematic diagram of a circuit structure in which a detection module in a bandwidth calibration circuit of an active filter provided in an optional embodiment of the present specification includes a third switch module; Figure 6 A schematic diagram of the circuit structure of a control module in a bandwidth calibration circuit of an active filter provided in an optional embodiment of the present specification; Figure 7 A control module in a bandwidth calibration circuit of an active filter provided in an optional embodiment of the present specification includes a circuit structure diagram of a series-connected full adder and a data selector; Figure 8 A schematic diagram of a circuit structure of a bandwidth calibration circuit of an active filter provided in one embodiment of this specification; Fig. 9 A simulation waveform diagram of a bandwidth calibration circuit of an active filter provided in an optional embodiment of the present specification; Fig.10 A flow chart of a bandwidth calibration method for an active filter provided in one embodiment of this specification; Fig.11 A schematic diagram of the structure of a radio frequency device provided as an optional embodiment of this specification. DETAILED DESCRIPTION

[0012] Many specific details are set forth in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present invention, so the present invention is not limited to the specific implementation disclosed below.

[0013] The terms used in one or more embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit one or more embodiments of the present invention. The singular forms of "a", "said" and "the" used in one or more embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in one or more embodiments of the present invention refers to and includes any or all possible combinations of one or more associated listed items.

[0014] It should be understood that, although the terms first, second, etc. may be used to describe various information in one or more embodiments of the present invention, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of one or more embodiments of the present invention, the first may also be referred to as the second, and similarly, the second may also be referred to as the first. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0015] With the rapid development of modern communication technology, RF equipment is increasingly used in many fields such as traffic, transportation, daily life and education. As a key component to ensure signal purity and stability, the performance of the filter is directly related to the communication quality of the entire system.

[0016] At present, in order to cope with the fluctuation of active filter bandwidth caused by environmental changes and manufacturing deviations, calibration circuits are often used to calibrate the bandwidth of active filters. General calibration circuits will use modes such as series resistor arrays, sampling filter output frequencies, and multi-way selection switches. However, if the series resistor array method is used, since the controlled switch is not ideal, there will be on-resistance, and the switch off resistance is not infinite, so the entire resistor array will include the on-resistance of the switch, and the calibration accuracy is not enough. Therefore, if the on-resistance of the switch is small enough, the area will be very large (the area of ​​MOSFET transistors is inversely proportional to the on-resistance); if the method of sampling the filter output frequency requires a frequency-voltage conversion circuit, additional power consumption will be required, and in the layout, the voltage transmission will be interfered by environmental factors, which will reduce the calibration accuracy; if the multi-way selection switch method is used, although the interference of the switch on-resistance can be avoided, multiple clock signals are required, and the generation and transmission of clock signals need to be as far away from each other as possible to prevent crosstalk, which will cause the chip area to become larger.

[0017] In view of this, an embodiment of the present specification provides a bandwidth calibration circuit for an active filter, which generates at least two switching signals through a divider, and uses a detection module to detect the bandwidth parameter of the active filter and compare it with a preset parameter range. If the bandwidth parameter is not reached, a drive signal is sent to a control module. The control module generates a control signal based on the drive signal / calibrates the control signal. The calibrated control signal can stabilize the bandwidth parameter within the preset parameter range, which not only improves the accuracy and efficiency of bandwidth calibration, simplifies the calibration process, but also enhances the flexibility and reliability of the system, is suitable for a variety of application scenarios, significantly improves the overall performance and stability of the active filter, and reduces the need for external manual intervention through an automated calibration process, thereby improving the signal purity and reliability of the communication system.

[0018] Specifically, the present invention provides a bandwidth calibration circuit for an active filter, see Figure 1 , Figure 1 FIG. 1 is a schematic diagram showing a bandwidth calibration circuit of an active filter provided by an optional embodiment of the present specification, such as Figure 1 As shown: the bandwidth calibration circuit of the active filter includes: a frequency divider, a detection module and a control module; wherein the frequency divider is used to divide the input clock signal to generate at least two switch signals and transmit them to the detection module; the detection module is used to respond to the at least two switch signals to detect whether the bandwidth parameter of the active filter reaches a preset parameter range, and if not, send a drive signal to the control module; the control module is used to calibrate the control signal based on the drive signal, and the control signal is used to control the on and off of the capacitor in the active filter.

[0019] Specifically, an active filter (AF) is a circuit containing active components (such as operational amplifiers, transistors, etc.) that can selectively pass or block signals within a specific frequency range. It can form a frequency response through resistors and capacitors, and use active components to provide gain and isolation functions.

[0020] A frequency divider (FD or Div) is a digital circuit or analog circuit that reduces the frequency of an input clock signal to one or more output signals with lower frequencies.

[0021] Clock signal (CLK) is a periodic electrical signal, usually expressed as a series of regular high and low level alternating pulse waveforms. It is used as a time reference for synchronizing various operations in digital circuits and computer systems to ensure that all components work in a uniform rhythm. The clock signal can be generated by an oscillator (such as a crystal oscillator, ceramic resonator, etc.) and is used to synchronize key operations such as data transmission and instruction execution to ensure the stability and accuracy of the system. In the embodiments of this specification, the clock signal is used as a switch signal and is sent to the detection module.

[0022] The detection module is used to respond to the switch signal, detect the bandwidth parameter of the active filter, and determine whether the bandwidth parameter reaches the preset parameter range. If not, it sends a driving signal to the control module. The detection module is a core module of the bandwidth calibration circuit of the active filter provided by the present invention, and will be described in detail later.

[0023] The bandwidth parameter is used to measure the maximum frequency range in which the active filter can effectively transmit signals, reflecting the active filter's ability to process signals of different frequencies.

[0024] Specifically, the RC time constant can be obtained by calculating the product of the resistance value and the capacitance value in the active filter (i.e., R×C), and the bandwidth parameter can be determined based on the time constant. Correspondingly, the at least two switching signals in the detection module are used to control the charging time and the discharging time of the capacitor to obtain the capacitance value, and determine the bandwidth parameter in combination with the resistance value.

[0025] The control module is used to calibrate the control signal according to the driving signal generated by the detection module, and send the control signal to the active filter to control the on and off of the capacitor therein to complete the bandwidth calibration of the active filter. The control module is another core module of the bandwidth calibration circuit of the active filter provided by the present invention, and will be described in detail later.

[0026] The present invention provides a bandwidth calibration circuit for an active filter, which realizes precise control of the charging and discharging time of a capacitor array by using a frequency divider to divide a clock signal into at least two switching signals; a detection module monitors whether the bandwidth parameter reaches a preset value based on these switching signals, and sends a driving signal to a control module when the condition is not met, prompting the control module to automatically adjust the on-off state of the capacitor according to the driving signal until the bandwidth parameter is stabilized within a preset range. While ensuring that the high accuracy and stability of the filter bandwidth can be maintained in the case of environmental changes or manufacturing deviations, the need for external manual intervention is reduced through an automated calibration process, thereby improving the signal purity and reliability of the communication system.

[0027] In an optional implementation of the embodiment of this specification, the bandwidth calibration circuit of the active filter further includes: a bandgap reference module; the bandgap reference module is used to provide a reference voltage to the detection module.

[0028] In the bandwidth calibration process, it is usually necessary for the reference circuit to provide a reference voltage (Vref) as a reference for calibration, so that key parameters in the circuit, such as current, voltage, etc., can be stabilized at a predetermined value and are not affected by temperature changes, power supply voltage fluctuations or manufacturing process differences. Specifically, in the embodiments of this specification, for the bandwidth calibration circuit of the active filter, the reference voltage Vref is used to compare with the capacitor voltage in the active filter to determine the calibration state of the current circuit, thereby realizing the calibration of the bandwidth circuit.

[0029] The reference voltage Vref can be provided by a variety of reference circuits, such as proportional to absolute temperature (PTAT), complementary to absolute temperature (CTAT), bandgap reference (BGR), etc., wherein the PTAT circuit can generate a voltage that increases linearly with absolute temperature; the CTAT circuit is opposite to the PTAT circuit and can generate a voltage that decreases linearly with absolute temperature; the BGR circuit can generate a stable voltage that is not affected by factors such as temperature, power supply voltage, and manufacturing process based on the characteristic that the forward voltage drop of the PN junction changes with temperature and the opposite trend that the voltage on the base resistor changes with temperature. Different reference circuits have different electrical properties and can be selected according to different actual needs. This specification does not make specific restrictions on this.

[0030] In the embodiments of this specification, preferably, a bandgap reference circuit BGR circuit is used as a bandgap reference module to provide a reference voltage Vref to the detection module.

[0031] In the embodiments of the present specification, a bandgap reference circuit (BGR circuit) is used as a bandgap reference module of a bandwidth calibration circuit of an active filter, so as to provide a highly stable reference voltage (Vref) that is not affected by temperature, power supply voltage and manufacturing process differences, thereby ensuring an accurate comparison between the capacitor voltage in the active filter and a preset value, thereby achieving efficient and accurate bandwidth calibration.

[0032] In an optional implementation of the embodiments of this specification, the at least two switching signals include a first switching signal and a second switching signal having different duty cycles; The detection module includes: a first switch module, a second switch module, a bandwidth element and a comparator, wherein the bandwidth element includes a resistor and capacitor array arranged based on an active filter; The resistor and the capacitor array share a common ground; the reference voltage is connected to the non-ground end of the resistor to generate a target current; the target current flows into the first end of the first switch module, and the second end of the first switch module is connected to the non-ground end of the capacitor array; the second switch module is connected to the two ends of the capacitor array; the first end of the comparator is connected to the non-ground end of the capacitor array, and the second end is input with the reference voltage; A first switch module, for responding to a first switch signal, and when closed, flowing a target current into the capacitor array to charge the capacitor and generate a capacitor voltage; A second switch module, configured to discharge the capacitor array in response to a second switch signal when the first switch module is disconnected and the second switch module is closed; The comparator is used to compare the capacitor voltage with the reference voltage and output a driving signal to the control module based on the comparison result.

[0033] The clock signal is divided by a frequency divider to obtain at least two switching signals, which will generate different duty cycles according to different types of frequency dividers.

[0034] Duty cycle is a parameter that describes the proportion of high level time in a pulse signal. In a complete cycle, it includes two parts, high level and low level. The duty cycle is the ratio of the duration of the high level to the entire cycle time. For example, in a pulse signal with a cycle of 1 second, if the high level lasts for 0.75 seconds, then the duty cycle is 75%.

[0035] In the specific implementation of the embodiments of this specification, a simple binary frequency divider may be used to divide the frequency of the clock signal, or a multi-stage frequency divider may be used to divide the frequency of the clock signal, and this specification does not make any specific limitation on this.

[0036] Optionally, the clock signal can be divided by four frequency dividers, see Figure 2 , Figure 2 FIG. 1 shows a schematic diagram of a frequency divider circuit structure in a bandwidth calibration circuit of an active filter provided by an optional embodiment of the present specification, such as Figure 2 As shown: By connecting four flip-flops in series to form a four-divider, the input clock signal CLK is divided, and finally two clock signals are obtained as switch signals: the first switch signal (CLK_1P) and the second switch signal (CLK_2P), and an inverter is added to the output end of the first switch signal to obtain the third switch signal (CLK_1N) of the first switch signal. Among them, the frequencies of the first switch signal, the second switch signal and the third switch signal are all 2.4MHz, the duty ratios of the first switch signal and the third switch signal are 50%, and the duty ratio of the second switch signal is 25%.

[0037] The detection module includes a first switch module, a second switch module, a bandwidth element and a comparator, wherein the bandwidth element includes a resistor and capacitor array arranged based on an active filter.

[0038] A comparator (COMP for short) is an electronic circuit used to compare the magnitudes of two voltages or currents and output corresponding high and low level signals according to the comparison results. In the embodiment of this specification, the comparator is used to compare the capacitor voltage of the capacitor array with a reference voltage.

[0039] A capacitor array (C_array) is a collection of multiple capacitors that can be selectively connected or disconnected by external control signals to achieve different total capacitance values. A capacitor array typically contains one or more fixed capacitors and a series of variable capacitors controlled by switches. Each switch can be a transistor or other type of electronic switch, and its state (on / off) is determined by a digital control signal.

[0040] The switch module uses one or more transistors (Transistor) as switch elements, and realizes the connection or disconnection of the current path in the circuit by controlling the voltage of the gate (for field-effect transistor Field-Effect Transistor, referred to as FET) or the base (for bipolar transistor Bipolar Junction Transistor, referred to as BJT). Field effect transistors FET include junction field effect transistors (JFET), metal oxide semiconductor field effect transistors (MOSFET) and other types, and bipolar transistors BJT include NPN bipolar transistors (NPN BJT), PNP bipolar transistors (PNP BJT) and other types. The specific type of transistor used to form the switch module can be selected according to actual needs, and this manual does not make specific restrictions on this.

[0041] Specifically, the bandwidth parameter is determined by calculating the product of the resistance value and the capacitance value (ie, R×C) in the active filter to obtain the RC time constant T. The capacitance value in the active filter can be simulated by the capacitor array C_array in the detection module, that is, the bandwidth parameter is determined by calculating R×C_array. In the active filter, the bandwidth can be expressed as a constant related to the time constant T. For example, the reciprocal of the time constant T, 1 / T, can be used to approximate it. Then, when the time constant T=R×C_array is a certain value after each calibration, the bandwidth of the active filter is a constant value, that is, the bandwidth calibration of the active filter is completed.

[0042] In the specific implementation of the embodiments of this specification, a capacitor array can be formed by a fixed capacitor and a plurality of variable capacitors controlled by switches, see Figure 3 , Figure 3 FIG. 1 shows a circuit structure diagram of a capacitor array provided by an optional embodiment of the present specification, such as Figure 3 As shown: C fix is a fixed capacitor, C is a unit capacitor, S0-S5 are control switches, and the corresponding control capacitor is a capacitor of C-32C unit capacitor. When the control switch gate control signal is low level (0), the capacitor in series does not participate in charging; when the switch gate control signal is high level (1), the capacitor in series participates in charging.

[0043] Among them, the capacitance value of the capacitor array C_array can be calculated by formula (1): (1) The fixed capacitance value C of the capacitor array fix It can be calculated by formula (2): (2) The unit capacitance C of the capacitor array can be calculated using formula (3): (3) In the above formula, C nom is the ideal value of the active filter integrating capacitor, bi is the digital signal controlled by each switch, N is the number of control bits of the capacitor array, and A is the designed calibration accuracy.

[0044] In the detection module, the capacitor array can be regarded as a variable capacitor, and the capacitor array and the resistor are grounded together. The reference voltage Vref generated by the bandgap reference module will be connected to the non-ground end of the resistor to generate a target current I, which can be calculated by formula (4): (4) After the target current I is generated, the target current I flows into the first end of the first switch module, the second end of the first switch module is connected to the non-ground end of the capacitor array C_array, the first end of the second switch array is connected to the non-ground end of the capacitor array C_array, the second end of the second switch array is connected to the ground end of the capacitor array C_array, the first end of the comparator is connected to the ground end of the capacitor array C_array, and the second end of the comparator inputs the reference voltage Vref.

[0045] The control end of the first switch module inputs the first switch signal CLK_1P. When CLK_1P is at a high level, the first switch module is closed. At this time, the target current I is connected to the capacitor array, that is, the capacitor array is charged to generate a capacitor voltage. The initial value of the capacitor voltage is 0. The capacitor voltage generated after charging can be calculated by formula (5): (5) In the above formula, is the time during which the first switching signal CLK_1P is at a high level.

[0046] The control end of the second switch module inputs the second switch signal CLK_2P. When the first switch signal CLK_1P is at a low level (ie, the first switch module is disconnected) and CLK_2P is at a high level, the second switch module is closed, ie, the capacitor array C_array is discharged.

[0047] The first terminal of the comparator inputs the capacitor voltage U CThe second terminal inputs the reference voltage Vref, and compares the capacitor voltage U C and a reference voltage Vref, and generates a driving signal based on the comparison result, and outputs the driving signal to the control module.

[0048] In the embodiments of the present specification, a frequency divider is used to generate switch signals with different duty cycles, the charging and discharging process of the capacitor array is accurately controlled, and a comparator is used to compare the capacitor voltage with a reference voltage, thereby achieving highly automatic calibration of the active filter bandwidth and improving the accuracy and efficiency of bandwidth calibration.

[0049] In an optional implementation of the embodiments of this specification, the comparator is specifically used to output a low-level drive signal to the control module when the capacitor voltage is less than the reference voltage; and output a high-level drive signal to the control module when the capacitor voltage is equal to the reference voltage.

[0050] The comparator COPM is used to compare the capacitor voltage U C and the reference voltage Vref, and generates a driving signal based on the comparison result. Specifically, the capacitor voltage U C The corresponding drive signal is generated and outputted based on the size of the capacitor voltage U and the reference voltage Vref. C When the capacitor voltage U C When the voltage is greater than the reference voltage Vref, a high level (1) driving signal is output to the control module.

[0051] In an optional implementation of the embodiment of the present specification, the detection module further includes: an amplifier; the amplifier is used to clamp the reference voltage to the non-ground end of the resistor to generate a target current.

[0052] An amplifier is an electronic device used to amplify the amplitude of an input signal to produce a stronger output signal while maintaining the original characteristics of the signal. There are many types of amplifiers, such as power amplifiers, differential amplifiers, operational amplifiers, etc.

[0053] Clamping is a circuit technique used to fix a specific point or level of a signal at a predetermined voltage value. It ensures that the signal does not exceed the set maximum or minimum value by adding a DC bias or limiting the signal to a certain voltage range.

[0054] In the embodiments of the present specification, preferably, an operational amplifier (OPA) is used, one input terminal of the operational amplifier OPA inputs a reference voltage Vref, and the other input terminal is connected to the non-ground terminal of the resistor, and the generated reference voltage Vref is clamped to the non-ground terminal of the resistor R to generate a target current I.

[0055] In an optional implementation of the embodiments of the present specification, the detection module further includes: a current mirror module, which is used to mirror the target current to the first end of the first switch module.

[0056] A current mirror is a circuit structure used to accurately copy the current in one branch to another branch. It usually consists of two or more matched transistors, one of which is used as a reference (input terminal) and its current is set to a known value; the other transistors generate the same or proportional output current based on this reference current.

[0057] A bias voltage VB is also generated in the current mirror. The bias voltage can be generated by a variety of methods, including a resistor divider, a bandgap reference circuit, a voltage regulator diode, an operational amplifier feedback circuit, an internal integrated bias circuit, and a startup circuit, etc. This specification does not specifically limit this. The bias voltage is used to accurately set the operating point of the transistors to ensure that they operate stably in the linear region, thereby achieving accurate and stable current replication.

[0058] In the embodiment of this specification, the current mirror module is composed of 4 transistors to form a current mirror, and the current is the target current I.

[0059] Below, combined with the attached Figure 4 The detection module in the bandwidth calibration circuit of the active filter is introduced in detail. Figure 4 , Figure 4 FIG. 1 shows a circuit structure diagram of a detection module in a bandwidth calibration circuit of an active filter provided in an optional embodiment of the present specification, such as Figure 4 As shown: The detection module includes: an amplifier OPA, a power supply VDD, MOSFET transistors M1-M6, a resistor R, a capacitor array C_array, and a comparator COMP. Among them, the transistors M1-M4 form a common source and common gate current mirror, the transistor M5 forms a first switch module, and the transistor M6 forms a second switch module. The gates of transistors M1 and M3 are connected to the output end of the amplifier, the sources of transistors M1 and M3 are connected to the power supply VDD, the drain of transistor M1 is connected to the source of transistor M2, the drain of transistor M3 is connected to the source of transistor M4, the gates of transistors M2 and M4 are connected, and there is a bias voltage VB on the gate of transistor M2; the drain of transistor M2 is connected to the reverse input end (-) of the amplifier OPA and the non-ground end of the resistor R; the drain of transistor M4 is connected to the drain of transistor M5, the source of transistor M5 is connected to the non-ground end of the capacitor array C_array, the drain of transistor M6 and the positive end (+) of the comparator COMP; the ground end of the resistor R is connected to the ground end of the capacitor array C_array, the source of transistor M6 and grounded. The positive input terminal (+) of the amplifier OPA inputs the reference voltage Vref, the gate of the transistor M5 inputs the first switching signal CLK_1P, the gate of the transistor M6 inputs the second switching signal CLK_2P, and the negative terminal (-) of the comparator COMP inputs the reference voltage Vref.

[0060] The reference voltage Vref is clamped to the non-ground end of the resistor R through the amplifier OPA to generate the target current I, and the target current I is mirrored to the first switch module (i.e., the source of the transistor M5) through the common source and common gate current mirror formed by the transistors M1-M4; then when the first switch signal CLK_1P is at a high level and the second switch signal CLK_2P is at a low level, the first switch module (transistor M5) is turned on and the second switch module (transistor M6) is turned off. At this time, the target current I will flow through the first switch module and flow into the capacitor array C_array for charging, and the capacitor voltage U C ; Capacitor voltage U C The positive input of the comparator (COMP) is compared with the reference voltage Vref input at the negative phase terminal. C <reference voltage Vref, the comparator (COMP) outputs a low-level drive signal (0) to the control module. C = reference voltage Vref, the comparator (COMP) outputs a high-level driving signal (1) to the control module; when the first switch signal CLK_1P changes from a high level to a low level, and after 1 / 4 period T, the second switch signal CLK_2P changes from a low level to a high level, and all the charges stored on the capacitor array C_array are released to the ground terminal, so that the upper capacitor voltage U of the capacitor array is C is 0.

[0061] The embodiments of this specification realize accurate automatic calibration of the filter bandwidth by integrating an operational amplifier, a common-source and common-gate current mirror, a switch module and a comparator to form a detection module, and use an operational amplifier to clamp a reference voltage to a resistor to generate a stable current, and use a current mirror to copy the current to charge a capacitor array to generate a capacitor voltage, compare the capacitor voltage with the reference voltage and output a corresponding drive signal based on the comparison result, thereby ensuring that the bandwidth calibration circuit of the active filter maintains the consistency and accuracy of the bandwidth under various conditions, simplifying the calibration process, and improving the accuracy and reliability of the calibration.

[0062] In an optional implementation of the embodiment of the present specification, the at least two switch signals further include a third switch signal which is opposite to the first switch signal; the detection module further includes: a third switch module; a first end of the third switch module is connected to a first end of the first switch module, and a second end of the third switch module is grounded; The third switch module is used to close or open in response to a third switch signal.

[0063] The third switch signal CLK_1N is an inverted signal of the first switch signal CLK_1P obtained through an inverter.

[0064] See also Figure 5 , Figure 5 FIG. 1 shows a schematic diagram of a circuit structure in which a detection module in a bandwidth calibration circuit of an active filter provided by an optional embodiment of the present specification includes a third switch module, such as Figure 5 As shown: The detection module further includes a third switch module, which is composed of a MOSFET transistor M7. The drain of the transistor M7 is connected to the drain of the transistor M4, the source of the transistor M7 is grounded, and the gate of the transistor M7 inputs a third switch signal CLK_1N.

[0065] The third switch module is controlled by the third switch signal CLK_1N, and is opposite to the on-off state of the first switch module, that is, when the first switch module is turned on, the third switch module is turned off, and when the first switch module is turned off, the third switch module is grounded. The purpose of this is to ensure that the target current I always flows through the drain of the transistor M4, to avoid the drain voltage of the transistor M5 in the first switch module being pulled up to close to the power supply voltage VDD to produce a channel length modulation effect, thereby affecting the value of the target current I of the current mirror image to be offset, resulting in inaccurate calibration results.

[0066] Among them, the channel length modulation effect (CLM) is a phenomenon that exists in field effect transistors (FETs). When the transistor operates in its saturation region, as the drain-source voltage increases, the effective length of the channel decreases, causing the slope of the output characteristic curve to change, thereby causing the output resistance of the transistor to decrease, and affecting the gain and linearity of the transistor.

[0067] In the embodiments of the present specification, a third switch signal that is opposite to the first switch signal is introduced to control an additional third switch module, thereby ensuring that the third switch module is disconnected when the first switch module is turned on, and the third switch module is turned on when the first switch module is disconnected, thereby ensuring that the target current of the current mirror image always flows stably, avoiding current offset and inaccurate calibration due to the channel length modulation effect, maintaining the accuracy of the current mirror, ensuring the accuracy and stability of the bandwidth calibration circuit of the active filter, and improving the overall performance and reliability of the system.

[0068] In an optional implementation of the embodiment of this specification, the control module includes: a trigger and a series half adder; A trigger, for responding to a driving signal and outputting a first digital signal opposite to the driving signal to the series half adder; A series half adder is used to add 1 to a binary second digital signal when the first digital signal is at a high level, wherein the number of bits of the second digital signal is the same as the number of controllable capacitors in the active filter and are both initially 0; and when the first digital signal is at a low level, the second digital signal is inverted and output as a control signal to the active filter.

[0069] A flip-flop is a basic storage unit in a digital circuit that can store one bit of binary information. It is a bistable circuit, which means that it can be stable in one of two states and will only change state under the action of an external signal. Triggers are widely used in sequential logic circuits such as registers, counters, and shift registers. Triggers can be divided into RS flip-flops (Set-Reset Flip-Flop), JK flip-flops (JK Flip-Flop), D flip-flops (DFlip-Flop, referred to as DFF), etc. according to their functions. Among them, the D flip-flop latches the input data through the clock pulse and is suitable for synchronous operation; the RS flip-flop provides simple set and reset functions, which is suitable for scenarios such as switch control; the JK flip-flop combines the functions of the RS flip-flop with the synchronization mechanism, has a more flexible operation mode, and is suitable for complex logic design. Different triggers can be selected according to actual needs, and this manual does not make specific restrictions on this.

[0070] Optionally, in the embodiment of this specification, a D flip-flop is selected.FF It is a commonly used sequential logic circuit that has the ability to store one bit of binary information. FF At the rising or falling edge of the clock signal, the output and inverted output are updated according to the state of the input data D.

[0071] A half adder is a combinational logic circuit used to perform addition operations on two single-bit binary numbers. It has two input terminals A and B, and two output terminals: one for representing the sum S, and the other for representing the carry C. In the embodiment of this specification, the half adder is connected in series with the flip-flop.

[0072] Specifically, trigger D FF After receiving the driving signal output by the detection module, a first digital signal opposite to the driving signal will be output at the reverse output terminal, and the reverse output terminal is connected to the input terminal B of the half adder, and the first digital signal is input into the series half adder Half_adder.

[0073] When the first digital signal is at a high level (1), the series half adder Half_adder adds 1 to the second digital signal; when the first digital signal is at a low level (0), the second digital signal is inverted and output as a control signal to the active filter for bandwidth calibration.

[0074] The second digital signal is used to control the controllable capacitor in the active filter. The second digital signal is a binary number of several digits, the specific digits are the same as the number of controllable capacitors, and one digital signal controls the switch state of one controllable capacitor. Specifically, the initial state of the controllable capacitors is the connected state (1), and the initial value of each digit of the second digital signal is 0. For example, the state of the controllable capacitor is 111111, which means that there are 6 controllable capacitors, and they are all connected. In this case, the second digital signal 000011 is generated, and the corresponding first digital signal is a low level (0), then the second digital signal is inverted to obtain 111100 as a control signal output to the active filter, and the controllable capacitor is controlled according to the control signal, and the state of the controllable capacitor is set to 111100, that is, the two controllable capacitors are disconnected.

[0075] In an optional implementation of the embodiment of this specification, the control module further includes: a parallel trigger; A series half adder, specifically used for adding 1 to the second binary digital signal to obtain a third digital signal, and outputting the third digital signal to the parallel trigger; The first output terminal of the parallel trigger outputs the third digital signal to the series half adder, so that the series half adder starts accumulating from the third digital signal next time; The second output terminal of the parallel trigger outputs a fourth digital signal obtained by inverting the third digital signal. The fourth digital signal is used to control the on and off of the capacitor in the detection module. The capacitor in the detection module is set based on the active filter.

[0076] See also Figure 6 , Figure 6 FIG. 1 shows a circuit structure diagram of a control module in a bandwidth calibration circuit of an active filter provided in an optional embodiment of the present specification, such as Figure 6 As shown: When the first digital signal input at the input terminal B is at a high level (1), the series half adder Half_adder adds 1 to the second digital signal to obtain a third digital signal, and outputs the third digital signal to the parallel trigger D through the output terminal S<5.0> FF The parallel trigger returns the third output signal to the input terminal A<5.0> of the series half adder Half_adder through the output terminal, so that the series half adder Half_adder starts to accumulate from the third digital signal when accumulating next time; the parallel trigger D FF <5.0> A fourth digital signal obtained by inverting the third digital signal is output through the inverting output terminal, and the fourth digital signal is used to control the on-off of the capacitor array included in the detection module.

[0077] In the embodiment of the specification, a control module is formed by a trigger and a series half adder, and a parallel trigger is introduced. The trigger is used to respond to the driving signal output by the detection module to generate an opposite first digital signal; and the second digital signal is added by 1 or inverted according to the state of the first digital signal by the series half adder to generate a signal for controlling the state of the controllable capacitor, thereby realizing accurate calibration of the bandwidth of the active filter; further, the parallel trigger ensures the continuity and stability of the accumulation process, and outputs the inverted fourth digital signal to control the on-off of the capacitor in the detection module. The accuracy and reliability of bandwidth calibration are improved, the control logic is simplified, and the flexibility and adaptability of the system are enhanced, thereby ensuring that the consistency and accuracy of the filter performance can be maintained under various conditions.

[0078] In an optional implementation of the embodiment of this specification, the control module further includes: a full adder and a data selector connected in series; The series half adder is further used to output the control signal to the first input terminal of the series full adder; The data selector is used to transmit the correction signal to the second input terminal of the series full adder in the case of correction mode; The series full adder is used to add the control signal and the correction signal to obtain the updated control signal, and output the updated control signal to the active filter.

[0079] After the control signal is output through the series half adder, it is necessary to detect the control signal. If the control signal does not match the target control signal, the control signal is corrected through the correction mode of the data selector to make the control signal meet the target requirements.

[0080] Among them, the calibration signal is a signal or data provided externally, which is used to accurately adjust or calibrate the system. In the embodiment of this specification, the calibration signal is a set of binary values ​​input externally, which is used to correct or optimize the control signal output by the control module, thereby improving the bandwidth calibration accuracy of the active filter. The calibration signal can be manually input, automatically generated by writing a calibration code, or obtained by analyzing historical data, and this specification does not make specific restrictions on this.

[0081] See also Figure 7 , Figure 7 FIG. 1 shows a circuit structure diagram of a control module in a bandwidth calibration circuit of an active filter provided by an optional embodiment of the present specification, including a series full adder and a data selector, as shown in FIG. Figure 7 As shown: The series full adder Full_adder receives the control signal input by the series half adder Half_adder through the input terminal B<5.0>; the data selector Seletor has a correction mode (0) and a non-correction mode (1). When the control signal manual_sel of the data selector Seletor is 1, the data selector is in the non-correction mode (1), and the control signal outputted from the output terminal S<5.0> of the series full adder Full_adder without correction is directly outputted as the final control signal rc_code<5.0> to the active filter; in the control signal of the data selector Seletor, the control signal outputted from the output terminal S<5.0> of the series full adder Full_adder without correction is directly outputted as the final control signal rc_code<5.0> to the active filter; in the control signal of the data selector Seletor, the control signal outputted from the output terminal S<5.0> of the series full adder Full_adder is When the control signal manual_sel=0, the data selector is in the correction mode (0), then the data selector Seletor inputs the correction signal manual_code<5.0> to the input terminal A<5.0> of the series full adder Full_adder, the series full adder Full_adder adds the correction signal manual_code<5.0> inputted at the input terminal A<5.0> and the control signal inputted at the input terminal B<5.0>, outputs the corrected control signal through the output terminal S<5.0>, and outputs it as the final control signal rc_code<5.0> to the active filter.

[0082] In the embodiments of the present specification, a series full adder and a data selector are introduced into the control module, so that in the non-calibration mode, the control signal is directly output to the active filter; in the calibration mode, the data selector transmits the calibration signal provided externally to the series full adder, and generates an updated control signal after adding it to the control signal, thereby enhancing the flexibility and accuracy of the bandwidth calibration circuit of the active filter, not only supporting real-time adjustment and optimization of the filter performance, but also being able to flexibly respond to the needs of different application scenarios, thereby improving the overall stability and reliability of the system.

[0083] Below, combined with the attached Figure 8 , further describes the bandwidth calibration circuit of the active filter provided in this manual. Figure 8 , Figure 8 FIG. 1 shows a circuit structure diagram of a bandwidth calibration circuit of an active filter provided by an embodiment of the present specification, such as Figure 8 As shown: The bandwidth calibration circuit includes: an amplifier OPA, a power supply VDD, transistors M1-M7, a resistor R, a capacitor array C_array, a comparator COMP, a trigger D FF , series half adder Half_adder, parallel trigger D FF <5.0>, a full adder Full_adder and a data selector Seletor are connected in series, wherein the connection relationship of each component or component has been described in the previous embodiments and will not be repeated here.

[0084] When the bandwidth calibration of the active filter begins, the reference voltage Vref is clamped to the non-ground end of the resistor R through the amplifier OPA to generate a target current I, and the target current I is mirrored to the first switch module (i.e., the source of the transistor M5) through the common source and common gate current mirror formed by the transistors M1-M4; then when the first switch signal CLK_1P is high, the second switch signal CLK_2P is low, and the third switch signal CLK_1N is low, the first switch module (transistor M5) is turned on, the second switch module (transistor M6) is turned off, and the third switch module (transistor M7) is turned off. At this time, the target current I will flow through the first switch module and flow into the capacitor array C_array for charging. After the first switch module is turned on for a time T, the capacitor voltage U is obtained. C ; Capacitor voltage U C The positive input of the comparator (COMP) is compared with the reference voltage Vref input at the negative phase terminal. C When the reference voltage Vref is less than the reference voltage Vref, the comparator (COMP) outputs a low-level drive signal (0) to the trigger D FF , trigger D FFThe reverse output terminal of the device outputs a first digital signal of high level (1) to the input terminal B of the series half adder Half_adder. The series half adder Half_adder adds 1 to the second digital signal 000000 to obtain a third digital signal 000001, and outputs the third digital signal 000001 to the parallel trigger D through the output terminal S<5.0>. FF <5.0> input terminal D; parallel trigger D FF <5.0> The fourth digital signal 111110 which is the inversion of the third digital signal is output through the reverse output terminal; when the first switch signal CLK_1P changes from a high level to a low level, and after 1 / 4 period T, the second switch signal CLK_2P changes from a low level (0) to a high level (1), all the charges stored on the capacitor array C_array are released to the ground terminal, so that the upper capacitor voltage U of the capacitor array is C is 0, and at the same time generates a rising edge signal and sends it to the parallel trigger D FF <5.0>, parallel trigger D FF <5.0> returns the third output signal 000001 to the input terminal A<5.0> of the series half adder Half_adder through the output terminal, so that the series half adder Half_adder starts to accumulate from the third digital signal 000001 when accumulating next time; at the same time, the capacitor array is adjusted through the fourth digital signal 111110, and the capacitor array is reduced by one unit capacitance value, so that the capacitor voltage U obtained next time C The value of is higher.

[0085] After several adjustments, the capacitor voltage U C = reference voltage Vref, the comparator (COMP) outputs a high-level drive signal (1) to the trigger D FF Since the comparator (COMP) output changes from 0 to 1 with a rising edge, the trigger D FF The first digital signal output from the reverse output terminal of is low level (0), the series half adder Half_adder will not add 1 to the second digital signal (that is, the third digital signal input last time), that is, the third digital signal currently output is the same as the third digital signal output last time, then the parallel flip-flop D FF The fourth digital signal outputted from <5:0> will not change either, that is, the control code code<5:0> (ie, the fourth digital signal 111110) of the capacitor array C_array will be locked.

[0086] in U C =Vref, the above formula (5) can be simplified to obtain formula (6), which represents the RC time constant T, and the bandwidth parameter is determined by the RC time constant T. Formula (6) is determined as: (6) Among them, the resistor R and the capacitor array C_array are both fixed values, and the time constant T can be obtained. In the active filter, the bandwidth can be expressed as a constant related to the time constant T. For example, the reciprocal of the time constant T, 1 / T, can be used to approximate it. Then, after each calibration, when the time constant T=R×C_array is a certain value, the bandwidth of the active filter is a certain value, that is, the bandwidth calibration of the active filter is completed.

[0087] After the control code (the fourth digital signal) of the capacitor array is locked, the parallel trigger D FF <5.0> outputs the fourth digital signal to the input terminal B<5.0> of the series full adder Full_adder through the output terminal; the data selector Seletor has a calibration mode (0) and a non-calibration mode (1). When the control signal manual_sel of the data selector Seletor is 1, the data selector is in the non-calibration mode (1), so the calibration signal manual_code<5.0> is 000000, that is, the fourth digital signal is not calibrated, and the control signal that does not need to be calibrated output from the output terminal S<5.0> of the series full adder Full_adder is directly output as the final control signal rc_code<5.0> to the active Filter; when the control signal manual_sel of the data selector Seletor is 0, the data selector is in the correction mode (0), then the data selector Seletor inputs the correction signal manual_code<5.0> to the input terminal A<5.0> of the series full adder Full_adder, the series full adder Full_adder adds the correction signal manual_code<5.0> inputted at the input terminal A<5.0> and the control signal inputted at the input terminal B<5.0>, outputs the corrected control signal through the output terminal S<5.0>, and outputs it as the final control signal rc_code<5.0> to the active filter.

[0088] The embodiments of this specification integrate components such as amplifiers, current mirrors, switch modules, comparators, triggers, half adders, full adders and data selectors. First, a stable target current is generated by amplifiers and current mirrors, and the charging process of the capacitor array is controlled by the switch module. The comparator monitors the comparison result between the capacitor voltage and the reference voltage to trigger subsequent digital signal processing. The state of the capacitor array is dynamically adjusted through the coordinated work of the trigger and the series half adder to ensure that the capacitor voltage is ultimately equal to the reference voltage, thereby locking the optimal capacitor configuration. The series full adder and data selector are introduced to support further fine-tuning of the control signal in the correction mode to meet the needs of different application scenarios, thereby achieving accurate automatic calibration and flexible adjustment of the active filter bandwidth, improving the accuracy and efficiency of bandwidth calibration, enhancing the flexibility and robustness of the system, and ensuring the performance stability and consistency of the filter under various conditions.

[0089] For the bandwidth calibration circuit corresponding to the above active filter, see Fig. 9 , Fig. 9 FIG. 4 shows a simulation waveform diagram of a bandwidth calibration circuit of an active filter provided by an optional embodiment of the present specification, such as Fig. 9 As shown: code <0> To code <5> represents the high and low level change value of each digit of the second switch signal, and comp_vip represents the input voltage of the same-direction input terminal of the comparator COMP (i.e., the capacitor voltage U C ), comp_out represents the signal output by the comparator COMP, CLK_1P represents the first switching signal, and CLK_2P represents the second switching signal.

[0090] During the period when the first switch signal CLK_1P is at a high level, the second switch signal CLK_2P is at a low level, and the comparator COMP output is at a low level (0), the capacitor array C_array is always in a charging state. At the same time, as the calibration process proceeds, the value C_array of the capacitor array continues to decrease over time; the voltage comp_vip at the non-inverting input terminal (+) of the comparator COMP is always increasing. When the capacitor array control signal decreases from 111111 to 110000, the comparator COMP outputs a high level signal. At this point, the code (i.e., the fourth digital signal) calibrated by the capacitor array is locked, and the fourth digital signal is transmitted to the capacitor array of the active filter as the final control signal, thereby completing the bandwidth calibration of the active filter.

[0091] The present specification also provides a bandwidth calibration method for an active filter, see Fig.10 , Fig.10A flow chart of a bandwidth calibration method for an active filter provided by an embodiment of the present specification is shown. The method is applied to a bandwidth calibration circuit of the active filter. The bandwidth calibration circuit includes a frequency divider, a detection module and a control module. The method includes: Step 1002: The frequency divider divides the input clock signal to generate at least two switch signals which are transmitted to the detection module.

[0092] Step 1004: The detection module detects whether the bandwidth parameter of the active filter reaches a preset parameter range in response to at least two switch signals, and sends a driving signal to the control module if not.

[0093] Step 1006: The control module calibrates the control signal based on the drive signal, and the control signal is used to control the on and off of the capacitor in the active filter.

[0094] The bandwidth calibration method of the active filter provided in the embodiments of this specification can be specifically executed by a bandwidth calibration circuit. The specific calibration process of performing bandwidth calibration on the active filter using the bandwidth calibration method of the active filter has been described in detail in the above embodiments, which will not be repeated here.

[0095] The bandwidth calibration method of the active filter provided in the embodiment of the present specification generates at least two switching signals through a frequency divider, uses a detection module to detect the bandwidth parameter of the active filter and compares it with a preset parameter range, and sends a driving signal to the control module if the bandwidth parameter is not reached. The control module generates a control signal based on the driving signal / calibrates the control signal. The calibrated control signal can stabilize the bandwidth parameter within the preset parameter range, which not only improves the calibration accuracy and efficiency and ensures that the active filter always operates within the optimal performance range, but also simplifies the calibration process, enhances the flexibility and reliability of the system, can be applied to a variety of application scenarios, and significantly improves the overall performance and stability of the active filter.

[0096] The present specification also provides a radio frequency device, see Fig.11 , Fig.11 A schematic diagram of the structure of a radio frequency device provided by an optional embodiment of the present specification is shown. Fig.11 As shown: The radio frequency device 1100 includes a bandwidth calibration circuit 1110 of an active filter and an active filter 1120 . The bandwidth calibration circuit 1110 of the active filter is used to send a control signal to the active filter 1120 ; the active filter 1120 is used to control the on / off of a capacitor based on the control signal.

[0097] The RF device provided in the embodiments of this specification realizes precise automatic control of the bandwidth of the active filter by integrating a bandwidth calibration circuit and an active filter. The bandwidth calibration circuit sends an optimized control signal to the active filter, dynamically adjusts the on-off state of the capacitor, and ensures that the active filter always operates within the optimal performance range, thereby improving the accuracy and stability of RF signal processing, enhancing the flexibility and adaptability of the system, and being applicable to a variety of working environments and application scenarios, significantly improving the overall performance and reliability of the RF device.

[0098] The embodiment of this specification also provides a communication device, the communication device includes: Fig.11 The radio frequency device shown, the communication device may be a modem, a router, a mobile phone, a personal computer, etc. Since the communication device is equipped with the radio frequency device, the bandwidth calibration of the active filter can be realized.

[0099] In the description of the present invention, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In the present invention, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0100] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance. In this article, "equal", "same" and the like are not strict mathematical and / or geometric limitations, but also include errors that can be understood by those skilled in the art and are allowed in manufacturing or use.

[0101] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0102] Unless otherwise stated, the numerical ranges herein include not only the entire range within its two endpoints but also include several sub-ranges contained therein.

[0103] The preferred specific implementation modes and embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above implementation modes and embodiments, and various changes can be made within the knowledge scope of those skilled in the art without departing from the concept of the present application.

[0104] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The optional embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of the present invention. The present invention selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A bandwidth calibration circuit for an active filter, characterized in that: include: A frequency divider, a detection module and a control module; wherein, The frequency divider is used to divide the input clock signal to generate at least two switch signals and transmit them to the detection module; The detection module is used to detect whether the bandwidth parameter of the active filter reaches a preset parameter range in response to the at least two switch signals, and if not, send a driving signal to the control module; The control module is used to calibrate a control signal based on the drive signal, and the control signal is used to control the on and off of a capacitor in the active filter.

2. The bandwidth calibration circuit of the active filter according to claim 1, characterized in that: Also includes: Bandgap reference module; the bandgap reference module is used to provide a reference voltage to the detection module.

3. The bandwidth calibration circuit of the active filter according to claim 2, characterized in that: The at least two switching signals include a first switching signal and a second switching signal having different duty cycles; The detection module includes: a first switch module, a second switch module, a bandwidth element and a comparator, wherein the bandwidth element includes a resistor and capacitor array arranged based on the active filter; The resistor and the capacitor array are grounded; the reference voltage is connected to the non-ground end of the resistor to generate a target current; the target current flows into the first end of the first switch module, and the second end of the first switch module is connected to the non-ground end of the capacitor array; the second switch module is connected to the two ends of the capacitor array; the first end of the comparator is connected to the non-ground end of the capacitor array, and the second end is input with the reference voltage; The first switch module is used for responding to the first switch signal and, when closed, flowing the target current into the capacitor array to charge the capacitor and generate a capacitor voltage; The second switch module is used for discharging the capacitor array in response to the second switch signal when the first switch module is disconnected and the second switch module is closed; The comparator is used to compare the capacitor voltage with the reference voltage, and output a driving signal to the control module based on the comparison result.

4. The bandwidth calibration circuit of the active filter according to claim 3, characterized in that: The comparator is specifically used to output a low-level driving signal to the control module when the capacitor voltage is less than the reference voltage; and to output a high-level driving signal to the control module when the capacitor voltage is equal to the reference voltage.

5. The bandwidth calibration circuit of the active filter according to claim 3, characterized in that: The detection module further includes: an amplifier; the amplifier is used to clamp the reference voltage to the non-ground end of the resistor to generate a target current.

6. The bandwidth calibration circuit of the active filter according to claim 3, characterized in that: The detection module further includes: a current mirror module; the current mirror module is used to mirror the target current to the first end of the first switch module.

7. The bandwidth calibration circuit of the active filter according to claim 3, characterized in that: The at least two switch signals further include a third switch signal which is opposite to the first switch signal; the detection module further includes: a third switch module; a first end of the third switch module is connected to a first end of the first switch module, and a second end of the third switch module is grounded; The third switch module is used to close or open in response to the third switch signal.

8. The bandwidth calibration circuit of the active filter according to any one of claims 1 to 7, characterized in that: The control module includes: a trigger and a series half adder; The trigger is used for outputting a first digital signal opposite to the driving signal to the series half adder in response to the driving signal; The series half adder is used to add 1 to the binary second digital signal when the first digital signal is at a high level, wherein the number of bits of the second digital signal is the same as the number of controllable capacitors in the active filter and are initially 0; and when the first digital signal is at a low level, the second digital signal is inverted and output as a control signal to the active filter.

9. The bandwidth calibration circuit of the active filter according to claim 8, characterized in that: The control module further includes: a parallel trigger; The serial half adder is specifically used to add 1 to the second binary digital signal to obtain a third digital signal, and output it to the parallel trigger; The first output terminal of the parallel trigger outputs the third digital signal to the series half adder, so that the series half adder starts accumulating from the third digital signal next time; The second output end of the parallel trigger outputs a fourth digital signal obtained by inverting the third digital signal, and the fourth digital signal is used to control the on and off of the capacitor in the detection module, and the capacitor in the detection module is set based on the active filter.

10. The bandwidth calibration circuit of the active filter according to claim 8, characterized in that: The control module further comprises: a series-connected full adder and a data selector; The series half adder is further used to output the control signal to the first input terminal of the series full adder; The data selector is used to transmit the correction signal to the second input terminal of the series full adder in the case of correction mode; The series full adder is used to add the control signal and the correction signal to obtain the updated control signal, and output the updated control signal to the active filter.

11. A bandwidth calibration method for an active filter, characterized in that: A bandwidth calibration circuit applied to an active filter, the bandwidth calibration circuit comprising a frequency divider, a detection module and a control module; the method comprising: The frequency divider divides the input clock signal to generate at least two switch signals for transmission to the detection module; The detection module detects whether the bandwidth parameter of the active filter reaches a preset parameter range in response to the at least two switch signals, and sends a driving signal to the control module if not; The control module calibrates a control signal based on the drive signal, and the control signal is used to control the on and off of a capacitor in the active filter.

12. A radio frequency device, characterized in that: The invention comprises a bandwidth calibration circuit and an active filter of the active filter as described in any one of claims 1 to 10; the bandwidth calibration circuit is used to send the control signal to the active filter; the active filter is used to control the on-off of the capacitor based on the control signal.

13. A communication device, characterized in that: Comprising the radio frequency device as claimed in claim 12.

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