Automatic two-way transmission and level conversion buffer circuit applied to Flash chip

Abstract

The invention discloses an automatic two-way transmission and level conversion buffer circuit applied to a Flash chip. The automatic two-way transmission and level conversion buffer circuit comprises an LDO (Low Dropout Regulator) circuit, a direction control buffer circuit and an automatic direction buffer circuit, the input end of the LDO circuit inputs a VIN signal and an EN enable signal respectively, and the LDO circuit provides voltage for other chips or internal circuits according to the VIN signal and the EN enable signal; an EN enable signal and a DIR selection signal are input into the control end of the buffer circuit for controlling the direction, and switching and switching of forward transmission and reverse transmission of signals input into the buffer circuit for controlling the direction are controlled through the EN enable signal and the DIR selection signal. An EN enable signal is input into the control end of the automatic direction buffer circuit, and level conversion of two input ports of the automatic direction buffer circuit is controlled through the EN enable signal; compatibility of the Flash chip to different SPI protocols and different voltage domains are met, interference of power supply noise to an internal chip is effectively restrained, and control over the transmission direction of transmission signals is achieved.

Description

Technical Field

[0001] The invention relates to the field of integrated circuit design, and in particular to a buffer circuit for automatic bidirectional transmission and level conversion applied to a Flash chip. Background Art

[0002] In Flash chips, the peripheral buffer circuit is an important circuit functional module. The buffer circuit can not only enhance signal integrity, enhance driving capability, reduce the number of loads, and reduce the connection load, but also realize functions such as clock signal replication, format conversion, and level conversion. The common Flash buffer circuit implementation method mainly adopts a two-stage inverter architecture to achieve functions such as enhanced driving circuit capability and level conversion. However, this design scheme can only be used for traditional serial peripheral interface devices SPI, and cannot simultaneously meet the needs of two-bit serial peripheral interface devices DSPI and four-bit serial peripheral interface devices QSPI. At the same time, for high-precision chips, power supply noise will cause great interference to them, and even affect the normal operation of the circuit.

[0003] Traditional Flash peripheral chip structure such as Figure 7 As shown, there are only a number of unidirectional buffers, which can meet the execution of the SPI protocol and convert the high-voltage signal to a low-voltage signal. However, the new Flash chips on the market not only support the SPI protocol, but also support the QSPI and DSPI protocols, where QSPI and DSPI have 2 and 4 bidirectional transmission ports respectively, so the traditional unidirectional buffer is not enough to meet the existing needs. In addition, since the traditional buffer has no means to suppress power supply noise, when the external voltage fluctuates, it will cause signal transmission errors, which will cause the Flash chip to fail to work properly. Summary of the invention

[0004] Purpose of the invention: In order to overcome the deficiencies in the prior art, the present invention provides a buffer circuit for automatic bidirectional transmission and level conversion applied to a Flash chip, enhances the anti-noise capability of the buffer circuit, and realizes the level conversion function and automatic bidirectional transmission function of the buffer circuit.

[0005] Technical solution: To achieve the above-mentioned purpose, the present invention provides a buffer circuit for automatic bidirectional transmission and level conversion applied to a Flash chip, comprising an LDO circuit, a buffer circuit for controlling direction and a buffer circuit for automatic direction; the input end of the LDO circuit inputs a VIN signal and an EN enable signal respectively, and the LDO circuit provides voltage for the buffer circuit for controlling direction, the buffer circuit for automatic direction and the Flash chip according to the VIN signal and the EN enable signal; the control end of the buffer circuit for controlling direction inputs an EN enable signal and a DIR selection signal, and controls the switching of the forward transmission and reverse transmission of the signal in the buffer circuit for controlling direction and the switch through the EN enable signal and the DIR selection signal; the control end of the buffer circuit for automatic direction inputs an EN enable signal, and controls the level conversion of the two input ports of the buffer circuit for automatic direction through the EN enable signal.

[0006] Furthermore, the LDO circuit includes an error amplifier and an M1 power tube; the negative input terminal of the error amplifier is electrically connected to the output terminal of the voltage reference circuit, and the input terminal of the voltage reference circuit inputs a VIN signal; the output terminal of the error amplifier is electrically connected to the gate of the M1 power tube, the source of the M1 power tube inputs the VIN signal, the drain of the M1 power tube is electrically connected to one end of the R2 resistor, and the other end of the R2 resistor is electrically connected to the positive input terminal of the error amplifier and one end of the R1 resistor; the drain of the M1 power tube is the output terminal of the LDO circuit.

[0007] Furthermore, the buffer circuit for controlling the direction includes a Logic module circuit, a first LVST circuit, a first unidirectional buffer and a second unidirectional buffer; the input end of the Logic module circuit serves as the control end of the buffer module for controlling the direction, the two output ends of the Logic module circuit are electrically connected to the first unidirectional buffer and the second unidirectional buffer control end respectively, and the output end of the second unidirectional buffer is electrically connected to the input end of the first LVST circuit.

[0008] Furthermore, during forward transmission, the input end of the first unidirectional buffer is the input end of the buffer circuit that controls the direction, and the output end of the first unidirectional buffer is the output end of the buffer circuit that controls the direction; during reverse transmission, the input end of the second unidirectional buffer is the input end of the buffer circuit that controls the direction, and the output end of the first LVST circuit is the output end of the buffer circuit that controls the direction.

[0009] Furthermore, the Logic module circuit includes a first inverter, a first NAND gate circuit and a second NAND gate circuit; an EN enable signal is input to the input end of the first inverter, the output end of the first inverter is electrically connected to an input end of the first NAND gate circuit, the other input end of the first NAND gate circuit is input to the DIR selection signal, and the output end of the first NAND gate circuit is electrically connected to the control end of the second unidirectional buffer; an EN enable signal is input to one input end of the second NAND gate circuit, the other input end of the second NAND gate circuit is input to the DIR selection signal, and the output end of the second NAND gate circuit is electrically connected to the control end of the first unidirectional buffer.

[0010] Furthermore, the automatic direction buffer circuit includes a first accelerator module circuit, a second accelerator module circuit, a switch control module circuit and a second LVST circuit; an EN enable signal is input to the input end of the first accelerator module circuit, the input end of the switch control module circuit and the input end of the second LVST circuit; the output end of the second LVST circuit is electrically connected to the input end of the second accelerator module circuit; the power supply end of the first accelerator module circuit is electrically connected to the output end of the first accelerator module circuit through the R3 resistor, and the power supply end of the second accelerator module circuit is electrically connected to the output end of the second accelerator module circuit through the R4 resistor; the output end of the switch control module circuit is electrically connected to the gate of the M2 transistor, the source of the M2 transistor is electrically connected to the output end of the first accelerator module circuit, and the drain of the M2 transistor is electrically connected to the output end of the second accelerator module circuit.

[0011] Furthermore, the first LVST circuit and the second LVST circuit are both LVST level conversion circuits; the LVST level conversion circuit includes an MP1 transistor, an MP2 transistor, an MN1 transistor and an MN2 transistor; the drain of the MP1 transistor is electrically connected to the drain of the MN1 transistor and the gate of the MP2 transistor, and the drain of the MP2 transistor is electrically connected to the drain of the MN2 transistor and the gate of the MP1 transistor; the gate of the MN1 transistor is the input end of the LVST level conversion circuit, and the drain of the MP2 transistor is the output end of the LVST level conversion circuit.

[0012] Furthermore, the first accelerator module circuit and the second accelerator module circuit are both one-time self-acceleration module circuits, and the one-time self-acceleration module circuit includes a second inverter, an MP3 transistor and an MN3 transistor; the input end of the second inverter serves as the input end of the one-time acceleration module circuit, the output end of the second inverter is electrically connected to one end plate of the C1 capacitor, an input end of the third NAND gate circuit and an input end of the NOR gate circuit through the R5 resistor, and the other input end of the third NAND gate circuit and the other input end of the NOR gate circuit are both electrically connected to the input end of the second inverter; the output end of the third NAND gate circuit is electrically connected to the gate of the MP3 transistor, and the output end of the NOR gate circuit is electrically connected to the gate of the MN3 transistor; the drain of the MP3 transistor is electrically connected to the drain of the MN3 transistor, and serves as the output end of the one-time self-acceleration module circuit.

[0013] Beneficial effects: The present invention is a buffer circuit for automatic bidirectional transmission and level conversion applied to Flash chips. An LDO circuit is added to the buffer of the Flash chip, which can effectively suppress power supply noise and avoid the Flash chip from not being able to be used normally due to excessive power supply noise; an LDO low-voltage difference linear regulator is used to generate a stable level for use by internal modules and Flash chips, thereby enhancing the circuit's anti-noise ability. The bidirectional level conversion technology is used to meet the Flash chip's compatibility with different SPI protocols and different voltage domains; the interference of power supply noise on internal chips is effectively suppressed, and the compatibility and voltage conversion problems between different SPIs are achieved. The SPI 4-bit transmission line uses an automatic direction transmission and a buffer with a level conversion function, which can automatically detect the source of the input signal, thereby determining the transmission direction and realizing level conversion; the disposable self-accelerator module and the direction control circuit have a simple structure and consume less current, which is in line with low-power application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A buffer circuit diagram for automatic bidirectional transmission and level conversion applied to Flash chips;

[0015] Figure 2 This is the LDO circuit diagram;

[0016] Figure 3 A circuit diagram of a buffer for controlling direction;

[0017] Figure 4 The circuit diagram of the buffer for automatic direction;

[0018] Figure 5 It is a LVST level conversion circuit;

[0019] Figure 6 It is a one-time self-acceleration module circuit;

[0020] Figure 7 This is the circuit diagram of a traditional Flash chip unidirectional buffer. DETAILED DESCRIPTION

[0021] The present invention will be further described below in conjunction with the accompanying drawings.

[0022] like Figure 1 As shown, a buffer circuit for automatic bidirectional transmission and level conversion applied to a Flash chip comprises an LDO circuit 1, a buffer circuit for controlling direction 2 and a buffer circuit for automatic direction 3; the input end of the LDO circuit 1 inputs a VIN signal and an EN enable signal respectively, and the LDO circuit 1 provides voltages for the buffer circuit for controlling direction 2, the buffer circuit for automatic direction 3 and the Flash chip according to the VIN signal and the EN enable signal, thereby enhancing the circuit's anti-noise capability; the control end of the buffer circuit for controlling direction 2 inputs an EN enable signal and a DIR selection signal, and the input end of the buffer circuit for controlling direction 2 inputs a CK clock signal and a CS enable signal, and the switching of the forward transmission and reverse transmission of the signal in the buffer circuit for controlling direction 2 is controlled by the EN enable signal and the DIR selection signal; the driving capability of the signal is enhanced by using the buffer circuit for controlling direction for the CK clock signal and the CS enable signal of the Flash chip; and the transmission direction of the signal can be changed to realize the function of bidirectional transmission of the signal. The control end of the automatic direction buffer circuit 3 inputs an EN enable signal, and the input end of the automatic direction buffer circuit 3 inputs a VIN signal, that is, an input VCCA voltage signal and a VCCB voltage signal. The level conversion of the two input ports of the automatic direction buffer circuit 3 is controlled by the EN enable signal.

[0023] like Figure 2 As shown, the LDO circuit 1 includes an error amplifier 12 and an M1 power tube 13; the negative input terminal of the error amplifier 12 is electrically connected to the output terminal of the voltage reference circuit 11, and the input terminal of the voltage reference circuit 11 inputs a VIN signal; the output terminal of the error amplifier 12 is electrically connected to the gate of the M1 power tube 13, the source of the M1 power tube 13 inputs a VIN signal, the drain of the M1 power tube 13 is electrically connected to one end of the R2 resistor, the other end of the R2 resistor is electrically connected to the positive input terminal of the error amplifier 12 and one end of the R1 resistor, and the other end of the R1 resistor is grounded; the drain of the M1 power tube 13 is the output terminal of the LDO circuit 1; the M1 power tube 13 is a PMOS tube.

[0024] The R1 resistor and the R2 resistor form a feedback network, and the feedback network, the error amplifier 12 and the M1 power tube 13 form a negative feedback loop, so that the feedback voltage VFB at the positive input end of the error amplifier 12 and the reference voltage VREF output by the voltage reference circuit 11 connected to the negative input end of the error amplifier 12 are equal; finally, the VOUT voltage outputted from the output end of the LDO circuit 1 is determined by the resistance voltage division of the R2 resistor and the R1 resistor in the feedback resistor network; the VOUT voltage generated by the core LDO circuit 1 will be used as a power supply to power other chips, and power the control direction buffer circuit 2, the automatic direction buffer circuit 3 and the Flash chip.

[0025] like Figure 3 As shown, the buffer circuit 2 for controlling the direction includes a Logic module circuit 21, a first LVST circuit 22, a first unidirectional buffer 23 and a second unidirectional buffer 24; the input end of the Logic module circuit 21 serves as the control end of the buffer module 2 for controlling the direction, and the two output ends of the Logic module circuit 21 are electrically connected to the control ends of the first unidirectional buffer 23 and the second unidirectional buffer 24 respectively, and the output end of the second unidirectional buffer 24 is electrically connected to the input end of the first LVST circuit 22.

[0026] The logic module circuit 21 uses two NAND gates and an inverter to combine the selection signal DIR and the enable signal EN to control the buffer switch and the transmission direction respectively; since the input signal is a high level, an LVST circuit is added to the reverse transmission path to ensure that the Flash chip can accurately transmit the signal. When transmitting in the forward direction, the input end of the first unidirectional buffer 23 is the input end of the buffer circuit 2 that controls the direction, and the output end of the first unidirectional buffer 23 is the output end of the buffer circuit 2 that controls the direction; the input end of the first unidirectional buffer 23 inputs the IN signal, and then the output end of the first unidirectional buffer 23 outputs it to the Flash chip.

[0027] During reverse transmission, the input end of the second unidirectional buffer 24 is the input end of the buffer circuit 2 for controlling the direction, and the output end of the first LVST circuit 22 is the output end of the buffer circuit 2 for controlling the direction; the input end of the second unidirectional buffer 24 inputs the signal output by the Flash chip, and then outputs it by the output end of the first LVST circuit 22.

[0028] like Figure 3As shown, the logic module circuit 21 includes a first inverter 25, a first NAND gate circuit 26 and a second NAND gate circuit 27; the input end of the first inverter 25 inputs the EN enable signal, the output end of the first inverter 25 is electrically connected to one input end of the first NAND gate circuit 26, the other input end of the first NAND gate circuit 26 inputs the DIR selection signal, and the output end of the first NAND gate circuit 26 is electrically connected to the control end of the second unidirectional buffer 24; the input end of the second NAND gate circuit 27 inputs the EN enable signal, the other input end of the second NAND gate circuit 27 inputs the DIR selection signal, and the output end of the second NAND gate circuit 27 is electrically connected to the control end of the first unidirectional buffer 23. The switching of the forward transmission and reverse transmission of the signal in the buffer circuit 2 controlling the input control direction is realized by the inversion of the DIR selection signal and the EN enable signal through the inverter and the logical combination of the NAND gate.

[0029] like Figure 5 As shown, in order to meet the requirements of DSPI and QSPI, an automatic direction buffer circuit 3 is added; the automatic direction buffer circuit 3 includes a first accelerator module circuit 31, a second accelerator module circuit 32, a switch control module circuit 33 and a second LVST circuit 34; the input end of the first accelerator module circuit 31, the input end of the switch control module circuit 33, and the input end of the second LVST circuit 34 input an EN enable signal; the output end of the second LVST circuit 34 is electrically connected to the input end of the second accelerator module circuit 32; the power supply end of the first accelerator module circuit 31 is electrically connected to the output end of the first accelerator module circuit 31 through the R3 resistor, and the power supply end of the second accelerator module circuit 32 is electrically connected to the output end of the second accelerator module circuit 32 through the R4 resistor; the output end of the switch control module circuit 33 is electrically connected to the gate of the M2 transistor 35, the source of the M2 transistor 35 is electrically connected to the output end of the first accelerator module circuit 31, and the drain of the M2 transistor 35 is electrically connected to the output end of the second accelerator module circuit 32. The source and drain of the M2 transistor can be used as I / O ports to connect other chips, that is, two input ports of the automatic direction buffer circuit 3. The M2 transistor 35 is an NMOS tube, the R3 resistor and the R4 resistor are normally pulled up resistors, the source of the M2 transistor is electrically connected to the VCCA power supply through the R3 resistor, and the drain of the M2 transistor is electrically connected to the VCCB power supply through the R4 resistor.

[0030] The input end of the first accelerator module circuit 31, the input end of the switch control module circuit 33 and the input end of the second LVST circuit 34 input the EN enable signal; the power supply end of the first accelerator module circuit 31 is electrically connected to the VCCA power supply, and the VCCA voltage signal is input; the power supply end of the second accelerator module circuit 32 is electrically connected to the VCCB power supply, and the VCCB voltage signal is input; due to the difference in potential between the VCCA voltage signal and the VCCB voltage signal, the second LVST circuit 34 is added to convert the EN enable signal into a VCCB voltage signal, and then input into the second accelerator module circuit 32, thereby preventing circuit leakage. Both of the two one-time self-acceleration module circuits can detect the change in potential of the two input ports I / O ports respectively, and can automatically detect the source of the input signal, thereby determining the transmission direction and realizing level conversion; when performing level conversion, the input port potential is transiently and quickly pulled up or down, thereby realizing rapid level conversion. When the level of one input port changes, the one-time self-acceleration module circuit generates a high potential or a low potential to control the pull-up and pull-down MOS transistors of the other input port, namely the pull-up and pull-down M2 transistors 55; thereby completing the level conversion operation of the two input ports.

[0031] like Figure 4 As shown, the first LVST circuit 22 and the second LVST circuit 34 are both LVST level conversion circuits; the LVST level conversion circuit includes an MP1 transistor 41, an MP2 transistor 42, an MN1 transistor 43 and an MN2 transistor 44; the drain of the MP1 transistor 41 is electrically connected to the drain of the MN1 transistor 43 and the gate of the MP2 transistor 42, and the drain of the MP2 transistor 42 is electrically connected to the drain of the MN2 transistor 44 and the gate of the MP1 transistor 41; the gate of the MN1 transistor 43 is the input end of the LVST level conversion circuit, and the drain of the MP2 transistor 42 is the output end of the LVST level conversion circuit. The sources of the MP1 transistor 41 and the MP2 transistor 42 are both electrically connected to the VCC power supply; the sources of the MN1 transistor 43 and the MN2 transistor 44 are both grounded, wherein the gate of the MN1 transistor 43 is the input end of the LVST level conversion circuit to input the IN signal, and the gate of the MN2 transistor 44 is the input of the signal INN signal obtained by inverting the IN signal. The MN1 transistor and the MN2 transistor are level conversion input pairs, and the MP1 transistor and the MP2 transistor are load transistors, which are cross-connected to form positive feedback to ensure the normal operation of the circuit. The IN signal of the first LVST circuit 22 is the signal output by the second unidirectional buffer, and the IN signal of the second LVST circuit 34 is the EN enable signal.

[0032] like Figure 6As shown, the first accelerator module circuit 31 and the second accelerator module circuit 32 are both one-time self-acceleration module circuits, and the one-time self-acceleration module circuit includes a second inverter 51, an MP3 transistor 52 and an MN3 transistor 53; the input end of the second inverter 51 serves as the input end of the one-time acceleration module circuit, and the output end of the second inverter 51 is electrically connected to one end of the plate of the C1 capacitor, one input end of the third NAND gate circuit 54 and one input end of the NOR gate circuit 55 through the R5 resistor, the other input end of the third NAND gate circuit 54 and the other input end of the NOR gate circuit 55 are both electrically connected to the input end of the second inverter 51, and the other end of the plate of the C1 capacitor is grounded; the output end of the third NAND gate circuit 54 is electrically connected to the gate of the MP3 transistor 52, and the output end of the NOR gate circuit 55 is electrically connected to the gate of the MN3 transistor 53; the drain of the MP3 transistor 52 is electrically connected to the drain of the MN3 transistor 53, and serves as the output end of the one-time self-acceleration module circuit.

[0033] The source of the MP3 transistor in the first accelerator module circuit 1 is electrically connected to the VCCA power supply, and the source of the MP3 transistor in the second accelerator module circuit 2 is electrically connected to the VCCB power supply; the source of the MN3 transistor 53 is grounded. The R5 resistor and the C1 capacitor form an RC network. The input end of the one-time self-acceleration module circuit inputs the IN signal, and after the inverter and the RC network delay, the IN1 signal is generated, and the IN1 signal and the original IN signal are combined with the AND and NOR logic combinations, and then the MP3 transistor 52 and the MN3 transistor 53 are respectively controlled to be turned on briefly, and the output signal is output to achieve the effect of pulling up or pulling down the two ports.

[0034] The above is only a description of the preferred embodiments of the present invention. Ordinary technicians in this technical field can make several modifications and optimizations based on the above disclosure without departing from the above basic principles. These improvements and optimizations should be regarded as the understood protection scope of the present invention.

Claims

1. A buffer circuit for automatic bidirectional transmission and level conversion applied to a Flash chip, characterized in that: The invention comprises an LDO circuit (1), a direction-controlling buffer circuit (2) and an automatic direction-controlling buffer circuit (3); the input end of the LDO circuit (1) respectively inputs a VIN signal and an EN enable signal, and the LDO circuit (1) provides voltages for the direction-controlling buffer circuit (2), the automatic direction-controlling buffer circuit (3) and a Flash chip according to the VIN signal and the EN enable signal; the control end of the direction-controlling buffer circuit (2) inputs an EN enable signal and a DIR selection signal, and controls the switching of the forward transmission and reverse transmission of the signal in the direction-controlling buffer circuit (2) and the switch through the EN enable signal and the DIR selection signal; the control end of the automatic direction-controlling buffer circuit (3) inputs an EN enable signal, and controls the level conversion of the two input ports of the automatic direction-controlling buffer circuit (3) through the EN enable signal.

2. The buffer circuit for automatic bidirectional transmission and level conversion applied to a Flash chip according to claim 1, characterized in that: The LDO circuit (1) comprises an error amplifier (12) and an M1 power tube (13); the negative input end of the error amplifier (12) is electrically connected to the output end of the voltage reference circuit (11), and the input end of the voltage reference circuit (11) inputs a VIN signal; the output end of the error amplifier (12) is electrically connected to the gate of the M1 power tube (13), the source of the M1 power tube (13) inputs the VIN signal, the drain of the M1 power tube (13) is electrically connected to one end of a resistor R2, and the other end of the resistor R2 is electrically connected to the positive input end of the error amplifier (12) and one end of the resistor R1; the drain of the M1 power tube (13) is the output end of the LDO circuit (1).

3. The buffer circuit for automatic bidirectional transmission and level conversion applied to a Flash chip according to claim 1, characterized in that: The buffer circuit (2) for controlling the direction comprises a logic module circuit (21), a first LVST circuit (22), a first unidirectional buffer (23) and a second unidirectional buffer (24); the input end of the logic module circuit (21) serves as the control end of the buffer module (2) for controlling the direction, the two output ends of the logic module circuit (21) are respectively electrically connected to the control ends of the first unidirectional buffer (23) and the second unidirectional buffer (24), and the output end of the second unidirectional buffer (24) is electrically connected to the input end of the first LVST circuit (22).

4. The buffer circuit for automatic bidirectional transmission and level conversion applied to a Flash chip according to claim 3, characterized in that: During forward transmission, the input end of the first unidirectional buffer (23) is the input end of the buffer circuit (2) for controlling the direction, and the output end of the first unidirectional buffer (23) is the output end of the buffer circuit (2) for controlling the direction; during reverse transmission, the input end of the second unidirectional buffer (24) is the input end of the buffer circuit (2) for controlling the direction, and the output end of the first LVST circuit (22) is the output end of the buffer circuit (2) for controlling the direction.

5. The buffer circuit for automatic bidirectional transmission and level conversion applied to a Flash chip according to claim 3, characterized in that: The logic module circuit (21) comprises a first inverter (25), a first NAND gate circuit (26) and a second NAND gate circuit (27); an EN enable signal is input to an input end of the first inverter (25), an output end of the first inverter (25) is electrically connected to an input end of the first NAND gate circuit (26), a DIR selection signal is input to another input end of the first NAND gate circuit (26), and an output end of the first NAND gate circuit (26) is electrically connected to a control end of a second unidirectional buffer (24); an EN enable signal is input to an input end of the second NAND gate circuit (27), a DIR selection signal is input to another input end of the second NAND gate circuit (27), and an output end of the second NAND gate circuit (27) is electrically connected to a control end of the first unidirectional buffer (23).

6. The buffer circuit for automatic bidirectional transmission and level conversion applied to a Flash chip according to claim 1, characterized in that: The automatic direction buffer circuit (3) comprises a first accelerator module circuit (31), a second accelerator module circuit (32), a switch control module circuit (33) and a second LVST circuit (34); an EN enable signal is input to the input end of the first accelerator module circuit (31), the input end of the switch control module circuit (33) and the input end of the second LVST circuit (34); the output end of the second LVST circuit (34) is electrically connected to the input end of the second accelerator module circuit (32); the power supply end of the first accelerator module circuit (31) is electrically connected to the output end of the first accelerator module circuit (31) through the R3 resistor, and the power supply end of the second accelerator module circuit (32) is electrically connected to the output end of the second accelerator module circuit (32) through the R4 resistor; the output end of the switch control module circuit (33) is electrically connected to the gate of the M2 transistor (35), the source of the M2 transistor (35) is electrically connected to the output end of the first accelerator module circuit (31), and the drain of the M2 transistor (35) is electrically connected to the output end of the second accelerator module circuit (32).

7. The buffer circuit for automatic bidirectional transmission and level conversion applied to a Flash chip according to claim 6, characterized in that: The first LVST circuit (22) and the second LVST circuit (34) are both LVST level conversion circuits; the LVST level conversion circuit comprises an MP1 transistor (41), an MP2 transistor (42), an MN1 transistor (43) and an MN2 transistor (44); the drain of the MP1 transistor (41) is electrically connected to the drain of the MN1 transistor (43) and the gate of the MP2 transistor (42), and the drain of the MP2 transistor (42) is electrically connected to the drain of the MN2 transistor (44) and the gate of the MP1 transistor (41); the gate of the MN1 transistor (43) is the input end of the LVST level conversion circuit, and the drain of the MP2 transistor (42) is the output end of the LVST level conversion circuit.

8. The buffer circuit for automatic bidirectional transmission and level conversion applied to a Flash chip according to claim 6, characterized in that: The first accelerator module circuit (31) and the second accelerator module circuit (32) are both one-time self-acceleration module circuits, and the one-time self-acceleration module circuit comprises a second inverter (51), an MP3 transistor (52) and an MN3 transistor (53); the input end of the second inverter (51) serves as the input end of the one-time acceleration module circuit, and the output end of the second inverter (51) is electrically connected to one end of the plate of the C1 capacitor, an input end of the third NAND gate circuit (54) and the NOR gate circuit ( 55), another input end of the third NAND gate circuit (54) and another input end of the NOR gate circuit (55) are all electrically connected to the input end of the second inverter (51); the output end of the third NAND gate circuit (54) is electrically connected to the gate of the MP3 transistor (52), and the output end of the NOR gate circuit (55) is electrically connected to the gate of the MN3 transistor (53); the drain of the MP3 transistor (52) is electrically connected to the drain of the MN3 transistor (53) and serves as the output end of the one-time self-acceleration module circuit.

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