Clock frequency detection method

Abstract

The invention discloses a clock frequency detection method, which comprises the following steps of: 1, preparing frequency detection, 11, determining the digit of a frequency division counter according to the frequency of a clock signal to be detected and the frequency of a working clock, the frequency of the clock signal after frequency division is required to be 1 / 2, 1 / 4 or 1 / 2 of other smaller even number of the frequency of the working clock; step 12, beating two beats on the rising edge of the work clock of the clock signal after frequency division to obtain a new frequency division signal; 2, calculating a counting threshold value of the zero clearing counter, and setting a counting value of the zero clearing counter according to the counting threshold value; 3, starting a detection counter to count; and step 4, detecting whether the new frequency division signal obtained in the step 1 loses frequency or not. According to the method provided by the invention, whether a clock signal with a certain frequency exists or not can be accurately detected under the condition of not using instruments and meters.

Description

Technical Field

[0001] The present invention belongs to the field of time-frequency technology detection, and specifically relates to a clock frequency detection method. The method detects the presence or absence of a frequency signal by cleverly using a counter without using any instrument. Background Art

[0002] In the field of time-frequency, it is often necessary to detect the frequency of a certain signal or clock. For example, when switching the frequency signal, it is necessary to first detect whether the signal frequency exists. Only when the frequency signal exists can the switch be performed, otherwise the switch is meaningless. The invention patent application with application number CN202310491493.2 describes a method for calculating the precise value of the frequency by serial-to-parallel conversion. Although this method can accurately calculate the frequency value, it is often necessary to select the reference source in the field of time-frequency technology. The accuracy of the reference source system at this time is very high, and no accurate calculation is required. The work of this system is to determine whether the reference source exists, and no complex frequency accuracy calculation is required. In fact, the frequency is detected by direct calculation and indirect calculation respectively, and the methods and difficulty of the two are completely different. On the other hand, many frequency measurements in the field of time-frequency are based on high-end instruments (such as spectrum analyzers and frequency meters). The higher the measurement accuracy, the higher the instrument accuracy requirements. In the prior art, high-end instruments are used to measure the frequency of the signal. Although intuitive results can be obtained, the cost is very high, and in the absence of high-end instruments, the measurement of the signal frequency cannot be achieved. Summary of the invention

[0003] The purpose of the present invention is to provide a frequency detection method to detect whether a clock signal of a certain frequency exists without using instruments.

[0004] In order to achieve the above object, the present invention adopts the following technical solution:

[0005] The present invention provides a clock frequency detection method, which specifically comprises the following steps:

[0006] Step 1, prepare for frequency detection, including the following sub-steps:

[0007] Step 11, determining the number of bits of the frequency division counter according to the frequency of the clock signal to be measured and the working clock frequency, requiring that the frequency of the divided clock signal is one-half, one-quarter or other smaller even-numbered fraction of the working clock frequency;

[0008] Step 12, beat the divided clock signal twice on the rising edge of the working clock to obtain a new divided clock signal;

[0009] Step 2, calculating a count threshold of the clear counter, and setting the count value of the clear counter according to the count threshold;

[0010] Step 3, starting the detection counter counting, includes the following sub-steps:

[0011] Step 31, during the working process of the detection counter, real-time detection of the rising edge of the new frequency-divided signal obtained in step 1;

[0012] Step 32, set a two-bit register and initialize its value to 00;

[0013] Step 33, register assignment circular shift operation, specifically: the lowest bit of the register is replaced by 0 with the new frequency division signal obtained in step 1 and then assigned to the register. When the rising edge of the working clock comes, if the detection value of the register is 01, the detection result is "the rising edge of the frequency division signal is detected", if the detection value of the register is other values, the detection result is "the rising edge of the frequency division signal is not detected";

[0014] Step 33, when the rising edge of the frequency division signal is detected, the detection counter performs an accumulation operation, otherwise the detection counter keeps the original value unchanged;

[0015] Step 4: Check whether the new frequency-divided signal obtained in step 1 has lost frequency.

[0016] Furthermore, step 2 includes the following sub-steps:

[0017] Step 21, calculating the counting threshold of the clear counter according to the frequency of the working clock and the frequency of the new frequency-divided signal obtained in step 1;

[0018] Step 22, the clear counter continues to accumulate according to the counting threshold until its count value reaches the counting threshold; when the count value does not reach the threshold, the clear flag is set to a low level, and when the count value reaches the threshold, the clear flag is set to a high level; when the clear flag is a high level, the count value of the clear counter is set to zero.

[0019] Furthermore, in step 21, the counting threshold calculation formula of the clearing counter is as follows:

[0020] CNT_VALUE=fre / div_fre; (1)

[0021] Among them, CNT_VALUE is the counting threshold of the clear counter, fre is the frequency of the working clock, and div_fre is the frequency of the new divided signal.

[0022] Furthermore, step 4 includes the following sub-steps:

[0023] Step 41, setting a frequency loss counter to determine whether the new frequency division signal obtained in step 1 loses frequency; under the condition that the clear flag is at a high level, observing whether the value of the detection counter reaches its counting threshold, if so, setting the value of the frequency loss counter to zero, and entering step 43; otherwise, accumulating the value of the frequency loss counter, and entering step 42;

[0024] Step 42, when the value of the frequency loss counter reaches the counting threshold, the value is kept unchanged; otherwise, the frequency loss counter continues to accumulate the count and the process proceeds to step 43;

[0025] Step 43: judging whether the clock signal to be detected has lost its frequency according to the value of the frequency loss counter.

[0026] Furthermore, in step 41, the counting threshold of the detection counter is set: for a regular clock signal with a complete frequency, it can be calculated by formula (1); for a signal to be tested with an incomplete frequency, the counting threshold is set to be less than the counting threshold of the clearing counter obtained in step 2.

[0027] Furthermore, in step 43, if the value of the frequency loss counter is the set threshold, it indicates that the new frequency-divided signal obtained in step 1 has lost the frequency, or that no regular clock signal has been detected, thereby inferring that the clock signal to be measured has lost the frequency; if the value of the frequency loss counter is zero, it indicates that the new frequency-divided signal obtained in step 1 is a clock signal, or that a clock signal has been detected, thereby inferring that the clock signal to be measured has lost the frequency.

[0028] Compared with the prior art, the frequency detection method of the present invention has the following technical effects:

[0029] (1) The present invention introduces a stable working clock to detect a clock signal of a certain frequency, thereby eliminating the need for instruments, reducing detection costs, and simplifying detection steps.

[0030] (2) The present invention determines the number of bits of the frequency division counter according to the frequency of the clock signal to be detected and the working clock frequency, that is, by dividing the frequency of the signal to be detected under the premise of an existing working clock, there is no requirement for the frequency difference between the frequency of the signal to be detected and the working frequency. Regardless of whether the frequency of the signal to be detected is higher than the existing working clock frequency, in principle, it is possible to detect whether the clock signal is normal. For clock signals whose frequency is higher than the existing working clock frequency, frequency detection can be achieved by dividing the frequency using the method of the present invention, thereby expanding the scope of application of frequency detection.

[0031] (3) By synchronously processing the frequency-divided signal, the detection instability problem caused by the asynchrony between the clock signal to be detected and the working clock frequency is avoided, making the result of detecting the clock signal more reliable.

[0032] (4) The method of the present invention can determine the presence or absence of a frequency signal and is widely used in fields such as oscilloscopes and multiple reference sources that require frequency signal switching. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is the preparation work for frequency detection;

[0034] Figure 2 It is the workflow diagram of clearing the counter;

[0035] Figure 3 It is the workflow diagram of the detection counter;

[0036] Figure 4 It is the workflow diagram of frequency detection;

[0037] Figure 5 It is a detection counter threshold simulation waveform of a regular signal to be detected implemented by the present invention;

[0038] Figure 6 It is a simulation waveform diagram of the detection result of the incomplete clock signal to be detected implemented by the present invention. DETAILED DESCRIPTION

[0039] The implementation of the technical solution is further described in detail below in conjunction with the accompanying drawings.

[0040] Example

[0041] The clock frequency detection method provided in this embodiment is implemented by FPGA (Field Program Gate Array), and specifically comprises the following steps:

[0042] Step 1: Prepare for frequency detection.

[0043] Specifically, Figure 1 As shown, step 1 includes the following sub-steps:

[0044] Step 11, determine the number of bits of the frequency division counter according to the frequency of the clock signal to be tested and the working clock frequency, requiring the frequency of the divided clock signal to be half, one quarter or other smaller even number of the working clock frequency. This facilitates the subsequent flexible setting of the detection value of the detection frequency division counter according to actual needs.

[0045] Step 12, beat the divided clock signal twice on the rising edge of the working clock to obtain a new divided clock signal.

[0046] In actual operation, the frequency of the original clock signal to be tested is inferred by detecting the frequency of the new frequency-divided signal, which can reduce the frequency of the detection signal. In this step, the new frequency-divided signal obtained by beating the divided clock signal twice on the rising edge of the working clock is a signal that is completely synchronized with the rising edge of the working clock, and does not change the frequency of the original space-time signal to be tested. However, when the clock signal to be tested is an asynchronous signal compared to the working clock, using the signal after beating twice to detect the frequency is more stable and reliable than the signal before beating. It fully considers the processing when the signal to be tested is asynchronous, so that the consideration is more comprehensive, thereby achieving the purpose of detection.

[0047] Step 2, calculating the counting threshold of the clear counter, and setting the counting value of the clear counter according to the counting threshold. Specifically, step 2 includes the following sub-steps:

[0048] Step 21, calculating the counting threshold of the clear counter according to the frequency of the working clock and the frequency of the new frequency-divided signal obtained in step 1.

[0049] Specifically, Figure 2 As shown, the counting threshold calculation formula for clearing the counter is as follows:

[0050] CNT_VALUE=fre / div_fre; (1)

[0051] Among them, CNT_VALUE is the counting threshold of the clear counter, fre is the frequency of the working clock, and div_fre is the frequency of the new divided signal;

[0052] Step 22, the clear counter continues to accumulate according to the counting threshold until its count value reaches the counting threshold; when the count value does not reach the threshold, the clear flag is set to a low level, and when the count value reaches the threshold, the clear flag is set to a high level; when the clear flag is a high level, the count value of the clear counter is set to zero.

[0053] Step 3: Start the detection counter.

[0054] like Figure 3 The detection counter workflow is shown. Step 3 includes the following sub-steps:

[0055] Step 31, during the working process of the detection counter, real-time detection of the rising edge of the new frequency-divided signal obtained in step 1;

[0056] Step 32, set a two-bit register and initialize its value to 00.

[0057] Step 33, register assignment circular shift operation. Specifically: the lowest bit of the register is replaced from 0 to the new frequency division signal obtained in step 1 and then assigned to the register. When the rising edge of the working clock comes, if the detection value of the register is 01, the detection result is "the rising edge of the frequency division signal is detected", if the detection value of the register is other values ​​(including 00, 10, 11), the detection result is "the rising edge of the frequency division signal is not detected".

[0058] Step 33, when the rising edge of the frequency division signal is detected, the detection counter performs an accumulation operation, otherwise the detection counter keeps the original value unchanged.

[0059] It should be noted that the detection of the rising edge of the working clock signal is used as an example for explanation here. In fact, the detection of the falling edge of the working clock signal is also feasible, and the principle is similar.

[0060] Step 4: Check whether the new frequency-divided signal obtained in step 1 has lost frequency.

[0061] like Figure 4 As shown, step 4 includes the following sub-steps:

[0062] Step 41, setting a frequency loss counter to determine whether the new frequency division signal obtained in step 1 loses frequency; under the condition that the clear flag is at a high level, observing whether the value of the detection counter reaches its counting threshold, if so, setting the value of the frequency loss counter to zero (clearing), and entering step 43; otherwise, accumulating the value of the frequency loss counter, and entering step 42;

[0063] Specifically, the setting of the counting threshold of the detection counter: for a regular clock signal with a complete frequency, it can be calculated by formula (1); for a signal to be detected with an incomplete frequency, the counting threshold is set to be less than the counting threshold of the clearing counter obtained in step 2. Therefore, the present invention can be used for the detection of clock signals with a complete frequency as well as signals with an incomplete frequency.

[0064] Step 42, when the value of the frequency loss counter reaches the counting threshold, the value is kept unchanged; otherwise, the frequency loss counter continues to accumulate the count and the process proceeds to step 43;

[0065] Preferably, the counting threshold of the frequency loss counter is obtained: as long as the value of the counter is not zero and is accumulated, it means that the clock to be detected has frequency loss, so the most convenient and fast counting threshold is set to 1. However, for irregular clock signals, the time of frequency loss will be very long. At this time, the counting threshold can be set larger (set to 3 in this embodiment) to detect for a longer period of time, which only consumes some time and will not change the detection result. Therefore, the counting threshold of the frequency loss counter can also be set in combination with the specific situation of the irregularity of the actual clock signal.

[0066] Step 43: judging whether the clock signal to be detected has lost its frequency according to the value of the frequency loss counter.

[0067] Specifically, if the value of the frequency loss counter is the set threshold, it indicates that the new frequency-divided signal obtained in step 1 has lost the frequency, or that a regular clock signal has not been detected, thereby inferring that the clock signal to be measured has lost the frequency; if the value of the frequency loss counter is zero, it indicates that the new frequency-divided signal obtained in step 1 is a clock signal, or that a clock signal has been detected, thereby inferring that the clock signal to be measured has lost the frequency.

[0068] Figure 5 is an embodiment of the method of the present invention, Figure 5 The working frequency is 100Mhz, and the detected clock frequency is a regular clock signal of 20Mhz, which is divided into 10MHz after the frequency division, and the clock frequency after the frequency division is one tenth of the working frequency. Then the calculation result of the counting threshold in step 2 is 10.

[0069] Figure 6 is an embodiment of the present invention, a simulation diagram of the detection result of detecting an irregular signal, from Figure 6 It can be seen that when the threshold of the lost frequency counter is set to 2, the detection result is a high level, indicating that frequency loss is detected.

[0070] The clock frequency detection method proposed in the present invention solves the problem of determining whether the frequency of the clock signal to be detected is lost by setting several groups of counters (including clearing counters, detection counters, and frequency loss counters) in the absence of instrument detection, thereby reducing the cost of clock signal detection and simplifying the detection method. During detection, the detection method is extended to a working range where the clock signal frequency is higher than the working frequency, as well as the detection of some asynchronous signals, by frequency division and synchronization. At the same time, by analyzing the specific process of case application, the method can be extended to some detections of the frequency of some non-clock signals. Undoubtedly, the scheme has wider adaptability. During the implementation of the scheme, synchronous processing of the signal is also adopted to ensure that the implementation of the scheme is more reliable.

[0071] It is worth noting that, in the implementation process of the present invention, the rising edge of the clock signal is used as an example for explanation, but in fact, the falling edge of the clock signal can also be used to achieve the purpose of the present invention. Therefore, within the framework of the present invention, any reasonable inference made in combination with the knowledge in the technical field belongs to the protection scope of the present invention.

Claims

1. A clock frequency detection method, characterized in that: The specific steps include: Step 1, prepare for frequency detection, including the following sub-steps: Step 11, determining the number of bits of the frequency division counter according to the frequency of the clock signal to be measured and the working clock frequency, requiring that the frequency of the divided clock signal is one-half, one-quarter or other smaller even-numbered fraction of the working clock frequency; Step 12, beat the divided clock signal twice on the rising edge of the working clock to obtain a new divided clock signal; Step 2, calculating a count threshold of the clear counter, and setting the count value of the clear counter according to the count threshold; Step 3, starting the detection counter counting, includes the following sub-steps: Step 31, during the working process of the detection counter, real-time detection of the rising edge of the new frequency-divided signal obtained in step 1; Step 32, set a two-bit register and initialize its value to 00; Step 33, register assignment circular shift operation, specifically: replace the lowest bit of the register from 0 to the new frequency division signal obtained in step 1 and then assign it to the register. When the rising edge of the working clock comes, if the detection value of the register is 01, the detection result is "the rising edge of the frequency division signal is detected", if the detection value of the register is other values, the detection result is "the rising edge of the frequency division signal is not detected"; Step 33, when the rising edge of the frequency division signal is detected, the detection counter performs an accumulation operation, otherwise the detection counter keeps the original value unchanged; Step 4: Check whether the new frequency-divided signal obtained in step 1 has lost frequency.

2. The clock frequency detection method according to claim 1, characterized in that: Step 2 includes the following sub-steps: Step 21, calculating the counting threshold of the clear counter according to the frequency of the working clock and the frequency of the new frequency-divided signal obtained in step 1; Step 22, the clear counter continues to accumulate according to the counting threshold until its count value reaches the counting threshold; when the count value does not reach the threshold, the clear flag is set to a low level, and when the count value reaches the threshold, the clear flag is set to a high level; when the clear flag is a high level, the count value of the clear counter is set to zero.

3. The clock frequency detection method according to claim 2, characterized in that: In step 21, the counting threshold calculation formula for clearing the counter is as follows: CNT_VALUE=fre / div_fre; (1) Among them, CNT_VALUE is the counting threshold of the clear counter, fre is the frequency of the working clock, and div_fre is the frequency of the new divided signal.

4. The clock frequency detection method according to claim 2, characterized in that: Step 4 includes the following sub-steps: Step 41, setting a frequency loss counter to determine whether the new frequency division signal obtained in step 1 loses frequency; under the condition that the clear flag is at a high level, observing whether the value of the detection counter reaches its counting threshold, if so, setting the value of the frequency loss counter to zero, and entering step 43; otherwise, accumulating the value of the frequency loss counter, and entering step 42; Step 42, when the value of the frequency loss counter reaches the counting threshold, keep the value unchanged; Otherwise, the frequency loss counter continues to count up, and the process goes to step 43; Step 43: judging whether the clock signal to be detected has lost its frequency according to the value of the frequency loss counter.

5. The clock frequency detection method according to claim 4, characterized in that: In step 41, the counting threshold of the detection counter is set: for a regular clock signal with a complete frequency, it can be calculated by formula (1); for a signal to be tested with an incomplete frequency, the counting threshold is set to be smaller than the counting threshold of the clearing counter obtained in step 2.

6. The clock frequency detection method according to claim 4, characterized in that: In step 43, if the value of the frequency loss counter is the set threshold, it indicates that the new frequency-divided signal obtained in step 1 is lost, or that no regular clock signal is detected, thereby inferring that the clock signal to be measured is lost. If the value of the frequency loss counter is zero, it means that the new frequency-divided signal obtained in step 1 is a clock signal, or the clock signal is detected, thereby inferring the loss frequency of the clock signal to be measured.

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