Test method, system and equipment for realizing FPGA prototype of intelligent cabin scene and storage medium

Abstract

The invention discloses a test method, system and device for realizing an intelligent cabin scene FPGA prototype, and a storage medium, and belongs to the technical field of automobiles, and the method comprises the steps: dividing an SOC system into various IPs; integrating the cut RTL codes of the IPs into a gate-level integrated netlist which can be identified by the FPGA, and downloading the gate-level integrated netlist to a prototype verification hardware platform; loading the test case, performing function and performance verification on each IP, and judging whether the verification is passed or not; if the verification is passed, performing the next step; the IPs, peripherals and channels of the qualified intelligent cockpit are integrated to form a complete intelligent cockpit link, and a scene-level verification system of the intelligent cockpit is formed; performing back-end integration on the complete intelligent cockpit link; the integrated intelligent cabin resources are downloaded to a hardware verification platform; loading a test case, and performing function verification on the intelligent cabin business scene; and if the verification is passed, ending the process. According to the method, a complete solution is provided for verification of an intelligent cabin scene of a super-large-scale SoC, verification efficiency and accuracy are remarkably improved, and a solid foundation is laid for successful mass production of chips.

Description

Technical Field

[0001] The present invention belongs to the field of automobile technology, and specifically relates to a testing method, system, device and storage medium for realizing an FPGA prototype of an intelligent cockpit scenario. Background Art

[0002] FPGA prototype verification refers to verifying the functions and performance of application-specific integrated circuits (ASICs) and systems on chips (SoCs) by porting RTL to field programmable gate arrays (FPGAs). FPGA prototype verification can evaluate the functions and performance of chips before integrated circuit (IC) tape-out. It can not only ensure that the integrated circuit (IC) implementation model matches the expected design performance and improve the tape-out success rate, but also provide a verification platform for software designers, allowing software and chips to be developed simultaneously, accelerating the time to market for products. FPGA prototype verification plays a very important role in SoC and ASIC system verification.

[0003] As the chip design field continues to move towards a new stage of higher scale and greater complexity, the demand for FPGA prototype verification for domain-integrated SoCs is becoming more urgent. Although current technology has made great progress in shortening time to market and revealing potential software and hardware defects, it is still insufficient in chip verification for smart cockpit business scenarios, especially in achieving comprehensive scenario-level verification of each module function, peripherals and channels.

[0004] The traditional verification method divides the verification system into several subsystem modules and verifies them on multiple verification platforms. This approach often makes it difficult to accurately evaluate the functional integrity and performance when dealing with complex scenarios such as smart cockpits. Summary of the invention

[0005] In view of the above-mentioned defects in the prior art, the present invention provides a test method, system, device and storage medium for realizing the FPGA prototype of the smart cockpit scenario. The method cuts the ultra-large-scale SoC into individual IPs, and synthesizes and verifies them separately, and then integrates the smart cockpit link to realize the SoC scenario-level FPGA prototype verification. The system and method can realize integrated verification from the IP level to the smart cockpit business scenario by building an integrated verification environment, providing a complete solution for the verification of the smart cockpit scenario of the ultra-large-scale SoC, significantly enhancing the verification efficiency and accuracy, and laying a solid foundation for the successful mass production of chips.

[0006] The present invention is achieved through the following technical solutions:

[0007] In a first aspect, the present invention provides a testing method for realizing an FPGA prototype of a smart cockpit scenario, which specifically comprises the following steps:

[0008] Step 1: Divide the SOC system into individual IPs;

[0009] Step 2: Synthesize the RTL codes of each IP into a gate-level integrated netlist that can be recognized by FPGA, and download it to the prototype verification hardware platform;

[0010] Step 3: Load the test case, verify the function and performance of each IP, and determine whether the verification passes; if the verification passes, proceed to the next step;

[0011] Step 4: Integrate the verified smart cockpit IPs, peripherals and channels to form a complete smart cockpit link and a smart cockpit scenario-level verification system;

[0012] Step 5: Perform back-end integration of the complete smart cockpit link;

[0013] Step 6: Download the integrated smart cockpit resources to the hardware verification platform;

[0014] Step 7: Load the test case and perform functional verification on the smart cockpit business scenario; if the verification passes, end the process.

[0015] Furthermore, in step one, the SOC system is divided into a series of IPs including CPU, DPU, DPC, GPU, MCU and general peripherals.

[0016] Furthermore, in step three, if the verification fails, the logic code of the modified IP is returned and integrated and verified again.

[0017] Furthermore, in step 4, the intelligent cockpit scene-level verification system includes a CPU, a GPU module, a VPU module, a DPC display module, an MCU security module and general peripherals;

[0018] The CPU is used to send instructions through the bus to complete system startup and work scheduling between subsystems;

[0019] The general peripherals are used for data storage, including system images, audio and video data streams;

[0020] The GPU module is used to complete graphics drawing and layer aliasing functions according to software instructions;

[0021] The VPU module is used to complete the decoding and encoding of audio and video data;

[0022] The DPC display module is used to complete the final video data display function;

[0023] The MCU security module is used to monitor the safety of the entire bus and the entire system and collect fault information.

[0024] Furthermore, in step seven, if the verification fails, the logic code for modifying the smart cockpit link is returned.

[0025] In a second aspect, the present invention further provides a test system for realizing an FPGA prototype of a smart cockpit scenario, which is used to implement the test method described in the first aspect, including:

[0026] A partitioning module is used to divide the SOC system into various IPs;

[0027] The synthesis module is used to synthesize the RTL codes of each IP after cutting into a gate-level synthesis netlist that can be recognized by FPGA and download it to the prototype verification hardware platform;

[0028] The first function verification module is used to load test cases, verify the functions and performance of each IP, and determine whether the verification is passed; if the verification is passed, proceed to the next step;

[0029] Integration module, which is used to integrate the verified smart cockpit IPs, peripherals and channels to form a complete smart cockpit link and a smart cockpit scenario-level verification system;

[0030] The back-end integration module is used to integrate the complete smart cockpit link into the back-end;

[0031] Download module, used to download the integrated smart cockpit resources to the hardware verification platform;

[0032] The second function verification module is used to load test cases and perform functional verification on the smart cockpit business scenario; if the verification passes, the process ends.

[0033] In a third aspect, the present invention further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, a testing method for realizing an FPGA prototype for an intelligent cockpit scenario as described in any one of the present inventions is implemented.

[0034] In a fourth aspect, the present invention further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a testing method for realizing an FPGA prototype for an intelligent cockpit scenario as described in any one of the present inventions.

[0035] Compared with the prior art, the advantages of the present invention are as follows:

[0036] The present invention provides a testing method, system, device and storage medium for realizing an FPGA prototype for a smart cockpit scenario. The system and method can realize integrated verification from the IP level to the smart cockpit business scenario by constructing an integrated verification environment, providing a complete solution for the verification of smart cockpit scenarios of ultra-large-scale SoCs, significantly enhancing the verification efficiency and accuracy, and laying a solid foundation for the successful mass production of chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the specific embodiments or the description of the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn according to the actual scale.

[0038] Figure 1 It is a flowchart of a testing method for realizing an FPGA prototype of an intelligent cockpit scenario of the present invention;

[0039] Figure 2 This is a schematic diagram of the FPGA prototype verification platform;

[0040] Figure 3 This is a schematic diagram of the smart cockpit service link;

[0041] Figure 4 This is a schematic diagram of the structure of an electronic device in Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0042] In order to clearly and completely describe the technical solution and its specific working process of the present invention, the specific implementation methods of the present invention are as follows in conjunction with the accompanying drawings of the specification:

[0043] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0044] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0045] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0046] Example 1

[0047] like Figure 1 As shown, this embodiment provides a test method for realizing an FPGA prototype of a smart cockpit scenario, which specifically includes the following steps:

[0048] Step 1: Divide the SOC system into individual IPs;

[0049] like Figure 2 As shown in the figure, the FPGA prototype verification hardware platform can run the SoC system (CPU, GPU, VPU, DPC, MCU and other modules), the test PC is used for version download and visual debugging, the USB is used to download the logic version to the hardware platform, the JTag is used to debug the SoC through the emulator, the serial port is used for the PC to view the SoC debugging information in real time, and the network port is used to download the software version to the hardware platform.

[0050] The SOC system is divided into a series of IPs including CPU, DPU, DPC, GPU, MCU and general peripherals.

[0051] Step 2: Synthesize the RTL codes of each IP into a gate-level integrated netlist that can be recognized by FPGA, and download it to the prototype verification hardware platform;

[0052] Step 3: Load the test case, verify the function and performance of each IP, and determine whether the verification passes; if the verification passes, proceed to the next step; if the verification fails, return to modify the logic code of the IP, and perform synthesis and verification again.

[0053] Step 4: Integrate the verified smart cockpit IPs, peripherals and channels to form a complete smart cockpit link and a smart cockpit scenario-level verification system;

[0054] like Figure 3 As shown, the intelligent cockpit scene-level verification system includes a CPU, a GPU module, a VPU module, a DPC display module, an MCU security module and general peripherals;

[0055] The CPU is used to send instructions through the bus to complete system startup and work scheduling between subsystems;

[0056] The general peripherals are used for data storage, including system images, audio and video data streams;

[0057] The GPU module is used to complete graphics drawing and layer aliasing functions according to software instructions;

[0058] The VPU module is used to complete the decoding and encoding of audio and video data;

[0059] The DPC display module is used to complete the final video data display function;

[0060] The MCU security module is used to monitor the safety of the entire bus and the entire system and collect fault information.

[0061] Step 5: Perform back-end integration of the complete smart cockpit link;

[0062] Step 6: Download the integrated smart cockpit resources to the hardware verification platform;

[0063] Step 7: Load the test case and perform functional verification on the smart cockpit business scenario; if the verification passes, end the process; if the verification fails, return to modify the logic code of the smart cockpit link.

[0064] Example 2

[0065] This embodiment provides a test system for realizing an intelligent cockpit scenario FPGA prototype, which is used to implement the test method described in the first aspect, including:

[0066] A partitioning module is used to divide the SOC system into various IPs;

[0067] The synthesis module is used to synthesize the RTL code of each IP into a gate-level synthesis netlist that can be recognized by FPGA and download it to the prototype verification hardware platform

[0068] The first function verification module is used to load test cases, verify the functions and performance of each IP, and determine whether the verification is passed; if the verification is passed, proceed to the next step;

[0069] Integration module, which is used to integrate the verified smart cockpit IPs, peripherals and channels to form a complete smart cockpit link and a smart cockpit scenario-level verification system;

[0070] The back-end integration module is used to integrate the complete smart cockpit link into the back-end;

[0071] Download module, used to download the integrated smart cockpit resources to the hardware verification platform;

[0072] The second function verification module is used to load test cases and perform functional verification on the smart cockpit business scenario; if the verification passes, the process ends.

[0073] Example 3

[0074] Figure 4 This is a schematic diagram of the structure of a computer device in Example 3 of the present invention. Figure 4 A block diagram of an exemplary computer device 12 suitable for use in implementing embodiments of the present invention is shown. Figure 4 The computer device 12 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0075] like Figure 4 As shown, the computer device 12 is in the form of a general-purpose computing device. The components of the computer device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 that connects various system components (including the system memory 28 and the processing unit 16).

[0076] Bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor or a local bus using any of a variety of bus architectures. By way of example, these architectures include, but are not limited to, an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MAC) bus, an Enhanced ISA bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus.

[0077] The computer device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the computer device 12, including volatile and non-volatile media, removable and non-removable media.

[0078] The system memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. The computer device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the storage system 34 may be used to read and write non-removable, non-volatile magnetic media ( Figure 4 not shown, usually called a "hard drive"). Although Figure 4 Not shown in the figure, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk"), and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, a DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to the bus 18 via one or more data medium interfaces. The memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of the various embodiments of the present invention.

[0079] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in the memory 28. Such program modules 42 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment. The program modules 42 generally perform the functions and / or methods of the embodiments described herein.

[0080] The computer device 12 may also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), may also communicate with one or more devices that enable a user to interact with the computer device 12, and / or communicate with any device that enables the computer device 12 to communicate with one or more other computing devices (e.g., network card, modem, etc.). Such communication may be performed through an input / output (I / O) interface 22. In addition, the computer device 12 in this embodiment, the display 24 does not exist as an independent individual, but is embedded in the mirror surface, and when the display surface of the display 24 is not displayed, the display surface of the display 24 and the mirror surface are visually integrated. In addition, the computer device 12 may also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN) and / or public network, such as the Internet) through a network adapter 20. As shown in the figure, the network adapter 20 communicates with other modules of the computer device 12 through a bus 18. It should be understood that although not shown in the figures, other hardware and / or software modules may be used in conjunction with the computer device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0081] The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing the FPGA prototype testing method for realizing the smart cockpit scenario provided by the embodiment of the present invention.

[0082] Example 4

[0083] Embodiment 4 of the present invention provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the FPGA prototype testing method for realizing a smart cockpit scenario as provided in all the embodiments of the invention of this application is implemented.

[0084] Any combination of one or more computer-readable media may be used. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, device, or device.

[0085] Computer-readable signal media may include a data signal propagated in baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0086] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0087] Computer program code for performing the operations of the present invention may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0088] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A test method for realizing an FPGA prototype of an intelligent cockpit scenario, characterized in that: The specific steps include: Step 1: Divide the SOC system into individual IPs; Step 2: Synthesize the RTL codes of each IP into a gate-level integrated netlist that can be recognized by FPGA, and download it to the prototype verification hardware platform; Step 3: Load the test case, verify the function and performance of each IP, and determine whether the verification passes; if the verification passes, proceed to the next step; Step 4: Integrate the verified smart cockpit IPs, peripherals and channels to form a complete smart cockpit link and a smart cockpit scenario-level verification system; Step 5: Perform back-end integration of the complete smart cockpit link; Step 6: Download the integrated smart cockpit resources to the hardware verification platform; Step 7: Load the test case to verify the function of the smart cockpit business scenario; If the verification is successful, the process ends.

2. The testing method for realizing the FPGA prototype of the intelligent cockpit scenario according to claim 1, characterized in that: In step one, the SOC system is divided into a series of IPs including CPU, DPU, DPC, GPU, MCU and general peripherals.

3. The testing method for realizing the FPGA prototype of the intelligent cockpit scenario according to claim 1, characterized in that: In step three, if the verification fails, return to modify the logic code of the IP and perform synthesis and verification again.

4. The testing method for realizing the FPGA prototype of the intelligent cockpit scenario according to claim 1, characterized in that: In step 4, the intelligent cockpit scene-level verification system includes a CPU, a GPU module, a VPU module, a DPC display module, an MCU security module and general peripherals; The CPU is used to send instructions through the bus to complete system startup and work scheduling between subsystems; The general peripherals are used for data storage, including system images, audio and video data streams; The GPU module is used to complete graphics drawing and layer aliasing functions according to software instructions; The VPU module is used to complete the decoding and encoding of audio and video data; The DPC display module is used to complete the final video data display function; The MCU security module is used to monitor the safety of the entire bus and the entire system and collect fault information.

5. The testing method for realizing the FPGA prototype of the intelligent cockpit scenario according to claim 1, characterized in that: In step seven, if the verification fails, the logic code for modifying the smart cockpit link is returned.

6. A test system for realizing an FPGA prototype of a smart cockpit scenario, used to implement the method according to any one of claims 1 to 5, characterized in that: include: A partitioning module is used to divide the SOC system into various IPs; The synthesis module is used to synthesize the RTL codes of each IP after cutting into a gate-level synthesis netlist that can be recognized by FPGA and download it to the prototype verification hardware platform; The first function verification module is used to load test cases, verify the functions and performance of each IP, and determine whether the verification is passed; if the verification is passed, proceed to the next step; Integration module, which is used to integrate the verified smart cockpit IPs, peripherals and channels to form a complete smart cockpit link and a smart cockpit scenario-level verification system; The back-end integration module is used to integrate the complete smart cockpit link into the back-end; Download module, used to download the integrated smart cockpit resources to the hardware verification platform; The second function verification module is used to load test cases and perform functional verification on the smart cockpit business scenario; If the verification is successful, the process ends.

7. A computer device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, a test method for realizing an FPGA prototype of an intelligent cockpit scenario as described in any one of claims 1 to 5 is implemented.

8. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the program is executed by a processor, the test method for realizing an FPGA prototype of an intelligent cockpit scenario as described in any one of claims 1 to 5 is implemented.

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