Verification method and system
The interconnect path file is identified and constructed from the pin file through scripting programs, which solves the problem of missing details in the prior art when verifying the chip interconnect path, and realizes a more efficient verification process.
Patent Information
- Application Number
- CN202411649902.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-19
- Publication Date
- 2025-03-21
AI Technical Summary
The prior art is prone to miss details when verifying chip interconnect paths, resulting in incomplete verification process and low verification efficiency, requiring multiple iterations to add and modify verification procedures.
Identify the pin name that the user needs to verify from the pin file through a script program, determine the trigger target name and function keywords, build an interconnect path file, and use verification tools to verify, avoid manually designing the verification program and improve efficiency.
This method not only avoids the omissions when manually designing verification programs, but also improves the verification efficiency of interconnect paths, reduces user workload, and improves user experience.
Smart Images
Figure CN119670685A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of chip interconnection path verification, and further to a verification method and system. Background Art
[0002] With the continuous development of integrated circuits, the process is becoming more and more advanced, the frequency is getting higher and higher, the chips are becoming more and more complex, the functions are being implemented more and more, and the interconnection paths inside the chip are increasing, which brings great challenges to the verification of chips. Existing verification methods usually rely on manually designed verification programs to ensure the correctness of the interconnection paths. However, this method is prone to missing certain details when constructing the connection relationship of the interconnection path, resulting in an incomplete verification process. In order to make up for these omissions, it is often necessary to continuously add and modify the verification program and perform multiple rounds of iterations. This practice significantly reduces the verification efficiency of the interconnection path. Summary of the invention
[0003] In order to solve the above technical problems, the present application provides a verification method and system, which not only avoids the problem of missing certain details when manually designing the verification program, resulting in an incomplete verification process, but also improves the verification efficiency of the interconnection path.
[0004] In a first aspect, the present application provides a verification method for verifying an interconnection path in a chip, comprising: determining a pin name from a pin file through a script program according to a core function or an extended function of a pin to be verified by a user; determining a trigger target name and a function keyword of the pin through the script program according to the pin name; when the script program determines that there is no delay in the interconnection path corresponding to the pin based on the pin name, controlling the script program to construct a first interconnection path file based on the pin name, the trigger target name and the function keyword; inputting the first interconnection path file and a first constraint file inside the script program into a verification tool, and controlling the verification tool to verify the first interconnection path file, wherein the first constraint file is used to replace the full name of the pin name and the full name of the trigger target name with the pin name and the trigger target name in the first interconnection path file.
[0005] This verification method uses a script program to identify the pin name that the user needs to verify from the pin file, and determines the trigger target name and function keyword accordingly. When it is detected that there is no delay in the interconnection path corresponding to the pin, the script can construct a corresponding first interconnection path file, so that the verification tool verifies the first interconnection path file. This method not only avoids the problem of missing certain details when manually designing the verification program, resulting in an incomplete verification process, but also improves the verification efficiency of the interconnection path. At the same time, the user only needs to maintain the pin file, without manually designing the verification program, which reduces the user's workload and improves the user's experience.
[0006] In one implementation, it also includes: when the script program determines that there is a delay in the interconnection path corresponding to the pin based on the pin name, obtaining the delay signal name and the delay signal value pre-stored in the script program; constructing a second interconnection path file through the script program based on the pin name, the trigger target name, the function keyword, the delay signal name and the delay signal value; inputting the second interconnection path file and the first constraint file into a verification tool so that the verification tool verifies the second interconnection path file, wherein the first constraint file is used to replace the full name of the pin name, the full name of the trigger target name and the full name of the delay signal name with the pin name, the trigger target name and the delay signal name in the second interconnection path file.
[0007] In this verification method, when a delay is detected in the interconnection path corresponding to the pin, the script program obtains the pre-stored delay signal name and delay signal value. Subsequently, the script program uses the pin name, trigger target name, function keyword and detailed information of the delay signal to construct a second interconnection path file containing delay information. This method improves the accuracy of the verification process and ensures that the delay factor is correctly handled. At the same time, the second interconnection path file is verified through the compiler mode of the verification tool, which not only reduces the simulation time, but also further improves the verification efficiency.
[0008] In one implementation, when verifying the core function of the pin, the core function includes multiple core sub-functions, and each core sub-function corresponds to an interconnection path; determining the function keyword of the pin through the script program based on the pin name specifically includes: controlling the script program to traverse the first constraint file to determine the starting point keyword and the end point keyword of each core sub-function of the pin; using the starting point keyword and the end point keyword of each core sub-function as the function keyword in turn, and constructing the first interconnection path file corresponding to each core sub-function.
[0009] In one implementation, when verifying the extended function of the pin, the extended function includes multiple extended sub-functions, each of which corresponds to an interconnection path; determining the function keyword of the pin through the script program based on the pin name specifically includes: controlling the script program to traverse the first constraint file to determine the starting point keyword and the end point keyword of each extended sub-function of the pin; when there is no enable bit or the enable bit is empty in the multiple extended sub-functions, taking the starting point keyword and the end point keyword of each extended sub-function as the function keyword in turn, and constructing the first interconnection path file corresponding to each extended sub-function.
[0010] In one implementation, it also includes: when there is an enable bit in multiple extended sub-functions, controlling the script program to traverse the first constraint file to determine the enable keyword corresponding to the pin; adding the enable keyword to the function keyword corresponding to each of the extended sub-functions, and then constructing the first interconnection path file corresponding to each of the extended sub-functions.
[0011] In one implementation, it also includes: if the extended function of other pins exists and is consistent with the extended function of the pin to be verified by the user, determining the pin name of the other pins from the pin file through the script program; controlling the script program to invert the pin name of the other pins, and constructing the first interconnection path file with the inverted pin name of the other pins, the pin name of the pin to be verified, the trigger target name and the function keyword.
[0012] In one implementation, it also includes: when the extended function of the pin to be verified by the user is an output function, the script program does not perform a negation operation on the pin names of the other pins; and controls the script program to construct the first interconnection path file using the pin names of the other pins that are not negated, the pin name of the pin to be verified, the trigger target name and the function keyword.
[0013] In one implementation, it also includes: configuring a second constraint file and a third constraint file, the second constraint file includes modules in the chip that do not require interconnection path verification, and the third constraint file is configured to fix the test signal of the pin that the user wants to verify; inputting the second constraint file and the third constraint file into the verification tool so that the verification tool does not perform verification operations on the module and the test signal.
[0014] This verification method can significantly improve the efficiency and pertinence of the verification process by configuring the second constraint file and the third constraint file. The second constraint file clearly points out the modules in the chip that do not need to be verified for the interconnection path, so that the verification tool can skip these modules and avoid wasting time and computing resources on unnecessary parts. The third constraint file is used to fix the test signal of the pin to be verified by the user, which simplifies the interconnection path file and speeds up the verification speed.
[0015] In one implementation, the pin file includes test signal parameters of the pin to be verified by the user, and the test signal parameters include a test signal name, a test signal default value, and a test signal enable value. It also includes: determining the test signal parameters from the pin file through the script program according to the pin name; controlling the script program to add the test signal parameters to the first interconnection path file; and when the script program identifies that the test signal enable value is a first numerical value, controlling the verification tool not to perform a verification operation on the test signal.
[0016] In a second aspect, the present application also provides a verification system for verifying an interconnection path in a chip, comprising: an identification module, configured to determine a pin name from a pin file through a script program according to a core function or an extended function of a pin to be verified by a user; the identification module is also configured to determine a trigger target name and a function keyword of the pin through the script program according to the pin name; a construction module, configured to control the script program to construct a first interconnection path file based on the pin name, the trigger target name and the function keyword when the script program determines that there is no delay in the interconnection path corresponding to the pin based on the pin name; a verification module, configured to input the first interconnection path file and a first constraint file inside the script program into a verification tool, and control the verification tool to verify the first interconnection path file, wherein the first constraint file is used to replace the full name of the pin name and the full name of the trigger target name with the pin name and the trigger target name in the first interconnection path file.
[0017] Compared with the prior art, the present invention has at least one of the following beneficial effects:
[0018] 1. Use a script to identify the pin name that the user needs to verify from the pin file, and determine the trigger target name and function keyword accordingly. When it is detected that there is no delay in the interconnection path corresponding to the pin, the script can construct the corresponding first interconnection path file, so that the verification tool verifies the first interconnection path file. This method not only avoids the problem of missing certain details when manually designing the verification program, resulting in an incomplete verification process, but also improves the verification efficiency of the interconnection path. At the same time, users only need to maintain the pin file, without manually designing the verification program, which reduces the user's workload and improves the user experience.
[0019] 2. When a delay is detected in the interconnection path corresponding to the pin, the script program obtains the pre-stored delay signal name and delay signal value. Subsequently, the script program uses the pin name, trigger target name, function keyword, and detailed information of the delay signal to construct a second interconnection path file containing delay information. This method improves the accuracy of the verification process and ensures that the delay factor is correctly handled. At the same time, the second interconnection path file is verified through the compiler mode of the verification tool, which not only reduces the simulation time, but also further improves the verification efficiency.
[0020] 3. By configuring the second constraint file and the third constraint file, the efficiency and pertinence of the verification process can be significantly improved. The second constraint file clearly points out the modules in the chip that do not need to be verified for interconnection paths, so that the verification tool can skip these modules and avoid wasting time and computing resources on unnecessary parts. The third constraint file is used to fix the test signal of the pin that the user wants to verify, which simplifies the interconnection path file and speeds up the verification. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The preferred implementation modes will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present invention.
[0022] Figure 1 A flow chart of a verification method provided by an embodiment of the present application is shown;
[0023] Figure 2 A flow chart of a verification method provided by an embodiment of the present application is shown;
[0024] Figure 3 A flow chart for determining a function keyword provided by an embodiment of the present application is shown;
[0025] Figure 4 A schematic diagram of a pin file for a pin core function provided by an embodiment of the present application is shown;
[0026] Figure 5A schematic diagram of a first constraint file for a pin core function provided by an embodiment of the present application is shown;
[0027] Figure 6 A schematic diagram of an interconnection path provided by an embodiment of the present application is shown;
[0028] Figure 7 A flow chart for determining a function keyword provided by an embodiment of the present application is shown;
[0029] Figure 8 A schematic diagram of a pin file for a pin extension function provided by an embodiment of the present application is shown;
[0030] Fig. 9 A schematic diagram of a first constraint file for a pin extension function provided in an embodiment of the present application is shown;
[0031] Fig.10 A schematic diagram of an interconnection path provided by an embodiment of the present application is shown. DETAILED DESCRIPTION
[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.
[0033] In order to simplify the drawings, only the parts related to the invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".
[0034] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.
[0035] In this document, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0036] In addition, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.
[0037] It should be noted that the above embodiments can be freely combined as needed. The above are only preferred embodiments of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.
[0038] GPIO (General Purpose Input / Output) is a multi-function interface on a microcontroller, microprocessor, or integrated circuit that allows developers to configure specific pins as input or output modes as needed. In input mode, GPIO pins can read the state of external signals, such as button presses or sensor data; in output mode, GPIO pins can control external devices, such as lighting up LED lights or driving motors. The flexibility of GPIO makes it a key component for embedded systems and electronic projects to interact with the outside world.
[0039] The core function of GPIO refers to its basic digital signal input and output capabilities, allowing microcontrollers, microprocessors or integrated circuits to interact directly with external digital devices or circuits. Extended functions refer to that in addition to basic input and output, GPIO pins can also be configured to perform specific peripheral functions, such as but not limited to GPIO pins can be combined with the timer / counter function of the microcontroller to generate accurate time delays or count external events; GPIO pins can be configured as serial communication interfaces for data communication with other devices, etc. The embodiment of the present application pre-sets the interconnection path corresponding to the function of each pin (or GPIO pin) in a script program (or python script program), so that when a user wants to verify the function of a certain pin, the script program can be used to determine other parameters on the interconnection path corresponding to the pin, and then the script program is used to build an interconnection path file. Finally, the interconnection path file is transferred to the verification tool to complete the verification, which can achieve at least one of the following beneficial effects: avoiding the problem of missing some details when manually designing the verification program, resulting in an incomplete verification process, and improving the verification efficiency of the interconnection path; or the user only needs to maintain a pin file, which reduces the user's workload and improves the user's experience.
[0040] The following is explained with reference to the accompanying drawings:
[0041] Reference Figure 1 , which shows a flow chart of a verification method provided by an embodiment of the present application. Figure 1 As shown, including:
[0042] S100, according to the core function or extended function of the pin to be verified by the user, determine the pin name from the pin file through a script program.
[0043] S110, determining the trigger target name and the function keyword of the pin through a script program according to the pin name.
[0044] S120, when the script program determines that there is no delay in the interconnection path corresponding to the pin based on the pin name, the script program is controlled to construct a first interconnection path file based on the pin name, the trigger target name and the function keyword.
[0045] S130, inputting the first interconnection path file and the first constraint file in the script program into the verification tool, and controlling the verification tool to verify the first interconnection path file, wherein the first constraint file is used to replace the full name of the pin name and the full name of the trigger target name with the pin name and the trigger target name in the first interconnection path file.
[0046] The verification tool is an EDA (Electronic Design Automation) tool (or static verification tool (VC_STATIC)), which verifies the interconnection path file through the internal compiler mode. The first constraint file (or path definition file) includes the full name of the pin name, the full name of the trigger target name, and the function keyword. The pin file (which can be an Excel file) includes the pin name and the name of the extended function corresponding to each pin.
[0047] The user can determine the core function or extended function of the pin to be verified from the pin file according to the needs. When verifying the core function of the pin, the script program traverses the pin file to determine the pin name (or the starting point of the interconnection path) of the pin to be verified by the user. Since the interconnection path corresponding to the core function of each pin has been pre-set inside the script program, the script program can directly determine the trigger target name (or the end point of the interconnection path) corresponding to the pin name after identifying the pin name. Then, the script program traverses the first constraint file based on the pin name and the trigger target name to determine the function keyword (or starting point keyword) corresponding to the pin name and the function keyword (or end point keyword) corresponding to the trigger target name. The script program further constructs the first interconnection path file based on the pin name and its corresponding function keyword, the trigger target name and its corresponding function keyword. The code in the first interconnection path file is as follows:
[0048] add_cc-src${PATH_PD0}.Y-dest${PATH_GPIOD}.GPIOIN[0]-name
[0049] "PD0_Y_to_GPIOD_GPIOIN0".
[0050] Among them, add_cc is automatically added by the script program when constructing the first interconnection file, and is printed into the first interconnection path file through the print statement. It is also the keyword for the verification tool to identify the first interconnection verification file; -src${} is automatically added by the script program when constructing the first interconnection file, and is printed into the first interconnection path file through the print statement; PATH_PD0 is the script program that determines the location of the keyword 'Pad Name' by traversing the pin file, and then traverses the names of all pins until the pin name to be verified is found, and then prints out PATH_"Pin Name"; Y is the function keyword corresponding to the pin name determined by the script program traversing the first constraint file; -dest${} is automatically added by the script program when constructing the first interconnection file, and is printed into the first interconnection path file through the print statement; PATH_GPIOD is the trigger target name, which is directly printed out by the script program after identifying the pin name PD0. The specific principle is: PATH_GPIOD is the script program that determines the keyword 'Pad Name' by traversing the pin file Name', then iterates over all pin names until the pin name to be verified is found, and then prints out PATH_GPIO "x" (x is the pin grouping, usually uppercase letters such as A, B, C, D. For example, if the pin name is PD0, the corresponding PATH_GPIO "x" is PATH_GPIO "D"); GPIOIN is the function keyword corresponding to the trigger target name determined by the script program traversing the first constraint file; [0] is the script program traversing the pin file to determine the position of the keyword 'Pad Name', then iterates over all pin names until the pin name to be verified is found, and then prints out ["y"] (y is the pin number in each group, usually a number such as 0, 1, 2, 3. For example, if the pin name is PD0, the corresponding y is 0); -name is automatically added by the script program when constructing the first interconnection file, and is printed to the first interconnection path file through the print statement; PD0_Y_to_GPIOD_GPIOIN0 has been explained in the previous content and will not be repeated here.
[0051] Furthermore, the script program inputs the constructed first interconnection path file and the first constraint file into the verification tool, so that the verification tool verifies the first interconnection path file.
[0052] The code in the first interconnection path file in the above example is the interconnection path corresponding to a core sub-function of the core function of the pin. Therefore, when verifying the core function of the pin, the script program will construct a corresponding first interconnection path file for each core sub-function, so that the verification tool verifies the first interconnection path files corresponding to all core sub-functions, thereby completing the verification of the core function of the pin. Among them, the logic of constructing the path for each core sub-function is the same.
[0053] Similarly, when verifying the extended function of the pin, the script program traverses the pin file to determine the pin name of the pin to be verified by the user, and directly determines the trigger target name corresponding to the pin name. Then, the script program traverses the first constraint file based on the pin name and the trigger target name to determine the function keyword corresponding to the pin name and the function keyword corresponding to the trigger target name. The script program constructs a first interconnection path file based on the pin name and its corresponding function keyword, the trigger target name and its corresponding function keyword. Then the script program inputs the first interconnection path file and the first constraint file into the verification tool for verification. The extended function also includes multiple extended sub-functions, and the script program will also construct a corresponding first interconnection path file for each extended sub-function, so that the verification tool verifies the first interconnection path files corresponding to all extended sub-functions, thereby completing the verification of the extended function of the pin. Among them, the logic of the path constructed by each extended sub-function is the same as the core sub-function. Here, the code in the first interconnection path corresponding to the extended function is no longer exemplified.
[0054] The embodiment of the present application uses a script program to identify the pin name that the user needs to verify from the pin file, and determines the trigger target name and function keyword accordingly. When it is detected that there is no delay in the interconnection path corresponding to the pin, the script can construct a corresponding first interconnection path file, so that the verification tool verifies the first interconnection path file. This method not only avoids the problem of missing certain details when manually designing the verification program, resulting in an incomplete verification process, but also improves the verification efficiency of the interconnection path. At the same time, the user only needs to maintain the pin file, without manually designing the verification program, which reduces the user's workload and improves the user's experience.
[0055] Reference Figure 2 , which shows a flow chart of a verification method provided by an embodiment of the present application. Figure 2 As shown, including:
[0056] S200, when the script program determines that there is a delay in the interconnection path corresponding to the pin based on the pin name, obtain the delay signal name and delay signal value pre-stored in the script program.
[0057] S210, constructing a second interconnection path file through a script program based on the pin name, the trigger target name, the function keyword, the delay signal name and the delay signal value.
[0058] S220, input the second interconnection path file and the first constraint file into the verification tool, so that the verification tool verifies the second interconnection path file, wherein the first constraint file is used to replace the full name of the pin name, the full name of the trigger target name, and the full name of the delay signal name with the pin name, the trigger target name, and the delay signal name in the second interconnection path file.
[0059] When verifying the core function or extended function of a pin, there may be a delay in the interconnection path corresponding to the pin. At this time, the script determines whether there is a delay in the interconnection path corresponding to the pin based on the pin name. If there is a delay, the delay signal name and delay signal value corresponding to the pin name are obtained. Then the script constructs a second interconnection path file based on the pin name and the function keyword corresponding to the pin name, the trigger target name and the function keyword corresponding to the trigger target name, the delay signal name and the delay signal value. The following is an example of the code of the second interconnection path file of a core sub-function of a pin:
[0060] add_cc-src${PATH_PD0}.Y-dest${PATH_GPIOD}.GPIOIN[0]-path_delay2-clock${PATH_AHB_GPIO0_WRAPPER}.HCLK-name"PD0_Y_to_GPIOD_GPIOIN0".
[0061] Among them, -path_delay 2-clock is automatically added by the script program when constructing the second interconnection file, and is printed to the second interconnection path file through the print statement. 2 is the delay signal value, which can be pre-stored in the script program or manually modified. clock is automatically added by the script program when constructing the second interconnection file, and is printed to the second interconnection path file through the print statement.
[0062] ${PATH_AHB_GPIO0_WRAPPER}.HCLK is the name of the delay signal, which may be pre-stored in the script program, or obtained by the script program traversing the first constraint file. Further, the second interconnection path file and the first constraint file are input into the verification tool for verification.
[0063] If there is no delay in the interconnection path corresponding to the pin, there is no need for a delay signal name and a delay signal value; or the delay signal name and delay signal value can be added to all interconnection paths, in which case the delay signal value can be 0. When a delay exists in a certain interconnection path, the delay signal value can be manually modified. Furthermore, when there is a delay in the extended sub-function of the extended function of the pin, the construction logic of the respective second interconnection path is the same as the core sub-function, which will not be repeated here.
[0064] In the embodiment of the present application, when a delay is detected in the interconnection path corresponding to the pin, the script program obtains the pre-stored delay signal name and delay signal value. Subsequently, the script program uses the pin name, trigger target name, function keyword and detailed information of the delay signal to construct a second interconnection path file containing delay information. This method improves the accuracy of the verification process and ensures that the delay factor is correctly handled. At the same time, the second interconnection path file is verified by the compiler mode of the verification tool, which not only reduces the simulation time, but also further improves the verification efficiency.
[0065] In one embodiment of the present application, refer to the attached Figure 3 ,When verifying the core function of a pin, the core function includes multiple core sub-functions, each of which corresponds to an interconnection path; according to the pin name, the function keyword of the pin is determined through a script program, including:
[0066] S300, the control script program traverses the first constraint file to determine the starting keyword and the ending keyword of each core sub-function of the pin.
[0067] S310 , taking the starting point keyword and the ending point keyword of each core sub-function as function keywords in turn, and then constructing a first interconnection path file corresponding to each core sub-function.
[0068] When the user verifies the core functionality of a pin, the script reads the pin file (see Appendix Figure 4 Example of a pin file for a pin core function) with multiple pin names (see Appendix Figure 4 The core function of each pin includes multiple core sub-functions (refer to the attached Figure 5 Schematic diagram of the first constraint file for the core function of the pin of the example), and the multiple core sub-functions between each pin are the same. Figure 5The "Y" in IO_Y="Y" shown in the figure is the starting keyword corresponding to one of the core sub-functions, and the end keyword corresponding to the core sub-function is "GPIOIN" in GPIO_IN="GPIOIN". The starting keyword and end keyword of each core sub-function correspond to each other one by one. The following is an example of the core function of pin PD0 verified by the user:
[0069] The script traverses the pin file and obtains the pin name PD0. Based on the pin name PD0, the script determines the corresponding trigger target name GPIOD. Since each pin has multiple core sub-functions, it is necessary to verify the multiple core sub-functions corresponding to the pin name PD0 in turn. First, verify the interconnection path of the input function (the input function is a core sub-function) corresponding to the pin name PD0 (refer to the attached Figure 6 ), the script program traverses the first constraint file to determine the starting keyword Y corresponding to the pin name PD0, and determines the end keyword "GPIOIN" corresponding to the trigger target name GPIOD. The starting keyword Y and the end keyword GPIOIN constitute the function keyword. At the same time, the script program obtains the number of the pin in the group as [0] based on the pin name PD0. Further, according to the attached Figure 6 It can be known that there is still a delay in the interconnection path, and the delay signal name can be obtained from the script program or the first constraint file
[0070] ${PATH_AHB_GPIO0_WRAPPER}.HCLK, delay signal value (attached Figure 6 The delay signal value shown is 2) which can be pre-stored in the script program or manually modified. Further, according to the logic of constructing the interconnection path file described in the above embodiment, the first interconnection path file of the input function corresponding to the pin name PD0 can be obtained, and the code of the first interconnection path file is as follows:
[0071] add_cc-src${PATH_PD0}.Y-dest${PATH_GPIOD}.GPIOIN[0]-path_delay2-clock${PATH_AHB_GPIO0_WRAPPER}.HCLK-name"PD0_Y_to_GPIOD_GPIOIN0". Finally, the first interconnection path file and the first constraint file of the input function corresponding to the pin name PD0 are input into the verification tool for verification. After the verification is completed, the first interconnection path files of the remaining core sub-functions corresponding to the pin name PD0 are constructed in sequence, and the corresponding verification is performed until the first interconnection paths of all core sub-functions corresponding to the pin name PD0 are verified.
[0072] In one embodiment of the present application, refer to the attached Figure 7When verifying the extended function of a pin, the extended function includes multiple extended sub-functions, each of which corresponds to an interconnection path; according to the pin name, the function keyword of the pin is determined through a script program, including:
[0073] S700 , the control script program traverses the first constraint file to determine the starting keyword and the ending keyword of each extended sub-function of the pin.
[0074] S710: When there is no enable bit in the multiple extended sub-functions or the enable bit is empty, the start point keyword and the end point keyword of each extended sub-function are used as function keywords in turn to construct a first interconnection path file corresponding to each extended sub-function.
[0075] When the user verifies the core functionality of a pin, the script reads the pin file (see Appendix Figure 8 The pin names that the user wants to verify are traversed from the multiple pin names in the schematic diagram of the pin file for the pin extension function of the example. Each pin has at least one extended function, such as an additional Figure 8 Each extended function includes multiple extended sub-functions (refer to the attached Fig. 9 Schematic diagram of the first constraint file for pin extension function of the example), such as the attached Fig. 9 TIM3_CH4 in the example includes two extended sub-functions, namely input function and output function. Inout indicates that the extended function can be either input or output, ch4_in[0] and ch4_out are the starting keywords of the input function and the output function respectively, ch4-oe indicates the enable bit, and # indicates that the enable bit does not need to be verified. The following example takes the extended function TIM3_CH4 of the pin PC15 verified by the user as an example:
[0076] The script traverses the pin file to obtain the extended function TIM3_CH4 corresponding to pin PC15, and then determines the pin name TIM3. Based on the pin name TIM3, the script determines the corresponding trigger target name PC15. Since each extended function has multiple core sub-functions, it is necessary to verify the input function and output function corresponding to the pin name TIM3 in turn. First, verify the interconnection path of the output function corresponding to the pin name TIM3 (refer to the attached Fig.10 ), the script program traverses the first constraint file to determine the starting keyword ch4_out corresponding to the pin name TIM3, and determines the end keyword "A" corresponding to the trigger target name PC15 (the end keyword A is not in the attached Fig. 9As shown in FIG. 1 , the starting keyword ch4_out and the end keyword A constitute the function keyword. Further, according to the logic of constructing the interconnection path file described in the above embodiment, the first interconnection path file of the output function corresponding to the pin name TIM3 can be obtained, and the code of the first interconnection path file is as follows:
[0077] add_cc-src${PATH_TIM3}.ch4_out-dest${PATH_PC15}.A-enable
[0078] "{(($($PATH_GPIOC1.GPIOCK
[63] ===1)&&($($PATH_GPIOC1.GPIOAPR[63:60]===111)))"-name "TIM3_CH4_to_PC15_AF11".
[0079] Among them, -enable"{(($($PATH_GPIOC1.GPIOCK
[63] ==1)&&
[0080] ($($PATH_GPIOC1.GPIOAPR[63:60]==111))) is automatically generated by the script program and added to the first interconnection path file. Finally, the first interconnection path file and the first constraint file of the output function corresponding to the pin name TIM3 are input into the verification tool for verification. After the verification is completed, the first interconnection path files of the remaining core sub-functions corresponding to the pin name TIM3 are constructed in sequence, and the corresponding verification is performed until the first interconnection paths of all core sub-functions corresponding to the pin name TIM3 are verified.
[0081] In one embodiment of the present application, it also includes: when there is an enable bit in multiple extended sub-functions, the control script program traverses the first constraint file to determine the enable keyword corresponding to the pin; the enable keyword is added to the function keyword corresponding to each extended sub-function, and then the first interconnection path file corresponding to each extended sub-function is constructed.
[0082] When there are enable bits in multiple extended sub-functions of an extended function, the enable keyword corresponding to the extended sub-function needs to be added when constructing the interconnection path file corresponding to each extended sub-function. The following is still an example of the extended function TIM3_CH4 of the pin PC15 verified by the user:
[0083] After the script program obtains the pin name TIM3, the trigger target name PC15, the starting keyword ch4_out, and the end keyword A, if there is an enable bit in the extended sub-function corresponding to the pin name TIM3, the script program traverses the first constraint file for the pin extension function to obtain the corresponding enable keyword. Further according to the logic of constructing the interconnection path file described in the above embodiment, the script program constructs the first interconnection path file based on the pin name TIM3, the trigger target name PC15, the starting keyword ch4_out, the end keyword A, and the enable keyword, and sends the first interconnection path file to the verification tool for verification.
[0084] In one embodiment of the present application, it also includes: if there are other pins whose extended functions are consistent with the extended functions of the pins to be verified by the user, the pin names of the other pins are determined from the pin file through a script program; the script program is controlled to invert the pin names of the other pins, and the inverted pin names of the other pins, the pin names of the pins to be verified, the trigger target name and the function keyword are used to construct a first interconnection path file.
[0085] For example, the extended function of the pin PC15 verified by the user is TIM3_CH4. If the extended function of other pins also has TIM3_CH4, the script program continues to collect the pin names of other pins with TIM3_CH4 in the pin file after determining the verified pin name TIM3. Further, the script program inverts the pin names of other pins with TIM3_CH4, and then constructs the first interconnection path file with the inverted pin name, the verified pin name TIM3, the trigger target name PC15 and the function keyword.
[0086] In one embodiment of the present application, it also includes: when the extended function of the pin to be verified by the user is an output function, the script program does not perform a negation operation on the pin names of other pins; the control script program constructs a first interconnection path file using the pin names of other pins that are not negated, the pin name of the pin to be verified, the trigger target name and the function keyword.
[0087] The extended function includes multiple extended sub-functions, such as input function, output function, etc. When verifying the extended function of a pin, if there is an extended sub-function in the extended function that is an output function, then when constructing the first interconnection path file for the output function, it is not necessary to invert the pin names of other pins with the same extended function.
[0088] In one embodiment of the present application, the second constraint file and the third constraint file are configured, wherein the second constraint file includes a module in the chip that does not need to be verified for interconnection paths, and the third constraint file (see Attachment 1) includes a module in the chip that does not need to be verified for interconnection paths. Figure 6 and attached Fig.10The interconnection paths in the module are all controlled by the test signal (test mode) and are configured to fix the test signal of the pin to be verified by the user; the second constraint file and the third constraint file are input into the verification tool so that the verification tool does not perform verification operations on the module and the test signal.
[0089] In the embodiment of the present application, by configuring the second constraint file and the third constraint file, the efficiency and pertinence of the verification process can be significantly improved. The second constraint file clearly points out the modules in the chip that do not need to be verified for the interconnection path, so that the verification tool can skip these modules and avoid wasting time and computing resources on unnecessary parts. The third constraint file is used to fix the test signal of the pin to be verified by the user, simplifying the interconnection path file and speeding up the verification speed.
[0090] In one embodiment of the present application, the pin file includes test signal parameters of the pin to be verified by the user, the test signal parameters including the test signal name, the test signal default value and the test signal enable value, and also includes: determining the test signal parameters from the pin file through a script program according to the pin name; controlling the script program to add the test signal parameters to the first interconnection path file; when the script program recognizes that the test signal enable value is a first value, controlling the verification tool not to perform a verification operation on the test signal.
[0091] The user can also write the test signal parameters of the pin into the pin file, and can set the enable value of the test signal of the verification pin to the second value, and the enable value of not verifying the test signal to the first value. Thus, the script program traverses the pin file based on the pin name to obtain the test signal parameters of the pin to be verified. Further, the script program can construct a first interconnection path file based on the pin name, trigger target name, function keyword and test signal parameter. When the test signal enable value is the first value, the verification tool does not need to perform a verification operation on the test signal; when the test signal enable value is the second value, the verification tool can only perform a verification operation on the test signal.
[0092] In one embodiment of the present application, the first constraint file, the second constraint file, the third constraint file, the first interconnection path file, and the second interconnection path file may be files in .tcl or .csv format.
[0093] In one embodiment of the present application, a coverage collection instruction can be added to the interconnection path file so that the verification tool can verify the coverage of the code in the interconnection path file while verifying the interconnection path file. Wherein, the coverage of the code includes but is not limited to line coverage (Line Coverage), conditional coverage (ConditionalCoverage), toggle coverage (Toggle Coverage), branch coverage (Branch Coverage), etc. And similar to the above embodiment, the coverage collection instruction of the embodiment of the present application can be pre-set in the script program, or it can be stored in the pin file, and then read from the pin file by the script program.
[0094] The embodiment of the present application adds coverage collection instructions in the interconnection path file, thereby realizing that while the verification tool verifies the interconnection path file, the coverage of the code is verified, including line coverage, condition coverage, flip coverage, and branch coverage, etc. This method not only improves the efficiency of the verification process, but also enhances the comprehensiveness and accuracy of code testing, ensuring software quality and reliability. At the same time, the coverage collection instructions can be flexibly preset inside the script program or stored in the pin file, which is convenient for the script program to read and apply, and optimizes the verification process. In addition, in the embodiment of the present application, the process of generating the interconnection path file through the script program and verifying it through the verification tool, for different interconnection path files, the similarity of the coverage verification results is greater than the threshold, so there is no need to repeatedly add verification programs for different interconnection path files, saving labor costs.
[0095] The embodiment of the present application also provides a verification system for verifying the interconnection path in a chip, including: an identification module, configured to determine the pin name from the pin file through a script program according to the core function or extended function of the pin to be verified by the user; the identification module is also configured to determine the trigger target name and the function keyword of the pin through the script program according to the pin name; a construction module is configured to control the script program to construct a first interconnection path file based on the pin name, the trigger target name and the function keyword when the script program determines that there is no delay in the interconnection path corresponding to the pin based on the pin name; the verification module is configured to input the first interconnection path file and the first constraint file inside the script program into a verification tool, and control the verification tool to verify the first interconnection path file, wherein the first constraint file is used to replace the full name of the pin and the full name of the trigger target name with the pin name and the trigger target name in the first interconnection path file.
[0096] The details of the embodiments of the present application have been described above and will not be repeated here.
[0097] It should be noted that the above embodiments can be freely combined as needed. The above are only preferred embodiments of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.
Claims
1. A verification method for verifying an interconnection path in a chip, characterized in that: include: According to the core function or extended function of the pin to be verified by the user, the pin name is determined from the pin file through the script program; According to the pin name, determining the trigger target name and the function keyword of the pin through the script program; When the script program determines that there is no delay in the interconnection path corresponding to the pin based on the pin name, controlling the script program to construct a first interconnection path file based on the pin name, the trigger target name and the function keyword; The first interconnection path file and the first constraint file inside the script program are input into a verification tool, and the verification tool is controlled to verify the first interconnection path file, wherein the first constraint file is used to replace the full name of the pin name and the full name of the trigger target name with the pin name and the trigger target name in the first interconnection path file.
2. The verification method according to claim 1, characterized in that: Also includes: When the script program determines that there is a delay in the interconnection path corresponding to the pin based on the pin name, obtaining a delay signal name and a delay signal value pre-stored in the script program; Based on the pin name, the trigger target name, the function keyword, the delay signal name and the delay signal value, constructing a second interconnection path file through the script program; The second interconnection path file and the first constraint file are input into a verification tool so that the verification tool verifies the second interconnection path file, wherein the first constraint file is used to replace the full name of the pin name, the full name of the trigger target name, and the full name of the delay signal name with the pin name, the trigger target name, and the delay signal name in the second interconnection path file.
3. The verification method according to claim 1, characterized in that: When verifying the core function of the pin, the core function includes multiple core sub-functions, each of which corresponds to an interconnection path; determining the function keyword of the pin through the script program according to the pin name specifically includes: Controlling the script program to traverse the first constraint file to determine the starting keyword and the ending keyword of each core sub-function of the pin; The starting point keyword and the end point keyword of each core sub-function are sequentially used as the function keyword to construct the first interconnection path file corresponding to each core sub-function.
4. The verification method according to claim 1, characterized in that: When verifying the extended function of the pin, the extended function includes a plurality of extended sub-functions, each of which corresponds to an interconnection path; determining the function keyword of the pin through the script program according to the pin name specifically includes: Controlling the script program to traverse the first constraint file to determine a starting keyword and an end keyword for each extended sub-function of the pin; When there is no enable bit or the enable bit is empty in the plurality of extended sub-functions, the start point keyword and the end point keyword of each extended sub-function are sequentially used as the function keyword to construct the first interconnection path file corresponding to each extended sub-function.
5. The verification method according to claim 4, characterized in that: Also includes: When there is an enable bit in the plurality of extended sub-functions, controlling the script program to traverse the first constraint file to determine an enable keyword corresponding to the pin; The enable keyword is added to the function keyword corresponding to each of the extended sub-functions, thereby constructing the first interconnection path file corresponding to each of the extended sub-functions.
6. The verification method according to claim 4 or 5, characterized in that: Also includes: If the extended function of other pins is consistent with the extended function of the pin to be verified by the user, determine the pin names of the other pins from the pin file through the script program; The script program is controlled to invert the pin names of the other pins, and the inverted pin names of the other pins, the pin name of the pin to be verified, the trigger target name and the function keyword are used to construct the first interconnection path file.
7. The verification method according to claim 6, characterized in that: Also includes: When the extended function of the pin to be verified by the user is an output function, the script program does not perform a negation operation on the pin names of the other pins; The script program is controlled to construct the first interconnection path file by using the pin names of the other pins that are not inverted, the pin name of the pin to be verified, the trigger target name, and the function keyword.
8. The verification method according to claim 1, characterized in that: Also includes: Configure a second constraint file and a third constraint file, wherein the second constraint file includes modules in the chip that do not require interconnection path verification, and the third constraint file is configured to fix the test signal of the pin to be verified by the user; The second constraint file and the third constraint file are input into the verification tool, so that the verification tool does not perform verification operations on the module and the test signal.
9. The verification method according to claim 1, characterized in that: The pin file includes the test signal parameters of the pin to be verified by the user, the test signal parameters including the test signal name, the test signal default value and the test signal enable value, and also includes: According to the pin name, determining the test signal parameter from the pin file through the script program; Controlling the script program to add the test signal parameter to the first interconnection path file; When the script program identifies that the test signal enable value is a first value, the verification tool is controlled not to perform a verification operation on the test signal.
10. A verification system for verifying interconnection paths in a chip, characterized in that: include: The identification module is configured to determine the pin name from the pin file through a script program according to the core function or extended function of the pin to be verified by the user; The identification module is further configured to determine the trigger target name and the function keyword of the pin through the script program according to the pin name; A construction module is configured to control the script program to construct a first interconnection path file based on the pin name, the trigger target name and the function keyword when the script program determines that there is no delay in the interconnection path corresponding to the pin based on the pin name; A verification module is configured to input the first interconnection path file and the first constraint file inside the script program into a verification tool, and control the verification tool to verify the first interconnection path file, wherein the first constraint file is used to replace the full name of the pin name and the full name of the trigger target name with the pin name and the trigger target name in the first interconnection path file.