Chip packaging structure and manufacturing method thereof
By using temporary bonding carrier plate, copper frame and copper block in the chip packaging structure, flip the chip and plastic sealing and line connection, the problem of insufficient stability and current carrying capacity of the chip packaging structure in the prior art is solved, and higher packaging stability and heat dissipation capabilities are achieved.
Patent Information
- Application Number
- CN202411773597.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-04
- Publication Date
- 2025-03-21
AI Technical Summary
The existing chip packaging structures are susceptible to wire diameter limitations, have poor current carrying capacity, and it is difficult to effectively interconnect the pins on the front and back of the chip during packaging.
A method of making a chip package structure is adopted, including providing a temporary bonding carrier plate, fixing a copper frame and copper block, flip the chip and fixing it through silver glue, plastic sealing and removing the carrier plate, processing the surface of the package to expose the pins, and making the first and second line copper layers to achieve circuit connection of the pins.
It improves the stability and current carrying capacity of the chip package, reduces product stress, avoids product failure caused by stress, and improves the heat dissipation ability of the chip.
Smart Images
Figure CN119673781A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of packaging technology, and in particular to a chip packaging structure and a manufacturing method thereof. Background Art
[0002] With the continuous advancement of semiconductor packaging technology, the requirements for packaging substrates are becoming higher and higher. The purpose of chip packaging is to provide the chip with appropriate signal paths, thermal paths, and structural protection. Existing chip packaging is usually interconnected through wire bonding structures, which are easily limited by wire diameters and have poor current carrying capacity. Summary of the invention
[0003] The present application proposes a chip packaging structure and a manufacturing method thereof to solve the problem of interconnecting the front pins and the back pins of the chip and improve the stability of the chip packaging.
[0004] In order to solve the above technical problems, the present application provides a method for manufacturing a chip packaging structure, wherein the manufacturing method comprises: providing a temporary bonding carrier; fixing a copper frame with a hollow area on the temporary bonding carrier; placing a copper block in the hollow area of the copper frame to facilitate the subsequent thinning of the thickness of the plastic sealing medium on the front side of the chip; placing the front side of the chip on the copper block in a direction away from the copper block to obtain a body to be packaged; plastic-sealing the body to be packaged, and removing the temporary bonding carrier to obtain a plastic-sealed body; wherein the front side of the plastic-sealed body is oriented in the same direction as the front side of the chip. The back of the plastic package body faces opposite to the front of the chip; the front of the plastic package body is processed to expose the pins on the front of the chip and the copper frame; a first circuit copper layer is made on the front of the plastic package body to connect the pins on the front of the chip with the copper frame through the first circuit copper layer; an insulating buffer layer is pressed on the front and back of the plastic package body; the insulating buffer layer on the back of the plastic package body is drilled to expose the copper block and the copper frame; a second circuit copper layer is made on the surface of the buffer insulating layer on the back of the plastic package body to obtain the chip packaging structure.
[0005] Among them, the step of processing the front side of the plastic package to expose the pins on the front side of the chip and the side surface of the copper frame includes: performing laser drilling processing on the front side of the plastic package to expose the pins on the front side of the chip and the side surface of the copper frame.
[0006] Among them, the step of processing the front side of the plastic package to expose the pins on the front side of the chip and the side surface of the copper frame includes: grinding the front side of the plastic package to expose the pins on the front side of the chip and the side surface of the copper frame.
[0007] Wherein, the temporary bonding carrier is sticky and is used to fix the copper frame and the copper block.
[0008] The step of placing the chip on the copper block with the front side of the chip facing away from the copper block to obtain the packaged body also includes: fixing the chip on the copper block with silver glue to facilitate packaging.
[0009] The bottom area of the copper block is larger than the bottom area of the chip; and the distance between the edge of the copper block and the edge of the chip is larger than 100 microns.
[0010] Among them, the step of making a first circuit copper layer on the front side of the plastic package body to connect the pins on the front side of the chip to the copper frame through the first circuit copper layer includes: depositing a thin layer of copper on the front side of the plastic package body by sputtering or chemical deposition process; electroplating the first copper layer on the surface of the thin copper by electroplating process; and etching the first copper layer by pattern etching process to obtain the first circuit copper layer.
[0011] Among them, the step of making a second circuit copper layer on the surface of the buffer insulation layer on the back of the plastic package body includes: depositing a thin layer of copper on the surface of the buffer insulation layer using a sputtering or chemical deposition process; electroplating a second copper layer on the thin copper surface using an electroplating process; and etching the second copper layer using a graphic etching process to obtain the second circuit copper layer.
[0012] Wherein, after the step of manufacturing the second circuit copper layer on the surface of the buffer insulation layer on the back of the plastic package body, the method further includes: performing protective treatment on the surface of the second circuit copper layer to prevent oxidation of the second circuit copper layer.
[0013] In order to solve the above technical problems, the present application also provides a chip packaging structure, which includes: a packaging body, including a copper frame with a hollow area, a copper block and a chip arranged in the hollow area, and a packaging layer encapsulating the chip, the copper sheet and the copper frame; wherein the packaging body includes a front side and a back side, the front side of the packaging body is in the same direction as the front side of the chip, and the back side of the packaging body is in the opposite direction to the front side of the chip; a first circuit copper layer is arranged on the front side of the packaging body, and the copper frame is circuit-connected to the pins on the front side of the chip through a plurality of vias on the front side of the packaging body; an insulating buffer layer is arranged on the surface of the first circuit copper layer and the back side of the packaging body; a second circuit copper layer is arranged on the surface of the insulating buffer layer on the back side of the packaging body, and the copper frame is circuit-connected to the pins on the back side of the chip through a plurality of vias in the insulating buffer layer, thereby realizing the interconnection between the pins on the front side of the chip and the pins on the back side of the chip.
[0014] The beneficial effects of the present application are: first, the chip is flipped onto a temporary bonding carrier, and then the copper block is attached to the back of the chip through silver glue to prevent the laser from damaging the chip when drilling holes on the back of the chip. The copper block supports and protects the chip, thereby improving the product yield. The copper block is used to raise the chip, reduce the thickness of the dielectric above the chip and the diameter of the blind hole, which is conducive to reducing product stress and avoiding product failure caused by stress. In addition, the chip is in direct contact with the copper block, which greatly improves the heat dissipation capacity of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0016] Figure 1 A schematic diagram of a process flow of an embodiment of a method for manufacturing a chip packaging structure of the present application;
[0017] Figure 2 for Figure 1 A schematic diagram of the structure of an embodiment in step S12;
[0018] Figure 3 for Figure 1 A schematic diagram of the structure of an embodiment in step S13;
[0019] Figure 4 for Figure 1 A schematic diagram of the structure of an embodiment of step S14;
[0020] Figure 5 for Figure 1 A schematic diagram of the structure of an embodiment of step S15;
[0021] Figure 6 for Figure 1 A schematic diagram of the structure of an embodiment of step S16;
[0022] Figure 7 for Figure 1 A schematic diagram of the structure of an embodiment of step S17;
[0023] Figure 8 for Figure 1 A schematic diagram of the structure of an embodiment of step S18;
[0024] Fig. 9 for Figure 1 A schematic diagram of the structure of an embodiment of step S19;
[0025] Fig.10 for Figure 1 A schematic diagram of the structure of an embodiment of step S20;
[0026] Fig.11 for Figure 1 A schematic diagram of the structure of another embodiment of step S20;
[0027] Fig.12 This is a schematic structural diagram of an embodiment of a chip packaging structure of the present application. DETAILED DESCRIPTION
[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0029] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "said", and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless otherwise clearly indicated above, and "multiple" generally includes at least two, but does not exclude the inclusion of at least one.
[0030] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.
[0031] It should be understood that the terms "include", "comprises" or any other variations used herein are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "includes..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.
[0032] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.
[0033] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The presence of the phrase at each location in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.
[0034] This application provides a method for manufacturing a chip packaging structure. Figure 1 , Figure 1 FIG. 1 is a flow chart of an embodiment of a method for manufacturing a chip packaging structure of the present application. Figure 1 As shown, the manufacturing method of the chip packaging structure includes:
[0035] Step S11: providing a temporary bonding carrier.
[0036] The temporary bonding carrier is sticky and is used to carry and fix the components set on its surface. The temporary bonding carrier is formed by coating the surface of the carrier with a temporary bonding material, which is an intermediate layer material used in the semiconductor manufacturing process, mainly used to bond the chip and the temporary carrier together.
[0037] Step S12: Fixing the copper frame with the hollow area on the temporary bonding carrier.
[0038] The copper frame is a hollow frame structure etched from the entire copper plate, which is usually used for positioning when attaching chips. The area of the hollow area of the copper frame is larger than the bottom area of the copper block and the chip. The copper frame is vertically set on the temporary bonding carrier.
[0039] For details, please refer to Figure 2 , Figure 2 for Figure 1 A schematic diagram of the structure of an embodiment in step S12. Figure 2 As shown, a copper frame 12 is fixed on the temporary bonding carrier 11. The copper frame 12 has a certain height, and the height of the copper frame 12 is preferably 200um-250um.
[0040] Step S13: placing a copper block in the hollow area of the copper frame.
[0041] The copper block is bonded to the temporary bonding carrier in the hollow area to fix the copper block through the temporary bonding carrier. The copper block has a certain hardness and can support and fix the chip.
[0042] For details, please refer to Figure 3 , Figure 3 for Figure 1 A schematic diagram of the structure of an embodiment in step S13. Figure 3As shown, the copper block 13 is fixed on the temporary bonding carrier 11 in the hollow area and is spaced apart from the copper frame 12 .
[0043] Step S14: placing the chip on the copper block with the front side facing away from the copper block to obtain a packaged body.
[0044] The front side of the chip is arranged in a direction away from the copper block, that is, the chip is placed forward on the copper block. The back side of the chip is fixedly connected to the copper block. The front side of the chip has pins, and the pins on the back side of the chip are connected to the copper block.
[0045] This step can effectively reduce the thickness of the plastic encapsulation medium on the front of the chip when the chip is subsequently plastic encapsulated. In other embodiments, the height of the copper frame 12 is higher than the chip 14, so the copper block 13 can be used to raise the chip 14, thereby reducing the height difference between the front of the chip 14 and the copper frame 12, and reducing the thickness of the plastic encapsulation medium covering the surface of the chip 14. The plastic encapsulation medium thickness refers to the thickness of the plastic encapsulation medium layer covering the surface of the chip 14.
[0046] This step includes: using silver glue to fix the chip on the copper block, so as to facilitate the subsequent packaging of the chip and avoid displacement of the copper block and the chip during the packaging process.
[0047] The bottom area of the copper block is greater than or equal to the bottom area of the chip. Preferably, the distance between the edge of the bottom surface of the copper block and the edge of the bottom surface of the chip is greater than 100 microns, that is, the four sides of the copper block are greater than 100um larger than the chip, so that the silver glue has enough overflow range. By pasting the copper block and the silver glue in contact with the chip, the back of the chip contacts the large area of the copper block, thereby greatly improving the heat dissipation capacity of the chip.
[0048] For details, please read Figure 4 , Figure 4 for Figure 1 The structural diagram of the embodiment of step S14 is shown below. Figure 4 As shown, the chip 14 is fixed on the copper block 13. Preferably, the chip 14 is centrally arranged on the copper block 13, and the edge of the chip 14 is arranged away from the edge of the copper block 13, and the edge spacing is greater than 100 microns.
[0049] Step S15: plastic-encapsulate the package body and remove the temporary bonding carrier to obtain a plastic-encapsulated body.
[0050] The hollow area in the packaged body is filled with a plastic encapsulation medium.
[0051] Specifically, the method includes: pressing a plastic encapsulation medium on the surface of a temporary bonding carrier so that the plastic encapsulation medium is filled in the encapsulation body to encapsulate the chip.
[0052] The plastic package body includes a front side and a back side. The front side of the plastic package body faces the same direction as the front side of the chip, and the back side of the plastic package body faces the opposite direction to the front side of the chip.
[0053] Please refer to Figure 5 , Figure 5 for Figure 1 The structural diagram of the embodiment of step S15 is shown below. Figure 5 As shown, the plastic package body 100 includes a copper frame 12 , a copper block 13 , a chip 14 , and a plastic package dielectric layer 10 filling gaps between the copper frame 12 , the copper block 13 and the chip 14 .
[0054] Step S16: Process the front side of the plastic package to expose the pins and copper frame on the front side of the chip.
[0055] Specifically, multiple vias are made on the front of the plastic package, and copper is plated inside the vias to form blind holes, connecting the copper layer on the surface of the plastic package with the chip pins inside the plastic package. It should be noted that blind holes are conductive holes that connect the surface layer and the inner layer without penetrating the entire board, and are used to connect the surface layer circuit and the inner layer circuit below.
[0056] In one embodiment, the front side of the plastic package is laser drilled to expose the pins on the front side of the chip and one side surface of the copper frame. It should be noted that the structure supports the chip through the copper block, which reduces the dielectric thickness of the plastic package layer above the chip. According to the calculation of the laser drilling thickness-diameter ratio, the thinner dielectric thickness can achieve smaller blind holes, thereby achieving high-density chip packaging.
[0057] In another embodiment, the front side of the plastic package is ground to expose the pins on the front side of the chip and one side surface of the copper frame. Specifically, the plastic layer of the plastic package is ground, and the plastic layer refers to the part located above the chip. The chip is supported by a copper block so that the chip is higher than the copper frame, reducing the thickness of the plastic layer located above the chip, so that the pins of the chip can be exposed by grinding, and the circuit layer is directly in contact with the chip pins, which greatly improves the current carrying capacity of the chip and realizes high current carrying chip packaging. In this embodiment, the plastic layer above the front side of the chip is ground, and the plastic layer above the copper frame is drilled by laser drilling.
[0058] Please refer to Figure 6 , Figure 6 for Figure 1 The structural diagram of the embodiment of step S16 is shown below. Figure 6 As shown, a plurality of openings are drilled on the front side of the plastic package body 100 to expose a side surface of the copper block 13 in the inner layer of the plastic package body 100 and a pin surface on the front side of the chip 14 .
[0059] Step S17: a first circuit copper layer is formed on the front side of the plastic package body, so as to connect the pins on the front side of the chip with the copper frame through the first circuit copper layer.
[0060] This step specifically includes: using sputtering or chemical deposition process to deposit a thin layer of copper on the front of the plastic package. The thin copper is also a conductive seed layer, which adheres to the surface of the plastic package medium and the inside of the hole. Then, the first copper layer is electroplated on the surface of the thin copper by using the electroplating process. The thin copper is electroplated to a certain thickness by using the electroplating process, and the blind hole is metalized. Then, the first copper layer is pattern-etched by using the graphic etching process to obtain the first circuit copper layer. The graphic etching process specifically includes photolithography-development-etching, and the copper layer on the front of the plastic package is etched into a circuit pattern by the above method.
[0061] Please refer to Figure 7 , Figure 7 for Figure 1 The structural diagram of the embodiment of step S17 is shown below. Figure 7 As shown, the first circuit copper layer 21 is arranged on the front side of the plastic package 100 and connected to the copper frame 12 inside the plastic package 100 and the pins of the chip 14 through blind holes, so that the pins on the front side of the chip 14 are led out to the back side of the chip through the copper frame 12.
[0062] Step S18: Laminating an insulating buffer layer on the front and back sides of the plastic package body.
[0063] The first circuit copper layer is encapsulated by the insulating buffer layer, so that the first circuit copper layer is buried in the plastic packaging structure, thereby protecting the first circuit copper layer.
[0064] The insulating buffer layer may include FR4, PP, and PI. By laminating an insulating buffer layer on the front and back of the plastic package, the rigidity of the product structure can be increased and the welding stress can be buffered.
[0065] Please refer to Figure 8 , Figure 8 for Figure 1 The structural diagram of the embodiment of step S18 is shown below. Figure 8 As shown, the insulating buffer layer 200 is arranged on the front side of the plastic package 100 and the back side of the plastic package 100. The insulating buffer layer 200 arranged on the front side of the plastic package 100 covers the surface of the first circuit copper layer 21 to protect the first circuit copper layer 21. The insulating buffer layer 200 arranged on the back side of the plastic package 100 covers the copper block 13 and the copper frame 12.
[0066] Step S19: drilling holes in the insulating buffer layer on the back of the plastic package to expose the copper block and the copper frame.
[0067] Specifically, a laser is used to drill holes on the back side of the plastic package until the holes reach the copper block, thereby achieving conduction on the back side of the chip.
[0068] Please refer to Fig. 9 , Fig. 9 for Figure 1 The structural diagram of the embodiment of step S19 is shown below. Fig. 9 As shown, a via hole is provided on the insulating buffer layer 200 disposed on the back side of the plastic package body 100 to expose the other side of the copper frame 12 and the copper block 13 through the via hole.
[0069] Step S20: forming a second circuit copper layer on the surface of the buffer insulation layer on the back of the plastic package body to obtain a chip packaging structure.
[0070] Specifically, the second circuit copper layer connects the pins on the back side of the chip to the copper frame circuit, thereby realizing circuit interconnection between the pins on the back side of the chip and the pins on the front side of the chip.
[0071] This step specifically includes: depositing a thin copper layer on the surface of the buffer insulation layer by sputtering or chemical deposition process. The thin film is a conductive seed layer. Electroplating a second copper layer on the thin copper surface by electroplating process. Etching the second copper layer by pattern etching process to obtain a second circuit copper layer. The pattern etching process specifically includes photolithography-development-etching. The manufacturing process of the second circuit copper layer is the same as the manufacturing process of the first circuit copper layer.
[0072] Please refer to Fig.10 , Fig.10 for Figure 1 The structural diagram of the embodiment of step S20 is shown below. Fig.10 As shown, the second circuit copper layer 22 is disposed on the surface of the insulating buffer layer 200 on the back side of the plastic package 100 and is connected to the copper frame 12 and the copper block 13 through blind holes.
[0073] After step S20, the method further includes: performing protective treatment on the surface of the second circuit copper layer to prevent oxidation of the second circuit copper layer and improve the solderability of the pad. At least part of the second circuit copper layer is a pad for soldering with other components (such as a PCB board).
[0074] Please refer to Fig.11 , Fig.11 for Figure 1 A schematic diagram of the structure of another embodiment of step S20. Fig.11 As shown, a protective layer 23 is also provided on the surface of the second copper circuit layer 22, and the protective layer 23 is used to protect the second copper circuit layer 22. The first copper circuit layer 21 and the second copper circuit layer 22 are connected through the copper frame 12.
[0075] After step S20, the process further includes: cutting the finished product to obtain multiple single products. Specifically, the above operation steps are suitable for batch packaging of chips to obtain multiple chip packaging structures with pins located on the same side, and then cutting the finished product into single products by a cutting machine.
[0076] The beneficial effects of the present application are as follows: first, the chip is first flipped onto a temporary bonding carrier, and then the copper block is attached to the back of the chip through silver glue to prevent the laser from damaging the chip when drilling holes on the back of the chip. The copper block supports and protects the chip, thereby improving the product yield. Second, by padding the chip with the copper block, it is beneficial to make smaller blind holes when drilling holes on the front of the chip with the laser, which is beneficial to achieve high-sealing packaging of the chip; in addition, it is also beneficial to expose the chip through grinding technology, thereby facilitating the direct production of the circuit copper layer on the chip surface, omitting the blind holes, and facilitating the packaging of high-current-carrying chips. By padding the chip with the copper block, the thickness of the dielectric above the chip and the aperture of the blind holes are reduced, which is beneficial to reduce product stress and avoid product failure caused by stress. Third, the chip is in direct contact with the copper block, which greatly improves the heat dissipation capacity of the chip.
[0077] The present application also provides a chip packaging structure, which is manufactured by any of the manufacturing methods in the above embodiments. For the specific structure, please refer to 12. Fig.12 This is a schematic diagram of the structure of an embodiment of the chip packaging structure of the present application. Fig.12 As shown, the chip packaging structure includes: a plastic package 100. The plastic package 100 includes a copper frame 12 with a hollow area, a copper block 13 arranged in the hollow area, a chip 14 arranged on the surface of the copper block 13, and a packaging layer encapsulating the chip 14, the copper block 13 and the copper frame 12. The plastic package 100 includes a front side 101 and a back side 102. The front side 101 of the plastic package 101 faces the same direction as the front side of the chip 14, and the back side 102 faces the opposite direction to the front side of the chip 14.
[0078] The first circuit copper layer 21 is disposed on the front side 101 of the plastic package 100 , and the copper frame 12 is connected to the pins on the front side of the chip 14 through a plurality of via holes on the front side of the plastic package 100 for circuit connection.
[0079] The insulating buffer layer 200 is disposed on the surface of the first circuit copper layer 21 and the back side of the plastic package body 100 .
[0080] The second circuit copper layer 22 is arranged on the surface of the insulating buffer layer 200 on the back of the plastic package 100, and the copper frame 12 is connected to the copper block 13 through a plurality of blind holes in the insulating buffer layer 200, and then connected to the back pin circuit of the chip 14 through the copper block 13, so that the front pin and the back pin of the chip 14 are both led to the back of the plastic package 100, and the front pin and the back pin of the chip 14 are interconnected through the second circuit copper layer 22. Among them, the exposed second circuit copper layer 22 is a pad layer, which is used to be electrically connected to an external circuit. A protective layer 23 is also provided on the pad layer to protect the pad.
[0081] In this embodiment, the copper block is used to raise the chip, which is beneficial to the circuit processing on the front and back sides of the chip, avoids damage to the chip during the processing, and improves the heat dissipation capacity of the chip.
[0082] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. A method for manufacturing a chip packaging structure, characterized in that: The production method comprises: Provide temporary bonding carrier; Fixing the copper frame with the hollow area on the temporary bonding carrier; Placing a copper block in the hollow area of the copper frame to facilitate subsequent thinning of the thickness of the plastic sealing medium on the front side of the chip; Placing the chip on the copper block with the front side of the chip facing away from the copper block to obtain a packaged body; Plastic-sealing the body to be packaged, and removing the temporary bonding carrier to obtain a plastic-sealed body; wherein the front side of the plastic-sealed body faces the same direction as the front side of the chip, and the back side of the plastic-sealed body faces the opposite direction to the front side of the chip; Processing the front side of the plastic package to expose the pins on the front side of the chip and the copper frame; A first circuit copper layer is formed on the front side of the plastic package body, so as to connect the pins on the front side of the chip with the copper frame through the first circuit copper layer; Laminating an insulating buffer layer on the front and back sides of the plastic package body; Drilling the insulating buffer layer on the back of the plastic package body to expose the copper block and the copper frame; A second circuit copper layer is produced on the surface of the buffer insulation layer on the back side of the plastic package body to obtain the chip packaging structure.
2. The method for manufacturing a chip packaging structure according to claim 1, characterized in that: The step of processing the front side of the plastic package to expose the pins on the front side of the chip and one side surface of the copper frame includes: Laser drilling is performed on the front side of the plastic package to expose the pins on the front side of the chip and one side surface of the copper frame.
3. The method for manufacturing a chip packaging structure according to claim 1, characterized in that: The step of processing the front side of the plastic package to expose the pins on the front side of the chip and one side surface of the copper frame includes: The front side of the plastic package is ground to expose the pins on the front side of the chip and one side surface of the copper frame.
4. The method for manufacturing a chip packaging structure according to claim 1, characterized in that: The temporary bonding carrier is adhesive and is used to fix the copper frame and the copper block.
5. The method for manufacturing a chip packaging structure according to claim 1, characterized in that: The step of placing the chip on the copper block with the front side of the chip facing away from the copper block to obtain the packaged body further includes: The chip is fixed on the copper block by using silver glue to facilitate packaging.
6. The method for manufacturing a chip packaging structure according to claim 5, characterized in that: The bottom area of the copper block is larger than the bottom area of the chip; the distance between the edge of the copper block and the edge of the chip is larger than 100 microns.
7. The method for manufacturing a chip packaging structure according to claim 1, characterized in that: The step of manufacturing a first circuit copper layer on the front side of the plastic package body so as to connect the pins on the front side of the chip to the copper frame through the first circuit copper layer includes: Depositing a thin layer of copper on the front side of the plastic package body by sputtering or chemical deposition process; Electroplating a first copper layer on the surface of the thin copper using an electroplating process; The first copper layer is pattern-etched using a pattern etching process to obtain the first circuit copper layer.
8. The method for manufacturing a chip packaging structure according to claim 1, characterized in that: The step of manufacturing a second circuit copper layer on the surface of the buffer insulation layer on the back of the plastic package body comprises: Depositing a thin layer of copper on the surface of the buffer insulating layer by sputtering or chemical deposition process; Electroplating a second copper layer on the surface of the thin copper using an electroplating process; The second copper layer is pattern-etched by a pattern etching process to obtain the second circuit copper layer.
9. The method for manufacturing a chip packaging structure according to claim 1, characterized in that: After the step of forming a second circuit copper layer on the surface of the buffer insulation layer on the back of the plastic package body, the method further includes: A protective treatment is performed on the surface of the second circuit copper layer to prevent the second circuit copper layer from being oxidized.
10. A chip packaging structure, characterized in that: The chip packaging structure comprises: A plastic package body, comprising a copper frame with a hollow area, a copper block arranged in the hollow area, a chip arranged on the surface of the copper block, and a packaging layer encapsulating the chip, the copper sheet and the copper frame; wherein the plastic package body comprises a front side and a back side, the front side of the plastic package body faces the same direction as the front side of the chip, and the back side of the plastic package body faces the opposite direction to the front side of the chip; A first circuit copper layer is arranged on the front side of the plastic package body, and the copper frame is connected to the pins on the front side of the chip by circuit through a plurality of via holes on the front side of the plastic package body; An insulating buffer layer is arranged on the surface of the first circuit copper layer and the back side of the plastic package body; The second circuit copper layer is arranged on the surface of the insulating buffer layer on the back of the plastic package body, and the copper frame is circuit-connected with the pins on the back of the chip through multiple vias of the insulating buffer layer, thereby realizing the interconnection between the pins on the front of the chip and the pins on the back of the chip.