Multi-FPGA global clock synchronization device and method

Abstract

The invention relates to the technical field of integrated circuits, and discloses a multi-FPGA global clock synchronization device and method, and the device comprises an inter-board clock synchronization circuit and an in-board clock synchronization circuit. The inter-board clock synchronization circuit comprises an inter-board clock expansion circuit and an inter-board feedback clock circuit, the input end of the inter-board clock expansion circuit is connected with an external clock and a crystal oscillator signal, and the inter-board feedback clock circuit is connected between the output end and the input end of the inter-board clock expansion circuit; the in-board clock synchronization circuit comprises an in-board clock expansion circuit and an in-board feedback clock circuit, the input end of the in-board clock expansion circuit is connected with a clock signal output by the inter-board clock synchronization circuit, and the in-board feedback clock circuit is connected between the output end and the input end of the in-board clock expansion circuit; the output end of the in-board clock expansion circuit is connected with the internal logic module. Through an inter-board / internal clock expansion circuit and a dynamic feedback compensation mechanism, clock skew between board levels and boards is eliminated, and clock synchronization of a large-scale prototype verification system is supported.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit and hardware system design, and specifically to a global clock synchronization system and method for a multi-FPGA (field programmable gate array) system, which is particularly suitable for large-scale FPGA prototype verification platforms, distributed computing systems, and high-precision data acquisition systems. Background Art

[0002] Amid fierce competition in the integrated circuit industry, the focus of chip R&D has expanded beyond the design phase to include verification, which is becoming a critical factor in determining project success or failure. Compared to traditional software simulation verification methods, multi-FPGA-based prototyping technology has become the preferred solution for industry verification teams due to its reconfigurability, ability to simulate hardware behavior, and high verification speed.

[0003] When building large-scale, complex SoC prototyping systems, clock synchronization is always a primary challenge. This system requires precise and synchronized distribution of global clock and reset signals to each FPGA node, a prerequisite for ensuring functional correctness and timing closure. As SoC designs scale beyond the 10-billion-gate mark, the resources of a single FPGA are no longer sufficient to handle the complete design verification task. Designs must be partitioned into multiple submodules and distributed across multiple FPGAs for coordinated operation. During this process, clock synchronization becomes a key bottleneck limiting system performance. Because the clock generation modules (such as PLLs and MMCMs) within each FPGA are physically dispersed, PCB routing variations inevitably introduce clock skew, leading to hold time violations in inter-FPGA timing paths. As SoC design scale continues to grow, the accuracy, reliability, and scalability of the prototyping system's global clock and reset synchronization solution become even higher, necessitating innovative technical architectures to address this challenge.

[0004] Patent application CN220367554U discloses a clock synchronization device for a stacked FPGA prototype verification board, comprising: a first field programmable gate array (FPGA) chip and a second FPGA chip electrically connected to the first FPGA chip; a first clock management unit and a second clock management unit are provided in the first FPGA chip; a third clock management unit is provided in the second FPGA chip; a system clock signal is input into the first and second clock management units, the first clock management unit generates a first clock signal, which is respectively input into the third clock management unit and the feedback terminal of the first clock management unit; the second clock management unit outputs a second clock signal; and the third clock management unit outputs a third clock signal; wherein the clock tree delays of the first, second, and third clock signals are equal. This solution can reduce clock skew between FPGA chips and achieve clock synchronization for multiple FPGA chips. This solution is suitable for systems with two FPGA chips and is not applicable to large-scale FPGA verification systems. It also does not achieve clock synchronization within the FPGA.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to ordinary technicians in this field. Summary of the Invention

[0006] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0007] The embodiments of the present disclosure provide a multi-FPGA global clock synchronization device and method, which eliminates clock deviations at the board level and between boards through a master-slave clock expansion circuit and a dynamic feedback compensation mechanism, and supports clock synchronization of large-scale prototype verification systems.

[0008] In some embodiments, the multi-FPGA global clock synchronization device includes: an inter-board clock synchronization circuit and an intra-board clock synchronization circuit;

[0009] The inter-board clock synchronization circuit is used to achieve clock synchronization between multiple FPGA chips, including an inter-board clock expansion circuit and an inter-board feedback clock line. The input end of the inter-board clock expansion circuit is connected to the external clock and crystal oscillator signal, and the inter-board feedback clock line is connected between the output end and the input end of the inter-board clock expansion circuit. The inter-board clock expansion circuit generates multiple output clock signals based on the input external clock and feedback clock. The multiple output clock signals are respectively used as the input clocks of the FPGA chips;

[0010] The on-board clock synchronization circuit is set in the FPGA chip and is used to realize clock synchronization within the FPGA chip. It includes an on-board clock expansion circuit and an on-board feedback clock line. The input end of the on-board clock expansion circuit is connected to the clock signal output by the inter-board clock synchronization circuit. The on-board feedback clock line is connected between the output end and the input end of the on-board clock expansion circuit. The on-board clock expansion circuit generates an internal clock based on the input clock and feedback clock and distributes it to the internal logic module.

[0011] As a further optimization, the inter-board clock expansion circuit includes a selector and a clock manager, the input end of the selector is connected to the external clock and crystal oscillator signal, the output end of the selector is connected to one input end of the clock manager, the other input end of the clock manager is connected to the signal returned by the inter-board feedback clock line, and the output end of the clock manager outputs multiple clock signals as the input clock of the FPGA chip and the input signal of the inter-board feedback clock line.

[0012] As a further optimization, an input buffer is provided between the input end of the clock manager and the output end of the selector and the return signal of the inter-board feedback clock line, and an output buffer is provided between the output end of the clock manager and the output clock signal and the input signal of the inter-board feedback clock line.

[0013] As a further optimization, the routing of the inter-board feedback clock line is made equal in length to the routing of the output clock signal to achieve clock calibration synchronization and ensure consistent path delays.

[0014] As a further optimization, the on-board clock expansion circuit includes a clock manager. The input end of the clock manager is respectively connected to the clock signal output by the inter-board clock synchronization circuit and the signal returned by the on-board feedback clock line. The output end of the clock manager outputs the internal clock and distributes it to the internal logic module.

[0015] As a further optimization, an input buffer is provided between the input end of the clock manager and the clock signal output by the inter-board clock synchronization circuit and the return signal of the intra-board feedback clock line, and an output buffer is provided between the output end of the clock manager and the output internal clock and the input signal of the intra-board feedback clock line.

[0016] As a further optimization, the clock manager adopts a hybrid mode clock manager, which completes frequency synthesis and phase adjustment based on the input clock and the feedback clock to generate an output clock signal.

[0017] As a further optimization, multiple inter-board clock synchronization circuits are provided. A hierarchical cascade architecture is adopted between the multiple inter-board clock synchronization circuits. One inter-board clock synchronization circuit is selected as the master end, and the other inter-board clock synchronization circuits are used as slave ends. The master end generates a master clock source and sends it to each slave end. Each slave end generates multiple output clock signals as the input clock of the FPGA chip based on the received master clock source. Even if the design scale is expanded, the global clock can be calibrated through hierarchical and graded calibrating to ensure the clock and reset synchronization of the ultra-large-scale prototype system.

[0018] In some embodiments, the multi-FPGA global clock synchronization method includes two parts: inter-board clock synchronization and intra-board clock synchronization;

[0019] Inter-board clock synchronization is used to achieve clock synchronization between multiple FPGA chips. It first receives the input clock signal and crystal oscillator signal and selects one of them as the first input signal. At the same time, it receives the feedback clock signal returned by the inter-board feedback clock line as the second input signal. It performs frequency synthesis and phase adjustment based on the first and second clock signals to generate multiple output clock signals. The multiple output clock signals are used as the input clocks of the FPGA chips respectively.

[0020] Intra-board clock synchronization is used to achieve clock synchronization within the FPGA chip. First, it receives the clock signals output by the inter-board clock synchronization part and selects one as the first input signal. At the same time, it receives the feedback clock signal returned by the intra-board feedback clock line as the second input signal. Frequency synthesis and phase adjustment are performed based on the first clock signal and the second clock signal to generate an internal clock and distribute it to the internal logic module.

[0021] As a further optimization, inter-board clock synchronization and intra-board clock synchronization are completed through frequency synthesis and phase adjustment by a hybrid-mode clock manager.

[0022] The multi-FPGA global clock synchronization device and method provided by the disclosed embodiments can achieve the following technical effects: Through inter-board / inter-board clock expansion circuits and a dynamic feedback compensation mechanism, clock skew between boards is eliminated, supporting clock synchronization in large-scale prototyping systems. The inter-board / inter-board clock expansion circuits feature programmable clock frequency capabilities, reserve external clock input and output interfaces, and a multiplexer (MUX) to construct a clock tree-like structure outside the FPGA chip, effectively resolving the clock asynchrony issue in peripheral systems in multi-FPGA prototyping systems. A feedback clock line is provided, and its routing is equal in length to the output clock line, enabling clock calibration and synchronization to ensure consistent path delays. Each FPGA achieves internal logic clock synchronization through an independent clock management module. To meet the requirements of large-scale designs, a master / slave cascade mode is adopted to expand the clock synchronization range. The master clock expansion circuit generates global clock and reset signals, which are transmitted via equal-length clock cables to the slave clock expansion circuits, which then transmit them to downstream FPGAs. The master clock source can come from its own programmable clock chip or an external clock. Even if the design scale increases, the global clock can be calibrated through hierarchical and graded methods to ensure clock and reset synchronization of ultra-large-scale prototype systems.

[0023] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are exemplarily described by corresponding drawings. These exemplary descriptions and drawings do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a scale limitation. In addition,

[0025] Figure 1 This is the schematic diagram of the inter-board clock synchronization circuit;

[0026] Figure 2 This is the schematic diagram of the inter-board clock expansion circuit;

[0027] Figure 3 This is the schematic diagram of the clock synchronization circuit inside the board;

[0028] Figure 4 This is the schematic diagram of the mixed-mode clock manager;

[0029] Figure 5 This is a schematic diagram of a hierarchical cascade architecture implemented by multiple inter-board clock synchronization circuits. DETAILED DESCRIPTION

[0030] In order to be able to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The accompanying drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the sake of convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0031] The terms "first," "second," and the like in the embodiments of the present disclosure are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate to facilitate the description of the embodiments of the present disclosure herein. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0032] Unless otherwise stated, the term "plurality" means two or more.

[0033] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B means: A or B.

[0034] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0035] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0036] Example 1

[0037] This embodiment discloses a multi-FPGA global clock synchronization device, including an inter-board clock synchronization circuit and an intra-board clock synchronization circuit.

[0038] The inter-board clock synchronization circuit is used to achieve clock synchronization between multiple FPGA chips, such as Figure 1 As shown, it includes an inter-board clock expansion circuit and an inter-board feedback clock line. The input end of the inter-board clock expansion circuit is connected to the external clock and crystal oscillator signal. The inter-board feedback clock line is connected between the output end and the input end of the inter-board clock expansion circuit. The inter-board clock expansion circuit generates multiple output clock signals according to the input external clock and feedback clock, that is, Figure 1 The clk1, clk2, clk3, and clk4 in the output clock signals clk1, clk2, clk3, and clk4 are used as the input clocks of the FPGA chips FPGA_1, FPGA_2, FPGA_3, and FPGA_4 respectively.

[0039] like Figure 2 As shown, the inter-board clock expansion circuit includes a selector MUX and a clock manager MMCM_0. The input of the selector MUX is connected to an external clock and crystal oscillator signal. The output of the selector MUX is connected to one input of the clock manager MMCM_0 through an input buffer IBUFG. The other input of the clock manager MMCM_0 is connected to the return signal of the inter-board feedback clock line through an input buffer IBUFG. The output of the clock manager MMCM_0 outputs multiple clock signals through an output buffer BUFG. These clock signals clk1, clk2, clk3, and clk4 serve as input clocks for the FPGA chip and as input signals for the inter-board feedback clock line. The input and output buffers ensure the stability and reliability of the clock signals. After being selected by the selector MUX, the external clock and crystal oscillator signals are input to the clock manager MMCM_0 through the input buffer IBUFG. After MMCM_0 completes frequency synthesis and phase adjustment, the outputs clk1-clk4 are distributed through the output buffer BUFG to serve as the global clock inputs for the four FPGAs. At the same time, the clock clk1-clk4 generated by the clock manager MMCM_0 is fed back through the BUFG and the external PCB routing. The feedback clock routing is the same length as the clk1, clk2, clk3, and clk4 routing to achieve clock calibration synchronization to ensure consistent path delays.

[0040] The internal clock synchronization circuit is set in the FPGA chip to achieve clock synchronization in the FPGA chip, such as Figure 3 As shown, the intra-board clock synchronization circuit includes an intra-board clock expansion circuit and an intra-board feedback clock circuit. The input of the intra-board clock expansion circuit is connected to the clock signal output by the inter-board clock synchronization circuit. The intra-board feedback clock circuit is connected between the output and input of the intra-board clock expansion circuit. The intra-board clock expansion circuit generates an internal clock based on the input and feedback clocks and distributes it to the internal logic modules. The intra-board clock expansion circuit includes a clock manager MMCM_1. The input of the clock manager MMCM_1 is connected to the clock signal output by the inter-board clock synchronization circuit and the return signal from the intra-board feedback clock circuit, respectively. The output of the clock manager outputs the internal clock and distributes it to the internal logic modules. The main clock source is generated by the inter-board clock expansion circuit to generate clk1-clk4, which are then distributed to different FPGAs. For example, FPGA1 and FPGA2 use clk1 and clk2 as input clocks. After adjustment by their respective clock managers, they are distributed to the internal logic by the output buffer BUFG. The intra-board feedback clock circuit is routed from the output of the output buffer BUFG back to MMCM_1, dynamically calibrating the clock phase and frequency to improve stability. Each FPGA achieves internal logic clock synchronization through an independent clock management module.

[0041] In order to ensure the stability and reliability of the clock signal, an input buffer IBUFG is provided between the input end of the clock manager and the clock signal output by the inter-board clock synchronization circuit and the return signal of the intra-board feedback clock line. An output buffer BUFG is provided between the output end of the clock manager and the output internal clock and the input signal of the intra-board feedback clock line.

[0042] In this embodiment, the clock managers MMCM_0 and MMCM_1 both use mixed-mode clock managers. The mixed-mode clock managers perform frequency synthesis and phase adjustment based on the input clock and feedback clock to generate an output clock signal. MMCM is a feedback control circuit that uses an external input reference signal to control the frequency and phase of the oscillation signal inside the loop. Figure 4 As shown, the mixed-mode clock manager includes a multiplexer MPX, a frequency divider D, a phase frequency detector PFD, a charge pump CP, a loop filter LF, and a voltage-controlled oscillator VCO connected in sequence. The voltage-controlled oscillator VCO is followed by multiple output ports O0 to O5, each of which corresponds to a frequency divider D0 to D5. A feedback path is also set behind the voltage-controlled oscillator VCO, and the feedback path includes a frequency divider D6 and a frequency multiplier M.

[0043] The hybrid-mode clock manager operates as follows: After the input clocks CLKIN1 and CLKIN2 enter the module, they first pass through a multiplexer MPX, which selects between the two input clocks. The selected clock signal is then divided by a frequency divider D. When the rising edge of the input and feedback clock signals arrives, the phase-frequency detector (PFD) compares the frequencies and phases of the two clocks and generates a proportional signal that is transmitted to the subsequent charge pump (CP) and loop filter (LF). The charge pump (CP) and loop filter (LF) work together to generate a reference voltage, which is used to control the voltage-controlled oscillator (VCO). The phase-frequency detector (PFD) also generates an up or down signal to the charge pump (CP) and loop filter (LF) based on the phase-frequency difference between the input and feedback clocks, thereby increasing or decreasing the clock frequency generated by the VCO. For example, if the output clock frequency is too high, a down signal is generated, which reduces the VCO control voltage, thereby decreasing the clock frequency. The proportional signal generated by the phase-frequency detector (PFD) determines the magnitude of the frequency change.

[0044] In the feedback path, the feedback clock signal passes through a frequency multiplier M before reaching the phase-frequency detector (PFD). This allows the frequency multiplier M to adjust the output clock frequency accordingly, effectively increasing the frequency range. Furthermore, each MMCM module features multiple clock output ports, each corresponding to a frequency divider. Therefore, each clock port can independently adjust its output frequency, further expanding the frequency range and significantly enhancing frequency configuration flexibility.

[0045] In response to large-scale design requirements, the master / slave cascade mode is used to expand the clock synchronization range, that is, multiple inter-board clock synchronization circuits are set up, and a hierarchical cascade architecture is used between the multiple inter-board clock synchronization circuits, such as Figure 5 As shown, one inter-board clock synchronization circuit is selected as the master, and the remaining inter-board clock synchronization circuits are slaves. The master generates a master clock source and transmits it to each slave. Each slave generates multiple output clock signals based on the received master clock source, which serve as input clocks for the FPGA chip. Even as the design scales up, hierarchical and graded global clock calibration ensures clock and reset synchronization for ultra-large-scale prototype systems.

[0046] Example 2

[0047] In some embodiments, the multi-FPGA global clock synchronization method is implemented based on the device described in Example 1, and includes two parts: inter-board clock synchronization and intra-board clock synchronization;

[0048] Inter-board clock synchronization is used to achieve clock synchronization between multiple FPGA chips. It first receives the input clock signal and crystal oscillator signal and selects one of them as the first input signal. At the same time, it receives the feedback clock signal returned by the inter-board feedback clock line as the second input signal. It performs frequency synthesis and phase adjustment based on the first and second clock signals to generate multiple output clock signals. The multiple output clock signals are used as the input clocks of the FPGA chips respectively.

[0049] Intra-board clock synchronization is used to achieve clock synchronization within the FPGA chip. First, it receives the clock signals output by the inter-board clock synchronization part and selects one as the first input signal. At the same time, it receives the feedback clock signal returned by the intra-board feedback clock line as the second input signal. Frequency synthesis and phase adjustment are performed based on the first clock signal and the second clock signal to generate an internal clock and distribute it to the internal logic module.

[0050] Specifically, inter-board clock synchronization and intra-board clock synchronization are accomplished through frequency synthesis and phase adjustment by a hybrid-mode clock manager.

[0051] The present invention can reduce clock delay and ensure clock synchronization as much as possible, which is explained below through calculation.

[0052] First calculate the delay deviation t of clk1-clk4 relative to the external clock input clk0 clk0 ;

[0053] t clk0 =t in +t mmcm0 +t out +t pcb ,

[0054] where t in represents the delay of the input clock from the I / O pin to MMCM_0, t out Denotes the delay from MMCM to output I / O pin, t mmcm0 Indicates the delay of the clock passing through the MMCM device, t pcb Indicates the delay caused by wiring the FPGA external PCB board.

[0055] According to the phase-locked loop (PLL) characteristics, the delay satisfies:

[0056] t mmcm0 +t in +t out +t pcb =nT, n is a positive integer,

[0057] T represents the clock period, which can be simplified to:

[0058] t clk0 =nT.

[0059] MMCM1 incorporates FPGA1's clock signal clkin1, the clock output I / O port, the clock feedback line, and the clock input I / O port into a feedback loop. This feedback loop effectively compensates for clock skew caused by these four factors. These skews closely resemble those incurred during clock transmission, thus eliminating clock skew between FPGAs.

[0060] Taking FPGA1 and FPGA2 as examples, the deviations tclk1 and tclk2 of clkin1 and clkin2 relative to the clock inputs clk1 and clk2 are calculated below.

[0061] t clk1 =t in +t mmcm1 +t tree1 ;

[0062] t tree1 Indicates the delay deviation of the internal clock of FPGA1 through the clock tree. Similarly:

[0063] t clk2 =tin +t mmcm2 +t tree2 ;

[0064] t tree2 Indicates the delay deviation of the internal clock of FPGA2 through the clock tree.

[0065] According to the characteristics of the phase-locked loop (PLL):

[0066] t mmcm1 +t tree1 =nT n is a positive integer;

[0067] Similarly, t mmcm2 +t tree2 =nT n is a positive integer,

[0068] Simplified:

[0069] t clk1 =t clk2 =t in +nT.

[0070] As can be seen, FPGA1 and FPGA2 drive the internal logic of clkin1 and clkin2 with consistent delay relative to the external input clock. MMCM1 and MMCM2 compensate for local clock delays. FPGA1 eliminates internal clock tree delay variations through MMCM1's clock feedback loop, ultimately achieving global clock synchronization across the multi-FPGA system.

[0071] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible variations. Unless explicitly required, separate components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terms used in this application are only used to describe the embodiments and are not used to limit the scope of protection. As used in the description in the text, unless the context clearly indicates otherwise, the singular forms of "a", "an" and "the" are intended to also include plural forms. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of one or more associated listings. In addition, when used in this application, the term "comprise" and its variations "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, an element defined by the statement "comprises a..." does not exclude the presence of other identical elements in the process, method or device that includes the element. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments can be referenced to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can be found in the description of the method part.

[0072] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. The technicians will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0073] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units can be merely a logical functional division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, the functional units in the embodiments of the present disclosure may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

Claims

1. A multi-FPGA global clock synchronization device, characterized in that: Including inter-board clock synchronization circuit and intra-board clock synchronization circuit; The inter-board clock synchronization circuit is used to achieve clock synchronization between multiple FPGA chips, including an inter-board clock expansion circuit and an inter-board feedback clock line. The input end of the inter-board clock expansion circuit is connected to the external clock and crystal oscillator signal, and the inter-board feedback clock line is connected between the output end and the input end of the inter-board clock expansion circuit. The inter-board clock expansion circuit generates multiple output clock signals based on the input external clock and feedback clock. The multiple output clock signals are respectively used as the input clocks of the FPGA chips; The on-board clock synchronization circuit is set in the FPGA chip and is used to realize clock synchronization within the FPGA chip. It includes an on-board clock expansion circuit and an on-board feedback clock line. The input end of the on-board clock expansion circuit is connected to the clock signal output by the inter-board clock synchronization circuit. The on-board feedback clock line is connected between the output end and the input end of the on-board clock expansion circuit. The on-board clock expansion circuit generates an internal clock based on the input clock and feedback clock and distributes it to the internal logic module.

2. The multi-FPGA global clock synchronization device according to claim 1, characterized in that: The inter-board clock expansion circuit includes a selector and a clock manager. The input end of the selector is connected to the external clock and crystal oscillator signal, the output end of the selector is connected to one input end of the clock manager, the other input end of the clock manager is connected to the signal returned by the inter-board feedback clock line, and the output end of the clock manager outputs multiple clock signals as the input clock of the FPGA chip and the input signal of the inter-board feedback clock line.

3. The multi-FPGA global clock synchronization device according to claim 2, characterized in that: An input buffer is provided between the input end of the clock manager and the output end of the selector and the return signal of the inter-board feedback clock line. An output buffer is provided between the output end of the clock manager and the output clock signal and the input signal of the inter-board feedback clock line.

4. The multi-FPGA global clock synchronization device according to claim 2, characterized in that: The routing of the inter-board feedback clock line is equal in length to the routing of the output clock signal.

5. The multi-FPGA global clock synchronization device according to claim 1, characterized in that: The on-board clock expansion circuit includes a clock manager. The input end of the clock manager is connected to the clock signal output by the inter-board clock synchronization circuit and the signal returned by the on-board feedback clock line. The output end of the clock manager outputs the internal clock and distributes it to the internal logic module.

6. The multi-FPGA global clock synchronization device according to claim 5, characterized in that: An input buffer is provided between the input end of the clock manager and the clock signal output by the inter-board clock synchronization circuit and the return signal of the intra-board feedback clock line. An output buffer is provided between the output end of the clock manager and the output internal clock and the input signal of the intra-board feedback clock line.

7. The multi-FPGA global clock synchronization device according to claim 2 or 5, characterized in that: The clock manager adopts a mixed-mode clock manager, which completes frequency synthesis and phase adjustment based on an input clock and a feedback clock, thereby generating an output clock signal.

8. The multi-FPGA global clock synchronization device according to claim 1, characterized in that: There are multiple inter-board clock synchronization circuits, and a hierarchical cascade architecture is adopted between the multiple inter-board clock synchronization circuits. One inter-board clock synchronization circuit is selected as the host end, and the remaining inter-board clock synchronization circuits are used as slave ends. The host end generates a master clock source and sends it to each slave end. Each slave end generates multiple output clock signals as the input clock of the FPGA chip based on the received master clock source.

9. A multi-FPGA global clock synchronization method, characterized in that: This method includes two parts: inter-board clock synchronization and intra-board clock synchronization; Inter-board clock synchronization is used to achieve clock synchronization between multiple FPGA chips. It first receives the input clock signal and crystal oscillator signal and selects one of them as the first input signal. At the same time, it receives the feedback clock signal returned by the inter-board feedback clock line as the second input signal. It performs frequency synthesis and phase adjustment based on the first and second clock signals to generate multiple output clock signals. The multiple output clock signals are used as the input clocks of the FPGA chips respectively. Intra-board clock synchronization is used to achieve clock synchronization within the FPGA chip. First, it receives the clock signals output by the inter-board clock synchronization part and selects one as the first input signal. At the same time, it receives the feedback clock signal returned by the intra-board feedback clock line as the second input signal. Frequency synthesis and phase adjustment are performed based on the first clock signal and the second clock signal to generate an internal clock and distribute it to the internal logic module.

10. The multi-FPGA global clock synchronization method according to claim 9, characterized in that: Inter-board clock synchronization and intra-board clock synchronization are completed through frequency synthesis and phase adjustment by the hybrid-mode clock manager.

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