Message uploading method, data processing unit and network processor

Abstract

The invention relates to a message uploading method, a data processing unit and a network processor, and the method comprises the steps: obtaining the number of messages currently cached in the data processing unit in a target queue, so as to determine the number of descriptors to be read, obtaining the descriptors in batches through one PCIe reading operation, and sending the descriptors to the target queue; the messages of the currently cached target queue are written into host side caches pointed by the descriptors, and every time one message is successfully uploaded, one is subtracted from the message count of the currently cached target queue; and if the currently read descriptor is used up, but the target queue has unprocessed messages, repeating the above steps, determining and reading the required descriptor according to the number of the remaining messages of the currently cached target queue again, continuing to write the messages, and repeating the above steps. And all the messages of the currently cached target queue are successfully carried to the host side for caching. According to the method and the device, the message uploading efficiency and the bandwidth utilization rate are improved by optimizing the descriptor reading mode.

Description

Technical Field

[0001] The present application relates to the field of Virtio technology, and in particular to a message sending method, a data processing unit, and a network processor. Background Art

[0002] Virtio is a general-purpose paravirtualized I / O framework that includes the Virtio driver, Virtio devices, and virtualized queues (Virtqueues). Data exchange between the Virtio driver and the Virtio device is implemented through Virtqueues. Taking SplitVirtqueues as an example, the Virtio driver mainly consists of three parts: the descriptor ring, the available ring table, and the used ring table. Each descriptor entry in the descriptor table contains a buffer address, a buffer length, a flag, and a next hop pointer. The available ring table and the used ring table contain pointers (ids) that point to a descriptor entry in the descriptor table. Before receiving a packet, the Virtio driver needs to prepare the buffer for storing the packet and then notify the Virtio device. The Virtio device begins receiving the packet data. The data receiving process of the Virtio device is as follows: (1) The Virtio device receives Ethernet packets and stores them in the local cache of the Virtio device; (2) The Virtio device initiates a read operation on the available ring table of the Virtio driver to obtain the pointer (ID) of the available ring table; (3) Read the descriptor of the descriptor table according to the pointer (id) obtained from the available ring table to obtain information such as the cache address, cache length, flag, and next hop pointer; (4) Read the Ethernet message from the local cache of the Virtio device and send it to the cache unit pointed to by the descriptor; (5) Update the used descriptors, that is, update the index (index) and pointer (id) of the used ring table. The Virtio driver obtains the Ethernet message in the cache unit by reading the index (index) and pointer (id) of the used ring table and other information, and recycles the descriptor entries in the descriptor table for continued use.

[0003] like Figure 1As shown, after each descriptor read by a Virtio device, the next round of descriptor reads will only be initiated after the fixed number of descriptors currently being read has been exhausted. If a Virtio device reads one descriptor at a time, the next round of descriptor reads will only be initiated after the descriptors have been exhausted. If the descriptor return time is 1 μs, the message processing performance of a queue is 1 Mpps (packets per second). To improve the performance of the entire Virtio system, multiple queues can be enabled through pipelining. However, due to limitations such as the number of queues and the logical resources and area of the Virtio device, improving overall performance cannot be achieved by simply increasing the number of queues. Furthermore, the rapid development of cloud computing and artificial intelligence has placed increasingly higher performance demands on virtual machines, which in turn places higher demands on the performance of a single queue. If the Virtio device reads a fixed number (at least two) of descriptors each time, the performance of a single queue will be improved. However, there is a problem that must be solved. That is, the number of descriptors required is less than the number of descriptors requested. In this case, there are two ways to handle the excess descriptors: one is to increase RAM resources to store the excess descriptors, and the other is to roll back the excess descriptors. The first method increases the cache resources of the Virtio device and needs to balance the number of queues and the number of descriptors that can be stored in each queue, which increases the logic complexity. The second method does not use the rolled-back descriptors of the Virtio device, which not only wastes the PCIE read bandwidth and read return bandwidth, but also requires adding rollback processing logic to the Virtio device.

[0004] In summary, the Virtio device has certain defects when reading one or a fixed number of descriptors each time. Summary of the Invention

[0005] The purpose of the present application is to provide a message uploading method, a data processing unit, a network processor, and a computer program product to solve the problem of low single-queue message processing performance when reading one descriptor at a time, and the defect that reading a fixed number (at least two) of descriptors at a time requires more RAM resources and more complex logic for Virtio devices.

[0006] To achieve the above objectives, an embodiment of the present application provides a method for sending a message, the method comprising: Obtaining the number of messages currently cached in the data processing unit by the target queue, and determining the number of descriptor reads according to the number of messages; Reading the number of descriptors through a single PCIE read operation; Writing the message of the target queue into the host-side cache unit pointed to by the descriptor; wherein, each time a message of the target queue is written into the host-side cache unit, the number of currently cached messages corresponding to the target queue is reduced by one; If all the read descriptors have been used and not all the messages of the target queue have been written into the host-side cache unit, the number of descriptor reads is determined again based on the number of current cached messages corresponding to the target queue, and the re-determined number of descriptors is read through a single PCIE read operation, and the remaining messages of the target queue are written into the host-side cache unit pointed to by the re-read descriptors until all the cached messages corresponding to the target queue are written into the host-side cache unit.

[0007] Preferably, determining the number of descriptor reads according to the number of messages includes: The current number of messages in the target queue is determined as the number of descriptor reads.

[0008] Preferably, the method further comprises: If any queue in the data processing unit has a message to be written to the host side cached and any queue needs to read a descriptor, the any queue is determined as a queue to be scheduled, and all current queues to be scheduled are scheduled to determine the target queue.

[0009] Preferably, the method further comprises: Obtain the message valid bitmap value and read wait bitmap value of any of the queues, perform an AND operation on the message valid bitmap value and the read wait bitmap value, and determine whether to determine any of the queues as the queue to be scheduled based on the AND operation result; wherein, the message valid bitmap value indicates whether any of the queues has a cached message; the read wait bitmap value indicates whether any of the queues needs to read a descriptor; if any of the queues has a corresponding cached message, the message valid bitmap value of any of the queues is set to 1, otherwise it is set to 0; if any of the queues needs to read a descriptor, the read wait bitmap value of any of the queues is set to 1, otherwise it is set to 0.

[0010] Preferably, the method further comprises: Receive messages from any queue, cache the messages from any queue in a message storage module corresponding to any queue, and update a message quantity value in a message quantity cache unit corresponding to any queue.

[0011] A second aspect of the present application provides a data processing unit, comprising a descriptor number determination module, a descriptor reading module, and a message sending module; The descriptor number determination module is used to obtain the number of messages currently cached in the data processing unit by the target queue, and determine the number of descriptor reads according to the number of messages; The descriptor reading module is used to read the number of descriptors through a single PCIE read operation; The message sending module is used to write the message of the target queue into the host-side cache unit pointed to by the descriptor; wherein, each time a message of the target queue is written into the host-side cache unit, the number of cached messages of the target queue is reduced by one; The descriptor number determination module is further configured to determine the number of descriptor reads again based on the number of messages in the target queue currently cached, if all the descriptors currently read have been used and not all the messages in the target queue currently cached have been written into the host-side cache unit; The descriptor reading module is further configured to read a re-determined number of descriptors through a single PCIE read operation; The message sending module is further configured to write the remaining messages in the target queue into the host-side cache unit pointed to by the descriptor read again.

[0012] Preferably, the descriptor number determination module is used to determine the number of messages in the target queue as the descriptor reading number.

[0013] Preferably, the data processing unit also includes a queue scheduling module, which is used to determine any queue as a queue to be scheduled if any queue in the data processing unit caches a message to be written to the host side and any queue needs to read a descriptor, and schedule all current queues to be scheduled to determine the target queue.

[0014] Preferably, the queue scheduling module is used to obtain a message valid bitmap value and a read wait bitmap value of any queue, perform an AND operation on the message valid bitmap value and the read wait bitmap value, and determine whether to determine any queue as a queue to be scheduled according to the AND operation result; Among them, the message valid bitmap value indicates whether any of the queues has cached messages; the read wait bitmap value indicates whether any of the queues needs to read the descriptor; if there is a message of any of the queues currently cached, the message valid bitmap value of any of the queues is set to 1, otherwise it is set to 0; if any of the queues needs to read the descriptor, the read wait bitmap value of any of the queues is set to 1, otherwise it is set to 0.

[0015] Preferably, the data processing unit also includes a message receiving module, which is used to receive messages from any queue, cache the messages from any queue into the message storage module corresponding to any queue, and update the message number value in the message number cache unit corresponding to any queue.

[0016] The present invention further provides a data processing unit, including: Communication interface, used for communicating with other electronic devices; a memory for storing computer program instructions; The processor is used to execute the computer program instructions to support the data processing unit to implement the above method.

[0017] An embodiment of the present application further provides a network processor, including a Virtio driver and the data processing unit as described above, wherein the Virtio driver runs on a host side and is at least used to generate the descriptor.

[0018] An embodiment of the present application also provides a computer program product, including computer program instructions, which instruct a computer device to perform operations corresponding to the above method.

[0019] The message sending method, data processing unit, network processor, and computer program product of the embodiments of the present application have the following beneficial effects: An embodiment of the present application proposes an adaptive descriptor read strategy. Based on the number of messages currently required to be processed by a target queue (Virtqueue), the strategy dynamically determines the number of descriptors to be read from the host. A corresponding number of descriptors is read through a single PCIE read operation, and the messages from the target queue are written to the host-side cache corresponding to the descriptors. If the currently read descriptors have been used up and the messages from the target queue have not yet been fully sent, one or more PCIE read operations are performed based on the number of messages in the target queue currently cached to obtain more descriptors until all messages are processed. By minimizing the number of PCIE read operations, the strategy improves the processing throughput of a single queue and overcomes the low performance of reading a single descriptor. Because the number of descriptors read each time is dynamically determined based on the actual number of messages, there is no need to reserve RAM for descriptors that may not be used, nor is there a need for complex fallback processing. This effectively addresses the low single-queue message processing performance associated with reading one descriptor at a time, as well as the drawback that reading a fixed number (at least two) of descriptors each time requires additional RAM resources and more complex logic for the Virtio device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 This is a flowchart of the message sending disclosed in the background technology.

[0022] Figure 2 This is a flowchart of a message sending method in an embodiment of the present application.

[0023] Figure 3 Schematic diagram of the interaction between the data processing unit and the Virtio driver in an embodiment of the present application.

[0024] Figure 4 This is a schematic diagram of the principle of sending messages in an embodiment of the present application.

[0025] Figure 5 This is a structural diagram of a data processing unit in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The detailed description of the accompanying drawings is intended to serve as an illustration of the current embodiment of the present application and is not intended to represent the only form in which the present application can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included in the spirit and scope of the present application.

[0027] See Figures 2 and 3 An embodiment of the present application provides a method for sending a message, including: Step S10, obtaining the number of messages currently cached in the data processing unit by the target queue, and determining the number of descriptor reads according to the number of messages; Specifically, the Virtio driver needs to prepare a buffer before receiving a message, and then notify the Data Processing Unit (DPU). The DPU starts receiving messages and caches them locally. In the DPU, the received messages are cached according to the queue to which the messages belong, waiting to be sent to the cache unit on the host side; when any queue is scheduled, the queue is used as the target queue. At this time, the DPU obtains the number of messages in the currently cached target queue and determines the number of descriptor reads based on the number of messages.

[0028] Step S20, reading the descriptors corresponding to the descriptor read number through a single PCIE read operation; Specifically, compared to the traditional method that may require multiple PCIe read operations (reading one descriptor each time), this embodiment can batch read multiple descriptors at one time based on the number of messages, reducing the number of PCIe read operations. Each descriptor contains information such as the address, length, flags, and next hop pointer of the host-side cache unit.

[0029] Step S30, writing the message of the target queue into the host-side cache unit pointed to by the corresponding descriptor; wherein, each time a message of the target queue is written into the host-side cache unit, the number of messages in the target queue is reduced by one; Specifically, after batch reading of the descriptors corresponding to the number of descriptor reads, the messages cached in the target queue of the DPU are written sequentially into the cache units (buffers) corresponding to the descriptors corresponding to the number of descriptor reads; in this embodiment, the number of messages in the target queue is updated in real time, and each time a message is uploaded, the number of cached messages corresponding to the target is reduced by one.

[0030] Step S40: If all the currently read descriptors have been used and all the messages of the currently cached target queue have not been written into the host-side cache unit, the descriptor read number is determined again according to the number of messages of the currently cached target queue, and the descriptors corresponding to the re-determined descriptor read number are read through a single PCIE read operation, and the remaining messages of the currently cached target queue are written into the host-side cache unit pointed to by the re-read descriptors, until all the messages cached by the target queue are written into the host-side cache unit; Specifically, in step S40, if all the messages of the target queue cached locally by the DPU are written into the host-side cache unit, the host is notified that the messages of the target queue have been uploaded; if all the descriptors currently read have been used and all the messages of the target queue have not been written into the host-side cache unit, more descriptors need to be read to continue to complete the upload of the messages of the target queue. At this time, steps S10 to S30 are repeated until all the messages cached by the target queue are written into the host-side cache unit.

[0031] The method of this embodiment proposes an adaptive descriptor reading strategy. According to the number of messages currently cached in the target queue (Virtqueue), the number of descriptors that need to be read from the host is dynamically determined, and the corresponding number of descriptors are read through a PCIE read operation, and the messages of the target queue are written into the cache unit on the host side corresponding to the descriptor; during the processing, the remaining messages of the target queue are dynamically tracked. If the currently read descriptors have been used up and the messages of the target queue have not been sent up, one or more PCIE read operations are performed based on the number of messages of the target queue currently cached to obtain more descriptors. , until all messages are processed; the embodiment of the present application improves the processing throughput of a single queue by minimizing the number of PCIE read operations, and compensates for the disadvantage of low performance in reading a single descriptor. Since the number of descriptors read each time is dynamically determined according to the actual number of messages, there is no need to reserve RAM for descriptors that may not be used, and no need for complex fallback processing, thereby effectively solving the problem of low single-queue message processing performance when reading one descriptor at a time, and the defect that Virtio devices need to add more RAM resources and more complex logic when reading a fixed number (at least two) of descriptors each time.

[0032] In some embodiments, determining the number of descriptor reads based on the number of messages in the target queue includes: The number of messages in the target queue is determined as the number of descriptor reads.

[0033] Specifically, in this embodiment, when the storage space of the host-side cache unit corresponding to a descriptor is greater than or equal to the data volume of a message A, the host-side cache unit corresponding to the descriptor stores a message separately; when the storage space of the host-side cache unit of a descriptor is less than the data volume of a message B, different parts of the data of a message B are stored respectively through at least two host-side cache units corresponding to at least two descriptors; different messages are stored in different host-side cache units respectively; the number of messages in the target queue currently cached is updated in real time, and this embodiment dynamically determines the number of descriptor reads based on the number of messages in the target queue currently cached, that is, the number of descriptors read back at a single time is less than or equal to the number of descriptors actually required by the cached messages. This application can minimize the number of PCIE read operations, improve the processing throughput of a single queue, and make up for the disadvantage of low performance in reading a single descriptor. In addition, there is no need to reserve RAM for descriptors that may not be used, nor is there a need for complex fallback processing.

[0034] In some embodiments, the method further comprises: If any queue currently caches a message to be written to the host side in the data processing unit and any queue needs to read a descriptor, the any queue is determined as a queue to be scheduled, and all currently scheduled queues are scheduled to determine the target queue.

[0035] Specifically, the DPU can only initiate the reading of the descriptor of one queue at a time, and the DPU and the host driver usually transmit data through multiple queues. Therefore, it is necessary to arbitrate and schedule multiple queues to be scheduled with scheduling requirements, such as round-robin scheduling, and select one of the queues as the target queue. Among them, if there is a message from any queue currently cached and any queue needs to read the descriptor, it means that the queue has a scheduling requirement.

[0036] In some embodiments, the method further comprises: Obtain the message valid bitmap value and read wait bitmap value of any of the queues, perform an AND operation on the message valid bitmap value and the read wait bitmap value, and determine whether to determine any of the queues as the queue to be scheduled based on the AND operation result; wherein, the message valid bitmap value indicates whether any of the queues has cached messages; the read wait bitmap value indicates whether any of the queues needs to read the descriptor; if there is a message of any of the queues currently cached, the message valid bitmap value of any of the queues is set to 1, otherwise it is set to 0; if any of the queues needs to read the descriptor, the read wait bitmap value of any of the queues is set to 1, otherwise it is set to 0.

[0037] Specifically, the DPU includes a message valid bitmap and a read wait bitmap. Both the message valid bitmap and the read wait bitmap include bits corresponding to multiple queues one by one. Each bit of the message valid bitmap is used to fill in the message valid bitmap value of the corresponding queue, and each bit of the read wait bitmap is used to fill in the read wait bitmap value of the corresponding queue. The bitmap provides a clear and unambiguous way to represent the status of each queue, which is convenient for hardware or software logic to make judgments and decisions. Moreover, the storage space occupied by the bitmap is very small (each queue only requires 1 bit, marked as 0 or 1), which is suitable for implementation on resource-constrained device ends. Based on the message valid bitmap and the read wait bitmap, AND operations are performed. According to the AND operation results, it is possible to quickly determine which queues have scheduling requirements, and the queues whose message valid bitmap values and read wait bitmap values have an AND operation result of 1 are determined as queues to be scheduled. The DPU schedules these queues to be scheduled through a preset scheduling strategy.

[0038] In some embodiments, the method further comprises: Receive messages from any queue, cache the messages from any queue in the message storage module corresponding to any queue, and update the storage value in the message number cache unit corresponding to any queue, where the storage value is the number of messages from any queue currently cached.

[0039] Specifically, the DPU caches received messages according to queues. The DPU includes a message memory, which includes multiple message storage modules corresponding one-to-one to multiple queues, and each message storage module is used to cache messages of its corresponding queue; in addition, the DPU also includes a message number memory, which includes multiple message number cache units corresponding one-to-one to multiple queues, and each message number cache unit is used to record the number of messages of the corresponding queue currently cached by the DPU.

[0040] In some embodiments, the method comprises: After reading the corresponding descriptor, the read descriptor is stored in the descriptor FIFO module, and the descriptor FIFO module performs dequeue management on the descriptor stored in the descriptor FIFO module according to the first-in-first-out principle.

[0041] Specifically, the DPU also includes a descriptor FIFO module. In the method of this embodiment, the descriptor FIFO module is used to manage the read descriptors. The descriptor FIFO module acts as a buffer, which decouples the PCIe read operation and the message upload operation of the descriptor. The PCIe read operation of the descriptor is completed quickly, but the operation of writing to the host cache unit may be slightly slower due to other reasons. The descriptor FIFO module can absorb this difference and prevent data loss or processing flow blockage.

[0042] See Figure 4 The following is a detailed example to illustrate the message sending method of this embodiment: The DPU receives two messages from queue 1. Message 1 is 5000 bytes long and message 2 is 1000 bytes long. At this time, the DPU will record 2 in the memory cell corresponding to queue 1 in the descriptor read number memory (RAM). The corresponding DPU executes Figure 4 Step ①; The message valid bitmap (bitmap) and the bit0 corresponding to queue 1 are set to 1, and the corresponding DPU executes Figure 4 Step ②; The message valid bitmap and the read wait bitmap are logically ANDed to obtain a new bitmap. Since bit0 of the message valid bitmap is 1 and bit0 of the read wait bitmap is also 1 (the initial value is 1), the bit0 corresponding to queue 1 in the new bitmap is also 1, indicating that queue 1 can participate in the descriptor request scheduling, and the corresponding DPU executes Figure 4 Step ③; When dispatched to queue 1, the bit0 of the read wait bitmap is set to 0, indicating that queue 1 does not need to be dispatched again, and the corresponding DPU executes Figure 4 Step ④; Initiate a descriptor request for queue 1. The number of descriptors requested is the value of the storage unit corresponding to queue 1 in the descriptor read number memory (RAM) at this time, which is 2. The corresponding DPU executes Figure 4 Step ⑤; Read two descriptors (descriptor 1, descriptor 2) from queue 1 from the host driver. Assuming that the length of the cache unit pointed to by the descriptor is 2048 bytes, store these two descriptors in the descriptor FIFO module corresponding to queue 1. The corresponding DPU executes Figure 4 Step ⑥; Since the length of message 1 is 5000Byte and the length of a cache unit is 2048Byte, message 1 requires 3 descriptors. Therefore, the two descriptors that have been read can only be used to store part of the message data of message 1. The message storage module 1 corresponding to queue 1 in the message storage memory (RAM) is read. The descriptors 1 and 2 in the descriptor FIFO module corresponding to queue 1 are read. The part of the data of message 1 is sent to the host-side cache unit pointed to by the two descriptors respectively. The corresponding DPU executes Figure 4 Step ⑦; Since both descriptors have been used, the bit0 of the read wait bitmap is set to 1, indicating that queue 1 has completed the last round of queue scheduling, and the corresponding DPU executes Figure 4 Step ⑧; Since only part of the message data of message 1 is read from the message storage memory (RAM), the value of the storage unit corresponding to queue 1 in the descriptor read number memory (RAM) is still 2; Since bit0 of the message valid bitmap and the read wait bitmap are both 1, queue 1 can participate in a new round of descriptor request scheduling, and the corresponding DPU executes Figure 4 Step ③; When dispatched to queue 1, the bit0 of the read wait bitmap is set to 0, indicating that queue 1 does not need to be dispatched again, and the corresponding DPU executes Figure 4 Step ④; Initiate a descriptor request for queue 1. The number of descriptors requested is the value of the descriptor read number memory (RAM) at this time, which is 2. The corresponding DPU executes Figure 4 Step ⑤; Read two descriptors (descriptor 3, descriptor 4) from queue 1 from the host driver. The length of the cache unit pointed to by the descriptor is still 2048 bytes. Store these two descriptors in the descriptor FIFO module corresponding to queue 1. The corresponding DPU executes Figure 4 Step ⑥; Because the remaining 904 bytes of message 1 are not sent to the host-side buffer unit, the buffer unit pointed to by descriptor 3 of queue 1 is used to store the remaining 904 bytes of message 1. The buffer unit pointed to by descriptor 4 can fully store the 1000-byte length of message 2. Therefore, the message and descriptor processing order is as follows: Read the remaining message data of message 1 in the message storage module 1 of the message storage memory (RAM), and read the descriptor 3 in the descriptor storage FIFO at the same time, and send the remaining message data of message 1 to the cache unit pointed to by descriptor 3. The corresponding DPU executes Figure 4 Step ⑦; Since the message 1 of queue 1 has been completely read out from the message storage memory (RAM), the value of the storage unit corresponding to queue 1 in the descriptor read number memory (RAM) is reduced by 1. At this time, the value of the storage unit corresponding to queue 1 in the descriptor read number memory (RAM) becomes 1, and the corresponding DPU executes Figure 4 Step 9; Read the message 2 data in the message storage memory (RAM), read the descriptor 4 in the descriptor storage FIFO at the same time, and send the message 2 data to the cache unit pointed to by descriptor 4. The corresponding DPU executes Figure 4 Step ⑦; Since both descriptors have been used, set bit0 of the read wait bitmap to 1, and the corresponding DPU executes Figure 4 Step ⑧; Since the message 2 of queue 1 has been completely read out from the message storage memory (RAM), the value of the storage unit corresponding to queue 1 in the descriptor read number memory (RAM) is reduced by 1. At this time, the value of the storage unit corresponding to queue 1 in the descriptor read number memory (RAM) becomes 0, then the bit0 of the message valid bitmap is set to 0, indicating that the DPU has no message in queue 1, and the corresponding DPU executes Figure 4 Step 9.

[0043] Another embodiment of the present application further provides a data processing unit (DPU), which can be used to implement the European method for sending messages in the above embodiment. The DPU includes a descriptor number determination module 1, a descriptor reading module 2, and a message sending module 3. The descriptor number determination module 1 is used to obtain the number of messages currently cached in the data processing unit by the target queue, and determine the number of descriptor reads according to the number of messages; The descriptor reading module 2 is used to read the number of descriptors through a single PCIE read operation; The message sending module 3 is used to write the message of the target queue into the host-side cache unit pointed to by the descriptor; wherein, each time a message of the target queue is written into the host-side cache unit, the number of cached messages of the target queue is reduced by one; The descriptor number determination module 1 is further configured to determine the number of descriptor reads again based on the number of messages in the target queue currently cached, if all the descriptors currently read have been used and not all the messages in the target queue currently cached have been written into the host-side cache unit; The descriptor reading module 2 is further configured to read a re-determined number of descriptors through a single PCIE read operation; The message sending module 3 is further configured to write the remaining messages of the target queue currently cached into the host-side cache unit pointed to by the descriptor read again.

[0044] In some embodiments, the descriptor number determination module 1 is configured to determine the number of messages in the target queue as the number of descriptor reads.

[0045] In some embodiments, the DPU further includes a queue scheduling module, which is used to determine any queue as a queue to be scheduled if there is a message in any queue currently cached and any queue needs to read a descriptor, and schedule all currently scheduled queues to determine the target queue.

[0046] In some embodiments, the queue scheduling module is used to obtain a message valid bitmap value and a read wait bitmap value of any queue, perform an AND operation on the message valid bitmap value and the read wait bitmap value, and determine whether to determine any queue as a queue to be scheduled based on the AND operation result; Among them, the message valid bitmap value indicates whether any of the queues has cached messages; the read wait bitmap value indicates whether any of the queues needs to read the descriptor; if there is a message of any of the queues currently cached, the message valid bitmap value of any of the queues is set to 1, otherwise it is set to 0; if any of the queues needs to read the descriptor, the read wait bitmap value of any of the queues is set to 1, otherwise it is set to 0.

[0047] In some embodiments, the DPU also includes a message receiving module, which is used to receive messages from any queue, cache the messages from any queue into a message storage module corresponding to any queue, and update the storage value in the message number cache unit corresponding to any queue, where the storage value is the number of messages of any queue currently cached.

[0048] In some embodiments, the descriptor reading module 2 is further configured to store the read descriptor into a descriptor FIFO module after reading the corresponding descriptor, and the descriptor FIFO module performs dequeue management on the descriptors stored in the descriptor FIFO module according to a first-in-first-out principle.

[0049] In some embodiments, the DPU further includes a message memory including multiple message modules corresponding one-to-one to multiple queues, a message number memory including multiple message number storage units corresponding one-to-one to multiple queues, the message valid bitmap, the read wait bitmap, and the descriptor FIFO module.

[0050] It should be noted that the data processing unit of this embodiment corresponds to the method of the above embodiment. The contents not described in detail in the data processing unit of this embodiment can be obtained by referring to the contents of the embodiment method, and will not be repeated in this embodiment.

[0051] Another embodiment of the present application provides a data processing unit, including: Communication interface, used for communicating with other electronic devices; a memory for storing computer program instructions; The processor is configured to execute the computer program instructions to support the data processing unit in implementing the method according to the above embodiment.

[0052] In this embodiment, the memory primarily includes a program storage area and a data storage area. The program storage area can store operating devices, applications required for at least one function, and the data storage area can store related data. Furthermore, the memory can be a high-speed random access memory or a non-volatile memory, such as a plug-in hard drive, a Smart Media Card (SMC), a Secure Digital (SD) card, or a Flash Card. Alternatively, the memory can be other volatile solid-state memory devices.

[0053] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor, or the processor may be any conventional processor. The processor is the control center of the data processing unit and uses various interfaces and lines to connect the various parts of the data processing unit.

[0054] Another embodiment of the present application provides a network processor, including a Virtio driver and the data processing unit described in the above embodiment, wherein the Virtio driver runs on a host side and is at least used to generate the descriptor.

[0055] Another embodiment of the present application provides a computer program product, including computer program instructions, wherein the computer program instructions instruct a computer device to execute operations corresponding to the message sending method described in the above embodiment.

[0056] Specifically, the computer program product includes a series of computer program instructions. These computer program instructions are codes written in a computer program that define how to perform specific operations. These computer program instructions are designed to be loaded onto a computer device and instruct the device to perform specific operations, which are the steps in the message sending method described in the above embodiment. In this way, the computer program product of this embodiment provides a complete software solution that can be run on various computer devices to implement the message sending method described in the above embodiment.

[0057] While various embodiments of the present application have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technological improvements in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A message sending method, applied to a data processing unit, characterized in that: The method comprises: Obtaining the number of messages currently cached in the data processing unit by the target queue, and determining the number of descriptor reads according to the number of messages; Reading the number of descriptors through a single PCIE read operation; Writing the message of the target queue into the host-side cache unit pointed to by the descriptor; wherein, each time a message of the target queue is written into the host-side cache unit, the number of currently cached messages corresponding to the target queue is reduced by one; If all the read descriptors have been used and not all the messages of the target queue have been written into the host-side cache unit, the number of descriptor reads is determined again based on the number of current cached messages corresponding to the target queue, and the re-determined number of descriptors is read through a single PCIE read operation, and the remaining messages of the target queue are written into the host-side cache unit pointed to by the re-read descriptors until all the cached messages corresponding to the target queue are written into the host-side cache unit.

2. The method according to claim 1, characterized in that Determining the number of descriptor reads according to the number of messages includes: The current number of messages in the target queue is determined as the number of descriptor reads.

3. The method according to claim 2, characterized in that The method further comprises: If any queue in the data processing unit has a message to be written to the host side cached and any queue needs to read a descriptor, the any queue is determined as a queue to be scheduled, and all current queues to be scheduled are scheduled to determine the target queue.

4. The method according to claim 3, characterized in that The method further comprises: Obtain the message valid bitmap value and read wait bitmap value of any of the queues, perform an AND operation on the message valid bitmap value and the read wait bitmap value, and determine whether to determine any of the queues as the queue to be scheduled based on the AND operation result; wherein, the message valid bitmap value indicates whether any of the queues has a cached message; the read wait bitmap value indicates whether any of the queues needs to read a descriptor; if any of the queues has a corresponding cached message, the message valid bitmap value of any of the queues is set to 1, otherwise it is set to 0; if any of the queues needs to read a descriptor, the read wait bitmap value of any of the queues is set to 1, otherwise it is set to 0.

5. The method according to claim 1, wherein The method further comprises: Receive messages from any queue, cache the messages from any queue in a message storage module corresponding to any queue, and update a message quantity value in a message quantity cache unit corresponding to any queue.

6. A data processing unit, characterized in that: It includes a descriptor number determination module, a descriptor reading module and a message sending module; The descriptor number determination module is used to obtain the number of messages currently cached in the data processing unit by the target queue, and determine the number of descriptor reads according to the number of messages; The descriptor reading module is used to read the number of descriptors through a single PCIE read operation; The message sending module is used to write the message of the target queue into the host-side cache unit pointed to by the descriptor; wherein, each time a message of the target queue is written into the host-side cache unit, the number of cached messages of the target queue is reduced by one; The descriptor number determination module is further configured to determine the number of descriptor reads again based on the number of messages in the target queue currently cached, if all the descriptors currently read have been used and not all the messages in the target queue currently cached have been written into the host-side cache unit; The descriptor reading module is further configured to read a re-determined number of descriptors through a single PCIE read operation; The message sending module is further configured to write the remaining messages in the target queue into the host-side cache unit pointed to by the descriptor read again.

7. The data processing unit according to claim 6, characterized in that The descriptor number determination module is used to determine the number of messages in the target queue as the descriptor reading number.

8. The data processing unit according to claim 7, characterized in that The data processing unit also includes a queue scheduling module, which is used to determine any queue as a queue to be scheduled if any queue in the data processing unit has a message to be written to the host side cached and any queue needs to read a descriptor, and schedule all current queues to be scheduled to determine the target queue.

9. The data processing unit according to claim 8, characterized in that The queue scheduling module is used to obtain a message valid bitmap value and a read wait bitmap value of any queue, perform an AND operation on the message valid bitmap value and the read wait bitmap value, and determine whether to determine any queue as a queue to be scheduled based on the AND operation result; Among them, the message valid bitmap value indicates whether any of the queues has cached messages; the read wait bitmap value indicates whether any of the queues needs to read the descriptor; if there is a message of any of the queues currently cached, the message valid bitmap value of any of the queues is set to 1, otherwise it is set to 0; if any of the queues needs to read the descriptor, the read wait bitmap value of any of the queues is set to 1, otherwise it is set to 0.

10. The data processing unit according to claim 6, characterized in that The data processing unit also includes a message receiving module, which is used to receive messages from any queue, cache the messages from any queue in the message storage module corresponding to any queue, and update the message number value in the message number cache unit corresponding to any queue.

11. A data processing unit, characterized in that: include: Communication interface, used for communicating with other electronic devices; a memory for storing computer program instructions; A processor, configured to execute the computer program instructions to support the data processing unit in implementing the method according to any one of claims 1 to 5.

12. A network processor, characterized in that: The method comprises a Virtio driver and the data processing unit according to any one of claims 6 to 10, wherein the Virtio driver runs on a host side and is at least used to generate the descriptor.

13. A computer program product, characterized in that The method comprises computer program instructions, wherein the computer program instructions instruct a computer device to perform operations corresponding to the method according to any one of claims 1 to 5.

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