Phase-switching dual-mode frequency divider and frequency synthesizer including the frequency divider
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A phase switching, dual-mode frequency divider technology, applied in pulse counters, automatic power control, counting chain pulse counters, etc., to achieve the effect of saving chip area and high speed
What is AI technical title?
AI technical title is built by PatSnap AI team. It summarizes the technical point description of the patent document.
A phase switching, dual-mode frequency divider technology, applied in pulse counters, automatic power control, counting chain pulse counters, etc., to achieve the effect of saving chip area and high speed
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[0032] figure 1 A block diagram showing a receiver that can be used for the IEEE 802.11a standard. figure 1 The upper part of , shows the antenna ANT connected to the low noise amplifier LNA, which is connected to the first and second mixers MI, MQ, which in turn are connected to the analog-to-digital converter ADC. figure 1 The lower part shows the implementation of the PLL circuit. The PLL circuit includes a voltage oscillator VCO, a first divide-by-2 circuit, a frequency divider PS, a phase frequency detector PFD, a reference crystal Xtal, a charge pump CP and a low-pass filter LPF. The output of the divide-by-2 circuit is coupled to first and second mixers MI, MQ.
[0033] The frequency divider PS will be described in more detail below.
[0034] figure 2 show figure 1 Block diagram of the frequency divider in . The programmable frequency divider includes a 16 / 17 frequency divider 10, a buffer 20, a frequency divider 30, a decision unit 40, a synchronization unit...
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PUM
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Abstract
A phase-switching dual modulus prescaler having a dual modulus divider is provided. Said divider comprises a first and second divide-by-2 circuit (A;B), wherein said second divide-by-2 circuit (B) is coupled to the output of said first divide-by-2 circuit (A) and at least said second divide-by-two circuit (B) comprises a four phase output each separated by 90°. A phase selection unit (PSU) is provided for selecting one of the four phase outputs (Ip, In, Qp, Qn; INi, INni, INq, Innq) of the second divide-by-2 circuit (B). Moreover, a phase control unit is provided for providing control signal (C1, NC0; C2, NC2; C3, NC3) to the phase selection unit, wherein the phase selection unit (PSU) performs the selection of the four phase outputs (Ip, In, Qp, Qn; INi, INni, INq, Innq) according to the control signals (C0, NC0; C1, NC1; C2, NC2). Said phase selection unit (PSU) is implemented based on direct logic. The implementation of the phase selection unit based on direct logic enables a higher speed and saves area on the chip.
Description
technical field [0001] The present invention relates to a phase-switched dual-mode frequency prescaler, and a frequency synthesizer. Background technique [0002] The Phase Locked Loop (PLL) method for frequency synthesis is the most common method for generating high frequency oscillations in modern communication equipment. A programmable frequency synthesizer is a device capable of generating a signal with a frequency selected from a range of frequencies. A programmable frequency synthesizer utilizes a digital phase-locked loop circuit that uses a voltage-controlled oscillator, VCO, to generate an output signal. The PLL includes a feedback and control loop that monitors the frequency of the synthesizer output signal, compares its frequency to that of a reference signal, and controls the VCO to adjust the frequency of the synthesizer output signal. In most cases a digital frequency divider, also known as a frequency divider, in the feedback section of the loop divides the...
Claims
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