Chip fault positioning device and server

Abstract

The utility model provides a chip fault positioning device and a server, and relates to the technical field of fault positioning, the device comprises a host end, an enabling control circuit and an I2C link switch circuit, the enabling control circuit is connected with the host end; the I2C link switch circuit is connected with micro-control units (MCUs) in the at least two GPU modules, the enabling control circuit and the host end, and the I2C link switch circuit is used for enabling the host end to be in communication connection with the MCUs corresponding to the GPU modules based on enabling control signals; the MCU is respectively connected with at least two artificial intelligence AI chips in the GPU module; and the host end is used for generating a fault positioning signal based on the heartbeat signal corresponding to each AI chip connected with the MCU. According to the utility model, rapid positioning of the fault AI chip can be realized under the unattended condition, and the later maintenance efficiency is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of fault location, and in particular to a chip fault location device and a server. Background Art

[0002] AI (Artificial Intelligence) technology is very popular in today's society, and many AI servers or hyper-converged devices have been derived. The GPU (Graphics Processing Unit) module inside the AI ​​server or hyper-converged device is used to implement AI functions. Figure 1 As shown in the figure, generally an AI server or hyper-converged device includes multiple GPU modules, which can achieve high computing power and make AI technology more intelligent. The GPU module contains multiple AI chips, so an AI server or hyper-converged device may contain dozens of AI chips. There is a high probability that dozens of AI chips will fail during operation. Therefore, how to quickly locate the faulty AI chip in the faulty GPU module of the whole machine is an urgent problem to be solved.

[0003] In the prior art, it can be achieved by Figure 2 The AI ​​accelerator card shown implements fault diagnosis through the PCIe (Peripheral Component Interconnect express) bus protocol. Figure 2 When performing fault diagnosis on the AI ​​accelerator card shown in the figure, the PCIe structure tree must remain unchanged. Once the PCIe structure tree changes, it becomes more difficult to locate the faulty GPU module. At the same time, the PCIe-to-serial port chip and PCIe-to-I2C chip involved in the AI ​​accelerator card have low universality and high cost, which further leads to low efficiency in subsequent maintenance. Utility Model Content

[0004] The utility model provides a chip fault locating device and a server, which are used to solve the defects of how to quickly locate the faulty AI chip and the low efficiency of subsequent maintenance in the prior art, and realize the rapid location of the faulty AI chip in an unattended situation, thereby improving the efficiency of subsequent maintenance.

[0005] The utility model provides a chip fault locating device, comprising: a host end, an enabling control circuit and an I2C link switch circuit, wherein:

[0006] The enable control circuit is connected to the host end; the host end is used to generate a positioning control signal, and the enable control circuit is used to generate an enable control signal based on the positioning control signal; the enable control signal is used to control the on-off state of the I2C link switch circuit;

[0007] The I2C link switch circuit is connected to the microcontroller unit MCU in at least two graphics processor GPU modules, the enable control circuit and the host end. The I2C link switch circuit is used to enable the host end to communicate with the MCU corresponding to each GPU module based on the enable control signal; the MCU is respectively connected to at least two artificial intelligence AI chips in the GPU module to which it belongs; the host end is used to generate a fault location signal based on the heartbeat signal corresponding to each AI chip connected to the MCU.

[0008] According to the chip fault locating device provided by the utility model, the I2C link switch circuit includes at least two switch control circuits, and the switch control circuits correspond to the MCU one by one;

[0009] For each of the switch control circuits, the first enable terminal corresponding to the switch control circuit is connected to the output terminal of the enable control circuit, the first data terminal and the first clock terminal corresponding to the switch control circuit are both connected to the host terminal, and the second data terminal and the second clock terminal corresponding to the switch control circuit are both connected to the MCU corresponding to the switch control circuit.

[0010] According to the chip fault locating device provided by the utility model, the switch control circuit includes a first switch control subcircuit and a second switch control subcircuit, wherein:

[0011] The first enable terminals corresponding to the first switch control subcircuit and the second switch control subcircuit are both used as the first enable terminals corresponding to the switch control circuit;

[0012] The first data terminal corresponding to the first switch control subcircuit serves as the first data terminal of the switch control circuit, and the second data terminal corresponding to the first switch control subcircuit serves as the second data terminal of the switch control circuit;

[0013] The first clock terminal corresponding to the second switch control subcircuit serves as the first clock terminal of the switch control circuit, and the second clock terminal corresponding to the second switch control subcircuit serves as the second clock terminal of the switch control circuit.

[0014] According to the chip fault locating device provided by the utility model, the first switch control subcircuit includes MOS transistor Q1, MOS transistor Q2, MOS transistor Q3, resistor R1, resistor R2, resistor R3 and capacitor C1, wherein:

[0015] The base of the MOS tube Q1 serves as the first enable terminal of the first switch control subcircuit, the source of the MOS tube Q1 is grounded, the drain of the MOS tube Q1 is connected to the power supply terminal, one end of the resistor R1, one end of the capacitor C1, one end of the resistor R2, the base of the MOS tube Q2, the base of the MOS tube Q3 and one end of the resistor R3, the other end of the capacitor C1 and the other end of the resistor R2 are grounded, the source of the MOS tube Q2 serves as the first data terminal of the first switch control subcircuit, the drain of the MOS tube Q2 is connected to the drain of the MOS tube Q3, the source of the MOS tube Q3 is connected to the other end of the resistor R3, and the source of the MOS tube Q3 serves as the second data terminal of the first switch control subcircuit.

[0016] According to the chip fault locating device provided by the utility model, the second switch control subcircuit includes MOS transistor Q4, MOS transistor Q5, MOS transistor Q6, resistor R4, resistor R5 and capacitor C2, wherein:

[0017] The base of the MOS tube Q4 serves as the first enable terminal of the second switch control subcircuit, the source of the MOS tube Q4 is grounded, the drain of the MOS tube Q4 is connected to the power supply terminal, one end of the resistor R4, one end of the capacitor C2, the base of the MOS tube Q5, the base of the MOS tube Q6 and one end of the resistor R5, the other end of the capacitor C2 is grounded, the source of the MOS tube Q5 serves as the first clock terminal of the second switch control subcircuit, the drain of the MOS tube Q5 is connected to the drain of the MOS tube Q6, the source of the MOS tube Q6 is connected to the other end of the resistor R5, and the source of the MOS tube Q6 serves as the second clock terminal of the second switch control subcircuit.

[0018] According to the chip fault locating device provided by the utility model, the enabling control circuit includes a complex programmable logic device CPLD register and a decoder, wherein:

[0019] The input end of the CPLD register is connected to the second enable end corresponding to the host end, the output end of the CPLD register is connected to the input end of the decoder, and at least two output ends of the decoder serve as at least two output ends of the enable control circuit. The at least two output ends of the decoder correspond one-to-one to the at least two switch control circuits.

[0020] According to the chip fault locating device provided by the utility model, the CPLD register is connected to the host end for communication based on the LPC protocol.

[0021] According to the chip fault locating device provided by the utility model, for each of the MCUs, each of the AI ​​chips in the corresponding GPU module is connected to at least two input / output I / O pins of the MCU, and the AI ​​chip corresponds to the I / O pins one by one.

[0022] The utility model also provides a server, comprising: at least two graphics processing unit (GPU) modules and a chip fault locating device as described in any one of the above items, each of the GPU modules being connected to the chip fault locating device.

[0023] According to the server provided by the utility model, for each of the GPU modules, the GPU module includes a microcontroller unit MCU and at least two artificial intelligence AI chips, and the MCU is respectively connected to the chip fault locating device and the at least two AI chips.

[0024] The chip fault locating device and server provided by the utility model embed a highly universal MCU in a GPU module, and access an enabling control circuit through a host side, so that the enabling control circuit controls the switching state of an I2C link switch circuit, and after the enabling control circuit controls the I2C link switch circuit to be turned on, the host side is connected to the MCU connected to the I2C link switch circuit for communication, and through communication between the host side and the MCU, the faulty chip is located from at least two AI chips connected to the MCU, so that the faulty AI chip can be quickly located in an unattended situation, the troubleshooting time can be reduced, the efficiency of later maintenance can be improved, and the cost of the chip fault locating device and the space shortage of the single board layout in the GPU module can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 It is a structural diagram of a server provided by the prior art;

[0027] Figure 2 This is a connection diagram of an AI acceleration card provided by the prior art;

[0028] Figure 3 This is one of the structural schematic diagrams of the chip fault locating device provided by the embodiment of the utility model;

[0029] Figure 4 This is the second structural schematic diagram of the chip fault locating device provided by the embodiment of the utility model;

[0030] Figure 5 is a circuit diagram of a first switch control subcircuit provided in an embodiment of the utility model;

[0031] Figure 6 is a circuit diagram of a second switch control subcircuit provided in an embodiment of the utility model;

[0032] Figure 7 This is the third structural schematic diagram of the chip fault locating device provided in the embodiment of the utility model.

[0033] Reference numerals:

[0034] 110: host end; 120: enable control circuit; 121: CPLD register; 122: decoder; 130: I2C link switch circuit; 131: switch control circuit; 1311: first switch control subcircuit; 1312: second switch control subcircuit; 140: MCU; 200: GPU module; 210: AI chip. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the utility model clearer, the technical solution of the utility model will be described clearly and completely in conjunction with the drawings in the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0036] In view of the problem of how to quickly locate the faulty AI chip 210 in the prior art and the low efficiency of subsequent maintenance, the embodiment of the utility model provides a chip fault location device. Figure 3 FIG. 1 is one of the structural diagrams of the chip fault location device provided by the embodiment of the utility model. Figure 3 As shown, the chip fault location device includes: a host end 110, an enable control circuit 120 and an I2C link switch circuit 130, wherein:

[0037] The enable control circuit 120 is connected to the host end 110; the host end 110 is used to generate a positioning control signal, and the enable control circuit 120 is used to generate an enable control signal based on the positioning control signal; the enable control signal is used to control the on / off state of the I2C link switch circuit 130;

[0038] The I2C link switch circuit 130 is connected to the MCU (Micro Controller Unit) 140 in at least two GPU (Graphics Processing Unit) modules 200, the enable control circuit 120 and the host end 110. The I2C link switch circuit 130 is used to enable the host end 110 to communicate with the MCU 140 corresponding to each GPU module based on the enable control signal; the MCU 140 is respectively connected to at least two AI (Artificial Intelligence) chips 210 in the GPU module 200 to which it belongs; the host end 110 is used to generate a fault location signal based on the heartbeat signal corresponding to each AI chip 210 connected to the MCU 140.

[0039] Specifically, in the embodiment of the utility model, when locating a chip fault, the host end 110 generates a positioning control signal by polling, and sends the positioning control signal to the enable control circuit 120. Since the I2C addresses of the MCUs 140 in the GPU modules 200 in the same server are the same address, the enable control circuit 120 and the I2C link switch circuit 130 are set in the chip fault locating device, and the positioning control signal is used as the input signal of the enable control circuit 120, so that the enable control circuit 120 generates an enable control signal, and sends the enable control signal to the I2C link switch circuit 130. Since the I2C link switch circuit 130 is connected to the host end 110 and each MCU 140 respectively, the enable control signal can control the on and off of the corresponding switch control circuit 131 in the I2C link switch circuit 130, thereby establishing a communication connection between the host end 110 and the corresponding MCU 140, that is, realizing access to the same I2C address. In addition, the MCU 140 in the GPU module 200 can collect the heartbeat signals corresponding to at least two AI chips 210 in the GPU module 200. If the AI ​​chip 210 works normally, the AI ​​chip 210 will continue to send heartbeat signals to the MCU 140. If the AI ​​chip 210 is faulty, the AI ​​chip 210 stops sending heartbeat signals to the MCU 140. Therefore, after establishing a communication connection between the host end 110 and the corresponding MCU 140, the host end 110 can obtain and analyze the heartbeat signals corresponding to each AI chip 210 collected by the corresponding MCU 140. The AI ​​chip 210 corresponding to the missing heartbeat signal is the faulty chip, thereby realizing rapid positioning of the chip fault.

[0040] Optionally, a first logic judgment circuit may be provided in the host end 110. After establishing a communication connection between the host end 110 and the corresponding MCU 140, the MCU 140 may input the heartbeat signal corresponding to each AI chip 210 into the first logic judgment circuit. The first logic judgment circuit may be a first AND gate. When the host end 110 polls each AI chip 210, the heartbeat signal of each AI chip may be input into the first input end of the first AND gate. For example, when the AI ​​chip 210 works normally, the heartbeat signal input into the first input end of the first AND gate is a high level signal 1. When the AI ​​chip 210 fails, the heartbeat signal input into the first input end of the first AND gate is a low level signal 0. The second input end is a preset signal, and the preset signal is a high level signal 1. Therefore, if the AI ​​chip 210 works normally, the output signal of the first AND gate is a high-level signal 1, that is, the fault location signal generated by the host end 110 is a high-level signal 1; if the AI ​​chip 210 fails, the output signal of the first AND gate is a low-level signal, that is, the fault location signal generated by the host end 110 is a low-level signal 0.

[0041] In addition, the MCU 140 can also generate a chip status signal based on the heartbeat signal corresponding to each AI chip 210. The chip status signal is obtained by splicing at least two binary signals. The number of bits of the chip status signal is the same as the number of AI chips 210 connected to the MCU 140, and the arrangement order is also the same. The host end 110 can generate a fault location signal by judging the binary signal at the corresponding position, that is, determine the AI ​​chip 210 that has failed. For example, the chip status signal sent by the MCU 140 is 11110111, and the host end 110 can judge that the 4th binary signal is 0, which means that the 4th AI chip 210 connected to the MCU 140 is a faulty chip, and then generate a corresponding fault location signal, which may include the location and status of the faulty chip.

[0042] It should be noted that a second logic judgment circuit may be provided in the MCU 140, and after each AI chip 210 sends a corresponding heartbeat signal to the MCU 140, the heartbeat signal may be sent to the second logic judgment circuit. The second logic judgment circuit may include at least two second AND gates, and the at least two second AND gates correspond to at least two AI chips 210 one by one, and the second input end of each second AND gate is a preset signal, and the preset signal is a high level signal 1. For any AI chip 210, the AI ​​chip 210 may transmit the heartbeat signal to the first input end of the corresponding second AND gate. When the AI ​​chip 210 works normally, the heartbeat signal input to the first input end of the second AND gate is a high level signal 1, and when the AI ​​chip 210 fails, the heartbeat signal input to the first input end of the second AND gate is a low level signal 0. After combining the preset signal, it can be determined that when the AI ​​chip 210 works normally, the binary signal output by the second AND gate is a high level signal 1, and when the AI ​​chip 210 fails, the binary signal output by the second AND gate is a low level signal 0. After sequentially splicing the binary signals of the second AND gates, the MCU 140 can generate chip status signals corresponding to all AI chips 210. After establishing a communication connection between the host end 110 and the corresponding MCU 140, the MCU 140 can send the chip status signal to the host end 110.

[0043] Optionally, after establishing a communication connection between the host end 110 and the corresponding MCU 140 and quickly locating the faulty chip, the host end 110 can send a reset instruction to the corresponding MCU 140 through the I2C link switch circuit 130, and the MCU 140 can execute the reset instruction to hard reset the faulty chip, thereby achieving self-recovery of the faulty chip.

[0044] Optionally, the host end 110 may be a CPU (Central Processing Unit) or an FPGA (Field Programmable Gate Array), etc., which is not limited in the embodiment of the present utility model.

[0045] Furthermore, for each of the MCUs 140, each of the AI ​​chips 210 in the corresponding GPU module 200 is connected to at least two I / O (Input / Output) pins of the MCU 140, and the AI ​​chip 210 corresponds one-to-one to the I / O pins.

[0046] For example, if the GPU module 200A includes 8 AI chips 210, the MCU 140 in the GPU module 200A includes 8 I / O pins, and each AI chip 210 is connected to each I / O pin of the MCU 140. When the second AI chip 210 fails, the host end 110 sends a positioning control signal to the enable control circuit 120, and the enable control circuit 120 generates an enable control signal according to the positioning control signal. Through the enable control signal, the second switch control circuit 131 in the I2C link switch circuit 130 corresponding to the GPU module 200A is turned on, thereby connecting the I2C link between the host end 110 and the GPU module 200A, so that the host end 110 and the MCU 140 are in communication connection. Afterwards, the host side 110 obtains and analyzes the heartbeat signals of each AI chip 210 collected by the MCU 140 in the GPU module 200A. Since the heartbeat signal is missing in the second pin of the MCU 140 or the number of pulses of the heartbeat signal is less than the number of pulses of the heartbeat signal of other I / O pins, it is determined that the second I / O pin of the MCU 140 is faulty, and the AI ​​chip 210 connected to the second I / O pin is determined to be a faulty chip.

[0047] Further, Figure 4 This is a second structural diagram of the chip fault locating device provided by the embodiment of the utility model, such as Figure 4 As shown, the I2C link switch circuit 130 includes at least two switch control circuits 131, and the switch control circuits 131 correspond to the MCU 140 one by one;

[0048] For each of the switch control circuits 131, the first enable terminal corresponding to the switch control circuit 131 is connected to the output terminal of the enable control circuit 120, the first data terminal and the first clock terminal corresponding to the switch control circuit 131 are both connected to the host terminal 110, and the second data terminal and the second clock terminal corresponding to the switch control circuit 131 are both connected to the MCU 140 corresponding to the switch control circuit 131.

[0049] Specifically, the I2C link switch circuit 130 includes a plurality of switch control circuits 131, and the number of the switch control circuits 131, the number of the MCUs 140, the number of the GPU modules 200, and the number of the output terminals of the enable control signal are all equal, that is, the first enable terminal of a switch control circuit 131 is connected to an output terminal of the enable control circuit 120, and at the same time, the switch control circuit 131 is connected to the corresponding MCU 140 through the second data terminal and the second clock terminal. In addition, each switch control circuit 131 is connected to the host terminal 110 through the first data terminal and the second clock terminal. When locating a chip fault, the host terminal 110 sends a positioning control signal to the enable control circuit 120, and the enable control circuit 120 determines the target switch control circuit 131 from all the switch control circuits 131 through the positioning control signal, that is, determines the target output terminal from each output terminal of the enable control circuit 120, and determines the switch control circuit 131 connected to the target output terminal as the target switch control circuit 131. Afterwards, an enable control signal is output to the target switch control circuit 131 through the target output terminal. The target switch control circuit 131 is turned on by the enable control signal, and then the host end 110 communicates with the MCU 140 connected to the target switch control circuit 131 through the turned-on target switch control circuit 131.

[0050] It should be noted that the structures of the switch control circuits 131 are the same, and each switch control circuit 131 is respectively connected to the host end 110 and the corresponding MCU 140 through the I2C bus, that is, each switch control circuit 131 is connected to the host end 110 through SDA (Serial Data, data signal line) and SCL (Serial Clock, clock signal line), and at the same time, each switch control circuit 131 is connected to the MCU 140 through SDA and SCL.

[0051] Furthermore, the switch control circuit 131 includes a first switch control subcircuit 1311 and a second switch control subcircuit 1312, wherein:

[0052] The first enable terminals CPLD_EN corresponding to the first switch control subcircuit 1311 and the second switch control subcircuit 1312 are both used as the first enable terminals corresponding to the switch control circuit 131;

[0053] The first data terminal I2C_SDA corresponding to the first switch control subcircuit 1311 serves as the first data terminal of the switch control circuit 131, and the second data terminal I2C_SDA_Q corresponding to the first switch control subcircuit 1311 serves as the second data terminal of the switch control circuit 131;

[0054] The first clock terminal corresponding to the second switch control subcircuit 1312 serves as the first clock terminal of the switch control circuit 131 , and the second clock terminal corresponding to the second switch control subcircuit 1312 serves as the second clock terminal of the switch control circuit 131 .

[0055] Specifically, each switch control circuit 131 includes a first switch control subcircuit 1311 and a second switch control subcircuit 1312, wherein the first switch control subcircuit 1311 corresponds to SDA in the I2C bus, that is, the first data terminal I2C_SDA of the first switch control subcircuit 1311 is connected to the host terminal 110, and the second data terminal I2C_SDA_Q of the first switch control subcircuit 1311 is connected to the corresponding MCU 140, and the first switch control subcircuit 1311 is used to transmit data signals between the host terminal 110 and the corresponding MCU 140. The second switch control subcircuit 1312 corresponds to SCL in the I2C bus, that is, the first clock terminal I2C_SCL of the second switch control subcircuit 1312 is connected to the host terminal 110, and the second clock terminal I2C_SCL_Q of the second switch control subcircuit 1312 is connected to the corresponding MCU 140, and the second switch control subcircuit 1312 is used to transmit clock signals between the host terminal 110 and the corresponding MCU 140. In addition, before transmitting data signals and clock signals between the host end 110 and the corresponding MCU 140, the host end 110 also needs to transmit the enable control signal to the first enable end CPLD_EN corresponding to the first switch control subcircuit 1311 and the second switch control subcircuit 1312 through the enable control circuit 120, and control the first switch control subcircuit 1311 and the second switch control subcircuit 1312 to be turned on through the enable control signal, thereby establishing a communication connection between the host end 110 and the corresponding MCU 140, realizing communication between the host end 110 and the corresponding MCU 140, and further quickly locating the faulty chip.

[0056] Further, Figure 5 is a circuit diagram of the first switch control subcircuit 1311 provided in an embodiment of the present utility model, such as Figure 5 As shown, the first switch control subcircuit 1311 includes MOS transistor Q1, MOS transistor Q2, MOS transistor Q3, resistor R1, resistor R2, resistor R3 and capacitor C1, wherein:

[0057] The base of the MOS transistor Q1 serves as the first enable terminal CPLD_EN of the first switch control sub-circuit 1311, the source of the MOS transistor Q1 is grounded, the drain of the MOS transistor Q1 is connected to the power supply terminal VDD3V3, one end of the resistor R1, one end of the capacitor C1, one end of the resistor R2, the base of the MOS transistor Q2, the base of the MOS transistor Q3 and one end of the resistor R3, the other end of the capacitor C1 and the other end of the resistor R2 are grounded, the source of the MOS transistor Q2 serves as the first data terminal I2C_SDA of the first switch control sub-circuit 1311, the drain of the MOS transistor Q2 is connected to the drain of the MOS transistor Q3, the source of the MOS transistor Q3 is connected to the other end of the resistor R3, and the source of the MOS transistor Q3 serves as the second data terminal I2C_SDA_Q of the first switch control sub-circuit 1311.

[0058] Specifically, when the enable control signal received by the first enable terminal CPLD_EN of the first switch control sub-circuit 1311 is a high-level signal, that is, the base of the MOS transistor Q1 is a high-level signal, so that the MOS transistor Q1 is turned on, and the ground terminal pulls down the drain of the MOS transistor Q1 to a low-level signal, thereby making the bases corresponding to the MOS transistors Q2 and Q3 low-level signals, so that the MOS transistors Q2 and Q3 are both in a cut-off state, thereby making the first data terminal I2C_SDA and the second data terminal I2C_SDA_Q in a disconnected state, that is, making the host terminal 110 and the MCU 140 connected to the first switch control sub-circuit 1311 in a disconnected state. In the case where the enable control signal received by the first enable terminal CPLD_EN of the first switch control subcircuit 1311 is a low-level signal, that is, the base of the MOS transistor Q1 is a low-level signal, so that the MOS transistor Q1 is in a cut-off state, and the power supply terminal VDD3V3 pulls the drain of the MOS transistor Q1 to a high-level signal, thereby making the bases corresponding to the MOS transistors Q2 and Q3 high-level signals, so that the MOS transistors Q2 and Q3 are both in a conducting state, thereby making the first data terminal I2C_SDA and the second data terminal I2C_SDA_Q in a connected state, that is, making the host terminal 110 and the MCU 140 connected to the first switch control subcircuit 1311 in a connected state, and establishing a communication connection between the host terminal 110 and the corresponding MCU 140.

[0059] Further, Figure 6 is a circuit diagram of the second switch control subcircuit 1312 provided in an embodiment of the present utility model, such as Figure 6 As shown, the second switch control subcircuit 1312 includes MOS transistor Q4, MOS transistor Q5, MOS transistor Q6, resistor R4, resistor R5 and capacitor C2, wherein:

[0060] The base of the MOS transistor Q4 serves as the first enable terminal CPLD_EN of the second switch control sub-circuit 1312, the source of the MOS transistor Q4 is grounded, the drain of the MOS transistor Q4 is connected to the power supply terminal, one end of the resistor R4, one end of the capacitor C2, the base of the MOS transistor Q5, the base of the MOS transistor Q6 and one end of the resistor R5, the other end of the capacitor C2 is grounded, the source of the MOS transistor Q5 serves as the first clock terminal I2C_SCL of the second switch control sub-circuit 1312, the drain of the MOS transistor Q5 is connected to the drain of the MOS transistor Q6, the source of the MOS transistor Q6 is connected to the other end of the resistor R5, and the source of the MOS transistor Q6 serves as the second clock terminal I2C_SCL_Q of the second switch control sub-circuit 1312.

[0061] Specifically, when the enable control signal received by the first enable terminal CPLD_EN of the second switch control subcircuit 1312 is a high-level signal, that is, the base of the MOS transistor Q4 is a high-level signal, so that the MOS transistor Q4 is turned on, and the ground terminal pulls down the drain of the MOS transistor Q4 to a low-level signal, thereby making the bases corresponding to the MOS transistors Q5 and Q6 low-level signals, so that the MOS transistors Q5 and Q6 are both in a cut-off state, thereby making the first clock terminal I2C_SCL and the second clock terminal I2C_SCL_Q in a disconnected state, that is, making the host terminal 110 and the MCU 140 connected to the second switch control subcircuit 1312 in a disconnected state. When the enable control signal received by the first enable terminal CPLD_EN of the second switch control subcircuit 1312 is a low-level signal, that is, the base of the MOS transistor Q4 is a low-level signal, so that the MOS transistor Q4 is in a cut-off state, and the power supply terminal VDD3V3 pulls the drain of the MOS transistor Q4 to a high-level signal, thereby making the bases corresponding to the MOS transistors Q5 and Q6 high-level signals, so that the MOS transistors Q5 and Q6 are both in a conducting state, thereby making the first clock terminal I2C_SCL and the second clock terminal I2C_SCL_Q in a connected state, that is, making the host terminal 110 and the MCU 140 connected to the second switch control subcircuit 1312 in a connected state, and establishing a communication connection between the host terminal 110 and the corresponding MCU 140.

[0062] It should be noted that MOS transistors Q1 to Q6 are all NMOS transistors, and a body diode is provided between the source and drain of each NMOS transistor in MOS transistors Q1 to Q6. In addition, the first switch control subcircuit 1311 and the second switch control subcircuit 1312 are respectively connected to the same MCU 140.

[0063] Further, Figure 7This is the third structural diagram of the chip fault locating device provided by the embodiment of the utility model, such as Figure 7 As shown, the enabling control circuit 120 includes a complex programmable logic device CPLD register 121 and a decoder 122, wherein:

[0064] The input end of the CPLD register 121 is connected to the second enable end corresponding to the host end 110, the output end of the CPLD register 121 is connected to the input end of the decoder 122, at least two output ends of the decoder 122 serve as at least two output ends of the enable control circuit 120, and at least two output ends of the decoder 122 correspond one-to-one to the at least two switch control circuits 131.

[0065] Specifically, the CPLD register 121 is connected to the host end 110 in communication based on the LPC protocol, and the host end 110 can control the I2C link switch circuit 130 by accessing the CPLD register 121. At the same time, due to the problem of limited I / O resources in the CPLD in the X86 platform, by using the decoder 122, it is possible to achieve the function of controlling multiple switch control circuits 131 in the I2C link switch circuit 130 with fewer I / O ports, that is, at least two output ends of the CPLD register 121 can control at least two output ends of the decoder 122, and the number of output ends of the decoder 122 is greater than the number of output ends of the CPLD register 121.

[0066] Optionally, the decoder 122 can be a 2-line-4-line decoder 122, a 3-line-8-line decoder 122, a 4-line-16-line decoder 122, etc. The decoder 122 can be selected according to the number of GPU modules 200 included in the server. For example, if the number of GPU modules 200 is less than or equal to 4, the decoder 122 can select a 2-line-4-line decoder 122; if the number of GPU modules 200 is greater than 4 and less than or equal to 8, the decoder 122 can select a 3-line-8-line decoder 122; if the number of GPU modules 200 is greater than 8 and less than or equal to 16, the decoder 122 can select a 4-line-16-line decoder 122.

[0067] For example, taking the decoder 122 as a 3-line to 8-line decoder 122 and the number of GPU modules 200 as 8, the decoder 122 includes 3 input terminals and 8 output terminals, that is, the CPLD register 121 includes 3 output terminals, each output terminal of the CPLD is connected to each input terminal of the decoder 122, the I2C link switch circuit 130 includes 8 switch control circuits 131, each output terminal of the decoder 122 is connected to the first enable terminal of each switch control circuit 131, and the host end 110 outputs a positioning control signal by accessing the CPLD register 121. The positioning control signal is a three-bit binary number. After the positioning control signal is output from the CPLD register 121 to the decoder 122, the decoder 122 outputs an eight-bit binary number. The positioning control signal and the input signal and output signal of the decoder 122 are shown in Table 1. It should be noted that the valid signals in the output signals of the decoder 122 in Table 1 are low-level signals. For example, when the positioning control signal and the input signal of the decoder 122 are both 000, the signal of the first output terminal Y0 in the output signal of the decoder 122 is a low-level signal, that is, the enable control signal controls the first switch control circuit 131 in the I2C link switch circuit 130 to be turned on, thereby enabling the host end 110 to communicate with the MCU 140 in the first GPU module 200.

[0068] Table 1

[0069]

[0070] The chip fault locating device provided by the utility model embeds a MCU 140 with high universality in a GPU module 200, and accesses an enabling control circuit 120 through a host end 110, so that the enabling control circuit 120 controls the switching state of an I2C link switch circuit 130, and after the enabling control circuit 120 controls the I2C link switch circuit 130 to be turned on, the host end 110 is connected to the MCU 140 connected to the I2C link switch circuit 130 for communication, and through the communication between the host end 110 and the MCU 140, the faulty chip is located from at least two AI chips 210 connected to the MCU 140, so that the faulty AI chip 210 can be quickly located in an unattended state, the troubleshooting time can be reduced, the efficiency of later maintenance can be improved, and the cost of the chip fault locating device can be reduced. Meanwhile, compared with the prior art, only one MCU 140 is embedded in the GPU module 200, so that the space occupied by the GPU module 200 is small, and the space tension of the single board layout in the GPU module 200 is further reduced.

[0071] An embodiment of the utility model further provides a server, comprising: at least two graphics processing unit (GPU) modules and a chip fault locating device as described in any one of the above items, each of the GPU modules being connected to the chip fault locating device.

[0072] Optionally, the server may be an AI server or a hyper-converged device, which is not limited in the embodiments of the present invention.

[0073] Furthermore, for each of the GPU modules, the GPU module includes a microcontroller unit MCU and at least two artificial intelligence AI chips, and the MCU is respectively connected to the chip fault locating device and the at least two AI chips.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the utility model.

Claims

1. A chip fault locating device, characterized in that: include: Host side, enable control circuit and I2C link switch circuit, where: The enabling control circuit is connected to the host end; The host end is used to generate a positioning control signal, and the enable control circuit is used to generate an enable control signal based on the positioning control signal; the enable control signal is used to control the on / off state of the I2C link switch circuit; The I2C link switch circuit is connected to the microcontroller unit MCU in at least two graphics processor GPU modules, the enable control circuit and the host end. The I2C link switch circuit is used to enable the host end to communicate with the MCU corresponding to each GPU module based on the enable control signal; the MCU is respectively connected to at least two artificial intelligence AI chips in the GPU module to which it belongs; the host end is used to generate a fault location signal based on the heartbeat signal corresponding to each AI chip connected to the MCU.

2. The chip fault locating device according to claim 1, characterized in that: The I2C link switch circuit includes at least two switch control circuits, and the switch control circuits correspond to the MCUs one by one; For each of the switch control circuits, the first enable terminal corresponding to the switch control circuit is connected to the output terminal of the enable control circuit, the first data terminal and the first clock terminal corresponding to the switch control circuit are both connected to the host terminal, and the second data terminal and the second clock terminal corresponding to the switch control circuit are both connected to the MCU corresponding to the switch control circuit.

3. The chip fault locating device according to claim 2, characterized in that: The switch control circuit comprises a first switch control subcircuit and a second switch control subcircuit, wherein: The first enable terminals corresponding to the first switch control subcircuit and the second switch control subcircuit are both used as the first enable terminals corresponding to the switch control circuit; The first data terminal corresponding to the first switch control subcircuit serves as the first data terminal of the switch control circuit, and the second data terminal corresponding to the first switch control subcircuit serves as the second data terminal of the switch control circuit; The first clock terminal corresponding to the second switch control subcircuit serves as the first clock terminal of the switch control circuit, and the second clock terminal corresponding to the second switch control subcircuit serves as the second clock terminal of the switch control circuit.

4. The chip fault locating device according to claim 3, characterized in that: The first switch control subcircuit includes a MOS transistor Q1, a MOS transistor Q2, a MOS transistor Q3, a resistor R1, a resistor R2, a resistor R3 and a capacitor C1, wherein: The base of the MOS tube Q1 serves as the first enable terminal of the first switch control subcircuit, the source of the MOS tube Q1 is grounded, the drain of the MOS tube Q1 is connected to the power supply terminal, one end of the resistor R1, one end of the capacitor C1, one end of the resistor R2, the base of the MOS tube Q2, the base of the MOS tube Q3 and one end of the resistor R3, the other end of the capacitor C1 and the other end of the resistor R2 are grounded, the source of the MOS tube Q2 serves as the first data terminal of the first switch control subcircuit, the drain of the MOS tube Q2 is connected to the drain of the MOS tube Q3, the source of the MOS tube Q3 is connected to the other end of the resistor R3, and the source of the MOS tube Q3 serves as the second data terminal of the first switch control subcircuit.

5. The chip fault locating device according to claim 3, characterized in that: The second switch control subcircuit includes MOS transistor Q4, MOS transistor Q5, MOS transistor Q6, resistor R4, resistor R5 and capacitor C2, wherein: The base of the MOS tube Q4 serves as the first enable terminal of the second switch control subcircuit, the source of the MOS tube Q4 is grounded, the drain of the MOS tube Q4 is connected to the power supply terminal, one end of the resistor R4, one end of the capacitor C2, the base of the MOS tube Q5, the base of the MOS tube Q6 and one end of the resistor R5, the other end of the capacitor C2 is grounded, the source of the MOS tube Q5 serves as the first clock terminal of the second switch control subcircuit, the drain of the MOS tube Q5 is connected to the drain of the MOS tube Q6, the source of the MOS tube Q6 is connected to the other end of the resistor R5, and the source of the MOS tube Q6 serves as the second clock terminal of the second switch control subcircuit.

6. The chip fault locating device according to any one of claims 1 to 5, characterized in that: The enabling control circuit includes a complex programmable logic device (CPLD) register and a decoder, wherein: The input end of the CPLD register is connected to the second enable end corresponding to the host end, the output end of the CPLD register is connected to the input end of the decoder, and at least two output ends of the decoder serve as at least two output ends of the enable control circuit. The at least two output ends of the decoder correspond one-to-one to the at least two switch control circuits.

7. The chip fault locating device according to claim 6, characterized in that: The CPLD register is connected to the host end for communication based on the LPC protocol.

8. The chip fault locating device according to any one of claims 1 to 5, characterized in that: For each of the MCUs, each of the AI ​​chips in the corresponding GPU module is connected to at least two input / output I / O pins of the MCU, and the AI ​​chip corresponds to the I / O pins one by one.

9. A server, characterized in that: include: At least two graphics processing unit (GPU) modules and a chip fault locating device as claimed in any one of claims 1 to 8, each of the GPU modules being connected to the chip fault locating device.

10. The server according to claim 9, characterized in that For each of the GPU modules, the GPU module includes a microcontroller unit MCU and at least two artificial intelligence AI chips, and the MCU is respectively connected to the chip fault locating device and the at least two AI chips.

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