Embedded semiconductor packaging structure
By using a multi -layer structure of layers of metal layers and insulating graphene layers on the chip base of high -power components, and combined with a dielectric layer to cover the chip and conductive interconnection layer, it solves the short circuit caused by the lack of insulating layer of the metal material base. The problem realizes higher insulation ability and lower cost.
Patent Information
- Application Number
- CN202421135362.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-23
- Publication Date
- 2025-01-24
- Estimated Expiration
- 2034-05-23
AI Technical Summary
In the application field of high-power components or equipment, metal materials lack insulating layers as the base of power chips, resulting in bridging short circuits due to foreign matters during manufacturing or transportation, resulting in electrical failure, and higher specifications of protection are required Dust and cleaning mechanisms to increase costs.
The multi -layer structure is used as the base of the chip, including layers of metal layers and insulating graphene layers to increase the ability of insulation and cover the chip and conductive interconnection layer through the first and second media layers. To achieve electrical connection.
Effectively increase the insulation ability of embedded semiconductor packaging structure, reduce the short -circuit risk of bridge caused by foreign objects, avoid electrical failure, and reduce the cost while maintaining the heat dissipation ability.
Smart Images
Figure CN222394805U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a semiconductor package, in particular to an embedded semiconductor package structure. Background Art
[0002] Technology brings convenience to our lives. Semiconductor technology is not only an important basic technology, but also the backbone of modern society. The development of every technology industry is inseparable from the use of semiconductor chips, including computers, mobile communications, transportation, industrial equipment and other fields.
[0003] In the application field of high-power components or equipment, metal materials such as copper or aluminum are often used as the base of the power chip due to the need for a fast heat dissipation solution. On the other hand, they can be used as a heat conduction medium. However, under this structure, the base of the power chip has no insulation layer. During the manufacturing or transportation process, it is easy to be attached with foreign matter, resulting in a short circuit with the surrounding conductive circuits or components, thus posing the risk of electrical failure. Therefore, a higher standard of dust prevention and cleaning mechanism must be relied on to reduce the situation of foreign matter attachment, but this will also lead to a significant increase in costs.
[0004] Therefore, how to provide an embedded semiconductor packaging structure to avoid the above problems is one of the current important issues. Utility Model Content
[0005] An object of the present invention is to provide an embedded semiconductor packaging structure, which can increase the insulation capacity of the chip module therein and reduce the risk of electrical failure caused by bridging short circuits due to foreign matter adhesion.
[0006] To achieve the above-mentioned purpose, the utility model provides an embedded semiconductor packaging structure, which includes a base, a chip, a first conductive interconnection layer and a first dielectric layer. The base has a stacked first metal layer and an insulating graphene layer. The chip is arranged and combined on the first metal layer of the base. The first conductive interconnection layer is arranged on the first metal layer and the chip. The first dielectric layer covers the first metal layer of the base and covers the chip and the first conductive interconnection layer. A portion of an upper surface of the first conductive interconnection layer is exposed to the first dielectric layer.
[0007] In one embodiment, the base further has a second metal layer, and the insulating graphene layer is sandwiched between the first metal layer and the second metal layer.
[0008] In one embodiment, the first conductive interconnect layer has at least one first conductive column and at least one second conductive column, the first conductive column is disposed on the first metal layer of the base, and the second conductive column is disposed on an electrode of the chip.
[0009] In one embodiment, the embedded semiconductor package structure further includes a second conductive interconnect layer and a second dielectric layer. The second conductive interconnect layer is disposed on the first dielectric layer and electrically connected to the portion of the first conductive interconnect layer exposed to the first dielectric layer. The second dielectric layer covers the first dielectric layer and the second conductive interconnect layer and exposes a portion of an upper surface of the first conductive interconnect layer.
[0010] In one embodiment, the second conductive interconnect layer includes a patterned conductive circuit and / or at least one electrical connection pad.
[0011] In one embodiment, the chip is a power chip.
[0012] In one embodiment, the embedded semiconductor package structure can meet the electrical environment of 400V or 100KW or above.
[0013] As mentioned above, the embedded semiconductor packaging structure of the present invention adds an insulating graphene layer to the base for insulation and heat dissipation purposes. It is stacked with the metal layer of the base to increase the insulation capacity of the embedded semiconductor packaging structure to avoid the adhesion of foreign matter during the manufacturing process or transportation process, resulting in a bridge short circuit with the surrounding conductive circuits or components, thereby causing electrical failure. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 It is a schematic diagram showing an embedded semiconductor package structure according to the first embodiment of the utility model.
[0015] Figure 2 It is a schematic diagram showing an embedded semiconductor package structure according to the second embodiment of the present invention. DETAILED DESCRIPTION
[0016] In order to enable those skilled in the art to understand the contents of the present invention and to implement the contents of the present invention accordingly, appropriate embodiments and drawings are described as follows.
[0017] Please refer to Figure 1 As shown, an embedded semiconductor package structure 10 according to the first embodiment of the present invention includes a base 11 , a chip 12 , a first conductive interconnection layer 13 , a first dielectric layer 14 , a second conductive interconnection layer 15 , a second dielectric layer 16 and a bonding element 17 .
[0018] The base (or chip base) 11 has a first surface S11a and a second surface S11b disposed opposite to each other. The base 11 is a multi-layer structure, which sequentially has a first metal layer 111, an insulating graphene layer 112 and a second metal layer 113. The insulating graphene layer 112 is sandwiched between the first metal layer 111 and the second metal layer 113. In this embodiment, the materials of the first metal layer 111 and the second metal layer 113 are, for example, but not limited to, copper.
[0019] The chip 12 has a first surface 121 and an opposite second surface 122. The first surface 121 of the present embodiment is an active side having a first electrode E12a and a second electrode E12b, and the second surface 122 is not provided with electrodes. In other embodiments, the second surface 122 may also be provided with electrodes, which is not limited here, and in this embodiment, the first metal layer 111 of the base 11 may be a patterned conductive circuit layer. The second surface 122 of the chip 12 can be connected to the first surface S11a of the base 11 through the bonding element 17. The bonding element 17 may be selected to include but not limited to adhesive glue, solder, conductive bumps, conductive glue, conductive silver glue, etc. depending on whether the second surface 122 of the chip 12 needs to be electrically connected. The chip 12 may be a processing chip, a memory chip or a power chip, etc., wherein the power chip may be a chip that can meet high voltage and high power of more than 400V or more than 100KW. In other embodiments, the chip 12 may also be other semiconductor components, which is not limited here.
[0020] The first conductive interconnection layer 13 is disposed on a portion of the first surface S11a of the base 11 and the first electrode E12a and the second electrode E12b of the chip 12. In this embodiment, the first conductive interconnection layer 13 includes first conductive pillars 131a, 131b and second conductive pillars 132a, 132b, wherein the first conductive pillars 131a, 131b are disposed on the first metal layer 111, and the second conductive pillars 132a, 132b are respectively disposed on the first electrode E12a and the second electrode E12b of the chip 12. The material of the first conductive interconnection layer 13 includes, but is not limited to, copper.
[0021] The first dielectric layer 14 covers the first surface S11a of the base 11, the chip 12 and the first conductive interconnection layer 13. An upper surface S13a of the first conductive interconnection layer 13 is exposed to an upper surface S14a of the first dielectric layer 14. The material of the first dielectric layer 14 includes but is not limited to photosensitive or non-photosensitive insulating materials, such as ABF (Ajinomoto Build-up Film), photosensitive resin, polyimide (Polyimide, referred to as PI), bismaleimide triazine (Bismaleimide Triazine, referred to as BT), FR5 prepreg (Prepreg, referred to as PP), molding resin (Molding Compound), or molded epoxy resin (Epoxy Molding Compound, referred to as EMC), etc.
[0022] The second conductive interconnection layer 15 is disposed on a portion of the upper surface S14a of the first dielectric layer 14 and the exposed upper surface S13a of the first conductive interconnection layer 13. The second conductive interconnection layer 15 may include but is not limited to patterned conductive lines 151 and electrical connection pads 152. The material of the second conductive interconnection layer 15 includes but is not limited to copper.
[0023] The second dielectric layer 16 is disposed on the first dielectric layer 14 and covers the second conductive interconnection layer 15. An upper surface S15a of a portion of the second conductive interconnection layer 15 is exposed to an upper surface S16a of the second dielectric layer 16, and the exposed upper surface S15a of the second conductive interconnection layer 15 is an electrical connection pad that can be used for external electrical connection. The material of the second dielectric layer 16 includes but is not limited to photosensitive or non-photosensitive insulating materials, such as ABF (Ajinomoto Build-up Film), photosensitive resin, polyimide (PI), bismaleimide triazine (BT), FR5 prepreg (PP), molding resin (Molding Compound), or molded epoxy resin (EMC).
[0024] Next, please refer to Figure 2 As shown, an embedded semiconductor package structure 20 according to the second embodiment of the present invention includes a base 21 , a chip 22 , a first conductive interconnection layer 23 , a first dielectric layer 24 , a second conductive interconnection layer 25 , a second dielectric layer 26 and a bonding element 27 .
[0025] The base 21 has a first surface S21a and a second surface S21b disposed opposite to each other. The base 21 is a double-layer structure, which has a metal layer 211 and an insulating graphene layer 212. The first surface S21a is a side close to the metal layer 211, and the second surface S21b is a side close to the insulating graphene layer 212. In this embodiment, the material of the metal layer 211 is, for example, but not limited to, copper.
[0026] The chip 22 has a first surface 221 and an opposite second surface 222. The first surface 221 is an active surface having a first electrode E22a and a second electrode E22b, while the second surface 222 is not provided with electrodes. However, in other embodiments, the second surface 222 may also be provided with electrodes, which is not limited here. In this embodiment, the metal layer 211 of the base 21 may be a patterned conductive circuit layer. The second surface 222 of the chip 22 may be connected to the first surface S21a of the base 21 through a bonding element 27. The bonding element 27 may be selected to include but not limited to adhesive glue, solder, conductive bumps, conductive glue or conductive silver glue, depending on whether the second surface 222 of the chip 22 has a need for electrical connection. The chip 22 may be a processing chip, a memory chip or a power chip, wherein the power chip may be a high voltage and high power chip that can meet 400V or more or 100KW or more.
[0027] The first conductive interconnection layer 23 is disposed on a portion of the first surface S21a of the base 21 and the first electrode E22a and the second electrode E22b of the chip 22. In this embodiment, the first conductive interconnection layer 23 includes first conductive pillars 231a, 231b and second conductive pillars 232a, 232b, wherein the first conductive pillars 231a, 231b are disposed on the metal layer 211, and the second conductive pillars 232a, 232b are respectively disposed on the first electrode E22a and the second electrode E22b of the chip 22. The material of the first conductive interconnection layer 23 includes, but is not limited to, copper.
[0028] The first dielectric layer 24 covers the first surface S21a of the base 21, the chip 22 and the first conductive interconnection layer 23. An upper surface S23a of the first conductive interconnection layer 23 is exposed to an upper surface S24a of the first dielectric layer 24. The material of the first dielectric layer 24 includes but is not limited to photosensitive or non-photosensitive insulating materials, such as ABF (Ajinomoto Build-up Film), photosensitive resin, polyimide (PI), bismaleimide triazine (BT), FR5 prepreg (PP), molding compound, or molded epoxy (EMC).
[0029] The second conductive interconnect layer 25 is disposed on a portion of the upper surface S24a of the first dielectric layer 24 and the exposed upper surface S23a of the first conductive interconnect layer 23. The second conductive interconnect layer 25 may include but is not limited to patterned conductive lines 251 and electrical connection pads 252. The material of the second conductive interconnect layer 25 includes but is not limited to copper.
[0030] The second dielectric layer 26 is disposed on the first dielectric layer 24 and covers the second conductive interconnection layer 25. An upper surface S25a of the second conductive interconnection layer 25 is partially exposed to an upper surface S26a of the second dielectric layer 26, and the exposed upper surface S25a of the second conductive interconnection layer 25 can be used as an electrical connection pad for external electrical connection. The material of the second dielectric layer 26 includes but is not limited to photosensitive or non-photosensitive insulating materials, such as ABF (Ajinomoto Build-up Film), photosensitive resin, polyimide (Polyimide, referred to as PI), bismaleimide triazine (Bismaleimide Triazine, referred to as BT), FR5 prepreg (Prepreg, referred to as PP), molding resin (Molding Compound), or molded epoxy resin (Epoxy Molding Compound, referred to as EMC), etc.
[0031] In summary, the present invention embeds the chip in the dielectric layer to form an embedded semiconductor packaging structure, and uses a multi-layer structure as the base (chip seat) of the chip, wherein the base includes a stacked metal layer and an insulating graphene layer. This can not only have heat dissipation capabilities, but also increase insulation capabilities to avoid the adhesion of foreign matter during the manufacturing process or transportation process, resulting in a short circuit with the surrounding conductive lines or components, thereby causing electrical failure.
[0032] The above embodiments are only used to list the implementation modes of the utility model and to explain the technical features of the utility model, and are not used to limit the protection scope of the utility model. Any changes or equivalent arrangements that can be easily completed by those familiar with this technology belong to the scope claimed by the utility model, and the scope of protection of the utility model shall be based on the claims.
Claims
1. An embedded semiconductor packaging structure, characterized in that: include: A base having a stacked first metal layer and an insulating graphene layer; A chip is disposed on the first metal layer bonded to the base; a first conductive interconnect layer, disposed on the first metal layer and the chip; as well as A first dielectric layer covers the first metal layer of the base and encapsulates the chip and the first conductive interconnection layer, wherein a portion of an upper surface of the first conductive interconnection layer is exposed to the first dielectric layer.
2. The embedded semiconductor package structure according to claim 1, wherein: The base further has a second metal layer, and the insulating graphene layer is sandwiched between the first metal layer and the second metal layer.
3. The embedded semiconductor package structure according to claim 1, wherein: The first conductive interconnection layer has at least one first conductive column and at least one second conductive column. The at least one first conductive column is arranged on the first metal layer of the base, and the at least one second conductive column is arranged on an electrode of the chip.
4. The embedded semiconductor package structure according to claim 1, wherein: The embedded semiconductor package structure further comprises: a second conductive interconnect layer disposed on the first dielectric layer and electrically connected to a portion of the first conductive interconnect layer exposed to the first dielectric layer; and A second dielectric layer covers the first dielectric layer and the second conductive interconnection layer and exposes a portion of an upper surface of the second conductive interconnection layer.
5. The embedded semiconductor package structure according to claim 4, characterized in that: The second conductive interconnect layer includes a patterned conductive circuit and / or at least one electrical connection pad.
6. The embedded semiconductor package structure according to claim 1, wherein: The chip is a power chip.