Detection circuit based on power system transistor driving

Abstract

The utility model discloses a detection circuit based on power system transistor driving, which comprises a signal input circuit and a direct current bias circuit, the signal input circuit and the direct current bias circuit are both electrically connected with a differential reduction circuit, the differential reduction circuit is electrically connected with an isolation operational amplifier module, and the isolation operational amplifier module is electrically connected with a differential proportion circuit. The differential proportion circuit is electrically connected with the comparator; the differential proportion circuit and the comparator are electrically connected with an MCU. The direct current bias circuit, the differential reduction circuit, the isolation operational amplifier module, the differential proportion circuit and the MCU are all electrically connected with the DCDC isolation system. The sampling isolation voltage operational amplifier ensures that the system is safe and reliable; single power supply sampling is adopted, the cost is reduced, expansion is facilitated, and the detection cost can be greatly reduced when a system needs to detect driving circuits of multiple transistors at the same time; reference voltage is added to the in-phase end through operational amplifier following, and noise interference is reduced.

Description

Technical Field

[0001] The utility model relates to the field of electricity, in particular to a detection circuit based on transistor drive of an electric power system. Background Art

[0002] In the power electronics industry, a large number of transistors are needed for frequency modulation and buck-boost conversion in ACDC and DCAC bridge conversion circuits of products such as frequency converters and inverters. Before the equipment is put into load test operation, it is often necessary to test the driving circuit of the transistor to ensure that each transistor can be turned on and off normally and quickly. The driving voltage of each transistor GS is a relative voltage, that is, it is not common to the ground. Therefore, isolated sampling is required when performing transistor drive detection to ensure that the circuit is safe and reliable and does not interfere with each other. The transistor conduction condition generally requires the gate-source voltage to reach the conduction voltage (generally 10-20V), and in order to make the transistor respond quickly to shutdown, designers often use negative voltage to turn off the transistor. This requires our detection circuit to have the ability to isolate and detect positive and negative voltages and frequencies.

[0003] The current solutions are as follows:

[0004] 1. Scheme 1 Figure 1 As shown in the figure, the measurement signal is directly connected to the measurement device through the differential amplifier after the current limiting and voltage reduction by a large resistor. In this solution, the driving signals are not isolated but also share the ground through the amplifier. If a signal fails, it will not only affect or even burn the measurement equipment, but also damage the product under test.

[0005] 2. Scheme 2 Figure 2 The measurement signal shown is sampled using an isolated op amp plus a dual supply op amp, or as Figure 3 As shown, an isolated op amp with positive and negative sampling is used. This solution can ensure that the driving signals of each channel are isolated from each other and will not interfere with the subsequent circuits and the circuit under test. However, it increases the economic cost. After all, a negative power charge pump costs at least 4 yuan, and an isolated op amp with positive and negative sampling is 4 times the price of an ordinary isolated op amp. Once the number of transistors in the system under test is too large, the cost will increase linearly.

[0006] 3. Scheme 3 Figure 4 As shown, a single-power op amp is used, and the input signal and DC bias are connected to the op amp's non-inverting terminal; the biggest problem with this circuit is that resistor noise is introduced, while reducing the impedance of the non-inverting input. Utility Model Content

[0007] In order to solve the above technical problems, the utility model proposes a detection circuit based on power system transistor drive.

[0008] The purpose of the utility model is achieved through the following technical solutions:

[0009] A detection circuit based on power system transistor drive, comprising a signal input circuit and a DC bias circuit, the signal input circuit and the DC bias circuit are both electrically connected to a differential reduction circuit, the differential reduction circuit is electrically connected to an isolation operational amplifier module, the isolation operational amplifier module is electrically connected to a differential proportional circuit, the differential proportional circuit is electrically connected to a comparator; the differential proportional circuit and the comparator are both electrically connected to an MCU; the DC bias circuit, the differential reduction circuit, the isolation operational amplifier module, the differential proportional circuit and the MCU are all electrically connected to a DCDC isolation system;

[0010] The differential reduction circuit includes a first operational amplifier U1A; the signal input circuit and the DC bias circuit are electrically connected to the 2nd and 3rd pins of the first operational amplifier U1A respectively, and the 1st pin of the first operational amplifier U1A is electrically connected to the isolation operational amplifier module through the current limiting resistor R5; the differential proportional circuit includes a second operational amplifier U2, and the 2nd and 3rd pins of the second operational amplifier U2 are electrically connected to the 6th and 7th pins of the isolation operational amplifier module respectively; the 1st pin of the second operational amplifier U2 is electrically connected to the comparator.

[0011] As a further improvement, the signal input circuit includes a signal input port J1, the first pin of the signal input port J1 is connected in series with the first resistor R1 and the second resistor R2 in sequence, and then electrically connected to the second pin of the first operational amplifier U1A and one end of the third resistor R3, the other end of the third resistor R3 is electrically connected to the first pin of the first operational amplifier U1A and one end of the current limiting resistor R5; the power supply of the first operational amplifier U1A is electrically connected to the output power supply of the DCDC isolation system, the positive pole is electrically connected to +5V_1, and the negative pole is connected to 0V_1.

[0012] As a further improvement, the isolation op amp module includes a first chip UG1, the second pin of the first chip UG1 is electrically connected to the other end of the current limiting resistor R5 and one end of the seventh capacitor C7, the other end of the seventh capacitor C7 is grounded and electrically connected to the third pin and the fourth pin of the first chip UG1; the first pin of the first chip UG1 is electrically connected to the DCDC isolation system.

[0013] A further improvement is that the comparator includes a third operational amplifier U3, a first pin of the second operational amplifier U2 is electrically connected to the fifteenth resistor R15, the fifteenth resistor R15 is electrically connected to the fourth pin of the third operational amplifier U3, one end of the thirteenth capacitor C13 and one end of the thirteenth resistor R13, the other end of the thirteenth capacitor C13 is electrically connected to the third pin of the third operational amplifier U3 and the sliding end of the sliding rheostat R16, the fixed end of one end of the sliding rheostat R16 is electrically connected to the system's 5V power supply, and the other fixed end is connected to the power ground; the positive pole of the third operational amplifier U3 is electrically connected to the system's 5V power supply, and the negative pole is connected to the power ground; the first pin of the third operational amplifier U3 is electrically connected to the other end of the thirteenth resistor R13.

[0014] As a further improvement, the DC bias circuit includes a fourth operational amplifier U1B, a seventh pin of the fourth operational amplifier U1B is electrically connected to one end of a seventh resistor R7 and one end of an eleventh resistor R11, the other end of the seventh resistor R7 is electrically connected to the third pin of the first operational amplifier U1A, and the other end of the eleventh resistor R11 is electrically connected to the sixth pin of the fourth operational amplifier U1B; a fifth pin of the fourth operational amplifier U1B is electrically connected to one end of a fourteenth resistor R14, the other end of the fourteenth resistor R14 is electrically connected to the cathode of a low-temperature drift reference source T1, the reference electrode of the low-temperature drift reference source T1, one end of an eleventh capacitor C11, one end of a twelfth capacitor C12 and one end of a twelfth resistor R12, the other end of the twelfth resistor R12 is electrically connected to a DCDC isolated output power supply; the other end of the eleventh capacitor C11 and the other end of the twelfth capacitor C12 are electrically connected to the anode of the low-temperature drift reference source T1 and are grounded.

[0015] As a further improvement, the model of the low temperature drift reference source T1 is TL432.

[0016] For further improvement, the MCU model is STM32F407.

[0017] The beneficial effects of the utility model are:

[0018] 1. Sampling isolation voltage op amp to ensure system safety and reliability.

[0019] 2. Single power supply sampling is used to reduce costs and facilitate expansion. When the system needs to detect the driving circuits of multiple transistors at the same time, the detection cost can be greatly reduced.

[0020] 3. The reference voltage is added to the in-phase terminal through the op amp follower to reduce noise interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention is further described with reference to the accompanying drawings, but the contents in the accompanying drawings do not constitute any limitation to the present invention.

[0022] Figure 1 This is the circuit diagram of the existing solution 1.

[0023] Figure 2 This is a circuit diagram of the existing solution 2 that uses an isolation op amp plus a dual-power op amp for sampling.

[0024] Figure 3 This is a circuit diagram of the existing solution 2 using an isolated operational amplifier with positive and negative sampling.

[0025] Figure 4 This is a circuit diagram of the existing solution 3.

[0026] Figure 5 It is a module diagram of the circuit of the utility model.

[0027] Figure 6 It is a specific circuit diagram of the utility model circuit.

[0028] Figure 7 This is a circuit diagram of the DCDC isolation system of the utility model. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the utility model more clear, the utility model is further described in detail below with reference to the accompanying drawings and examples.

[0030] Example 1

[0031] 1. If Figure 1 The utility model shown in the figure uses a low-cost dual op amp to follow the reference voltage, and then forms a differential signal with the measured signal as a DC bias. After being scaled down, it is connected to the isolation op amp for sampling. After the isolated output differential signal is converted into a single signal, one path is connected to the microcontroller ADC for analog-to-digital conversion, and the other path is connected to the microcontroller capture module through a comparator to generate a PWM signal. For details, see Figure 6 .

[0032] 2. The block diagram of the module circuit is as follows Figure 5 As shown, it mainly includes signal input circuit, DC bias circuit, differential reduction circuit, isolation amplifier module, differential ratio circuit, comparator, MCU and DCDC isolation system;

[0033] 3. The DC bias circuit generates a 1.25V voltage from the high-precision, low-temperature drift and low-cost TLV432 reference chip, which is followed by a set of op amps (U1B) in the dual op amp LM2904 to output the voltage V1P25_1.

[0034] 4. V1P25_1 is connected to the non-inverting terminal of a group of op amps (U1A) of LM2904, providing a 1.25V swing (virtual ground) for the single-power op amp. The input signal V1 is connected to the inverting terminal of the op amp (U1A) through the current limiting resistors R1 and R2, and is output Vo1 to the next stage after being reduced by 20 times through the feedback resistor R3.

[0035] Voltage at this time:

[0036]

[0037] 5. The isolation amplifier UG1 uses the voltage isolation amplifier chip NSI1311 of Nanochip. The peripheral components of this amplifier are simple, with low error, low temperature drift, and 0.1V-2V linear input voltage range. The input signal of Vo1 is connected to the in-phase terminal, the inverting terminal is grounded, and the output is a differential signal Vop-Von with a gain of 1.

[0038] 6. The isolated differential signal Vop-Von is connected to the pins 3 and 2 of the U2 single-power op amp TLV9061 respectively. The op amp converts the differential signal into a single signal Vo1_ADC by 1 times, and then connects it to the single-chip ADC for analog-to-digital conversion.

[0039] At this time, the voltage is: Vo1_ADC = Vo1 = 1.3125-0.05*V1;

[0040] Thus, the input voltage is: V1 = 26.25-20*Vo1_ADC;

[0041] 7. The voltage Vo1_ADC is incorporated into the inverting input terminal of the comparator TLV340. The power supply voltage +5V is connected to the non-inverting terminal of U3 after being divided by an adjustable resistor. By comparing the changes in the size of Vo1_ADC, a real-time PWM signal is output. The frequency of the input signal can be measured through the signal capture pin of the microcontroller.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model rather than to limit the protection scope of the utility model. Although the utility model is described in detail with reference to the preferred embodiments, ordinary technicians in this field should understand that the technical solution of the utility model can be modified or replaced by equivalents without departing from the essence and scope of the technical solution of the utility model.

Claims

1. A detection circuit based on power system transistor drive, characterized in that: It includes a signal input circuit and a DC bias circuit, the signal input circuit and the DC bias circuit are both electrically connected to a differential reduction circuit, the differential reduction circuit is electrically connected to an isolation operational amplifier module, the isolation operational amplifier module is electrically connected to a differential proportional circuit, and the differential proportional circuit is electrically connected to a comparator; the differential proportional circuit and the comparator are both electrically connected to an MCU; the DC bias circuit, the differential reduction circuit, the isolation operational amplifier module, the differential proportional circuit and the MCU are all electrically connected to a DCDC isolation system; The differential reduction circuit comprises a first operational amplifier (U1A); the signal input circuit and the DC bias circuit are electrically connected to the second and third pins of the first operational amplifier (U1A), respectively; the first pin of the first operational amplifier (U1A) is electrically connected to the isolation operational amplifier module through a current limiting resistor (R5); the differential proportional circuit comprises a second operational amplifier (U2); the second and third pins of the second operational amplifier (U2) are electrically connected to the sixth and seventh pins of the isolation operational amplifier module, respectively; and the first pin of the second operational amplifier (U2) is electrically connected to the comparator.

2. The detection circuit based on power system transistor drive according to claim 1, characterized in that: The signal input circuit comprises a signal input port (J1), wherein the first pin of the signal input port (J1) is connected in series with a first resistor (R1) and a second resistor (R2) in sequence, and then electrically connected to the second pin of the first operational amplifier (U1A) and one end of a third resistor (R3), and the other end of the third resistor (R3) is electrically connected to the first pin of the first operational amplifier (U1A) and one end of a current limiting resistor (R5); the power supply of the first operational amplifier (U1A) is electrically connected to the output power supply of a DCDC isolation system, with the positive electrode electrically connected to +5V_1 and the negative electrode electrically connected to 0V_1.

3. The detection circuit based on power system transistor drive as claimed in claim 2, characterized in that: The isolation operational amplifier module comprises a first chip (UG1), a second pin of the first chip (UG1) being electrically connected to the other end of a current limiting resistor (R5) and one end of a seventh capacitor (C7), the other end of the seventh capacitor (C7) being grounded and electrically connected to a third pin and a fourth pin of the first chip (UG1); and a first pin of the first chip (UG1) being electrically connected to a DCDC isolation system.

4. The detection circuit based on power system transistor drive as claimed in claim 3, characterized in that: The comparator comprises a third operational amplifier (U3), a first pin of the second operational amplifier (U2) is electrically connected to a fifteenth resistor (R15), the fifteenth resistor (R15) is electrically connected to the fourth pin of the third operational amplifier (U3), one end of a thirteenth capacitor (C13) and one end of the thirteenth resistor (R13), the other end of the thirteenth capacitor (C13) is electrically connected to the third pin of the third operational amplifier (U3) and the sliding end of a sliding rheostat (R16), a fixed end of one end of the sliding rheostat (R16) is electrically connected to a system 5V power supply, and the other fixed end is connected to a power supply ground; the positive pole of the third operational amplifier (U3) is electrically connected to a system 5V power supply, and the negative pole is connected to a power supply ground; the first pin of the third operational amplifier (U3) is electrically connected to the other end of the thirteenth resistor (R13).

5. The detection circuit based on power system transistor drive according to claim 1, characterized in that: The DC bias circuit comprises a fourth operational amplifier (U1B), wherein the seventh pin of the fourth operational amplifier (U1B) is electrically connected to one end of a seventh resistor (R7) and one end of an eleventh resistor (R11), the other end of the seventh resistor (R7) is electrically connected to the third pin of the first operational amplifier (U1A), and the other end of the eleventh resistor (R11) is electrically connected to the sixth pin of the fourth operational amplifier (U1B); the fifth pin of the fourth operational amplifier (U1B) is electrically connected to one end of a fourteenth resistor (R14), the other end of the fourteenth resistor (R14) is electrically connected to a cathode of a low-temperature drift reference source (T1), a reference electrode of the low-temperature drift reference source (T1), one end of an eleventh capacitor (C11), one end of a twelfth capacitor (C12) and one end of a twelfth resistor (R12), and the other end of the twelfth resistor (R12) is electrically connected to a DCDC isolation power supply; the other end of the eleventh capacitor (C11) and the other end of the twelfth capacitor (C12) are electrically connected to an anode of the low-temperature drift reference source (T1) and are grounded.

6. The detection circuit based on power system transistor drive according to claim 5, characterized in that: The model of the low temperature drift reference source (T1) is TL432.

7. The detection circuit based on power system transistor drive according to any one of claims 1 to 6, characterized in that: The model of MCU is STM32F407.

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