Solid-state imaging device and data processing device

a data processing device and imaging device technology, applied in the field of solid-state imaging devices and data processing devices, can solve the problems of inability to detect defects when they occur, increase costs, etc., and achieve the effect of detecting defects in memory effectively

Inactive Publication Date: 2012-12-04
SONY CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent text describes a solid-state imaging device and a data processing device that can detect and correct defects in a memory. The device includes a pixel array unit, SRAMs, a memory control section, a defect detecting section, and a defect relieving section. The defect detecting section can detect a defective address in the SRAM and the defect relieving section can hold pixel data in the defective address and output it to the correction process section instead of writing new pixel data. This allows for effective detection and correction of defects in the memory.

Problems solved by technology

When a test is carried out as disclosed in Patent Document 1, the problem of a cost increase arises because a tester must be used.
Further, since such a test is carried out before the shipment of products, another problem arises in that defects cannot be detected when they occur after the shipment of products.

Method used

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  • Solid-state imaging device and data processing device

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first embodiment

1. First Embodiment

[0025]A solid-state imaging device according to a first embodiment of the invention will now be described with reference to the drawings.

[1-1. Configuration of Solid-State Imaging Device]

[0026]As shown in FIG. 1, a solid-state imaging device 100 of the present embodiment includes a pixel array unit 10, an image processing unit 20, a memory unit 41, a control circuit 42, a control interface 43, and an image interface 44.

[0027]The pixel array unit 10 is formed by two-dimensionally disposing a plurality of pixels each having a photoelectric conversion portion. At the pixel array unit 10, light from an object acquired through a lens (not shown) is photo-electrically converted by the plurality of pixels to accumulate electrical charge at each of the pixels according to the light impinging on the same. The pixel array unit 10 reads the electrical charge accumulated at each pixel and outputs it to the image processing unit 20 as pixel data through an A / D conversion porti...

second embodiment

2. Second Embodiment

[0136]A solid-state imaging device according to a second embodiment of the invention will now be described. In the solid-state imaging device of the first embodiment, a defect detecting process and a defect relieving process are carried out using pixel data read out from the pixel array unit 10. In the present embodiment, a defect detecting process and a defect relieving process are carried out using test data.

[0137]Four types of test data or pieces of unit data each having 10 bits, i.e., data [1111111111], [0000000000], [1010101010], and [0101010101] are used as data for testing a solid-state imaging device 100 according to the present embodiment.

[0138]Specifically, a memory unit 41 is tested using four types of test data, i.e., test data formed by consecutive 0s, test data formed by consecutive 1s, test data formed by consecutive pairs of “0” and “1” alternating in the order listed, and test data formed by consecutive pairs of “1” and “0” alternating in the ord...

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Abstract

A solid-state imaging device includes: a pixel array unit formed by two-dimensionally disposing a plurality of pixels each having a photoelectric conversion portion; one or more SRAMs; a memory control section controlling writing of pixel data sequentially output from the pixel array unit into the SRAM and controlling readout of the pixel data from the SRAM; a correction process section performing a process of correcting the pixel data read from the SRAM by the memory control section; a defect detecting section detecting a defective address in the SRAM; and a defect relieving section holding pixel data to be written in the defective address of the SRAM by the memory control section and outputting the pixel data held therein to the correction process section instead of the pixel data which has been written in the defective address of the SRAM.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a solid-state imaging device and a data processing device. More particularly, the invention relates to a solid-state imaging device and a data processing device having a memory to be used for a correction process.[0003]2. Background of the Related Art[0004]A solid-state imaging device used in a mobile telephone, a digital still camera, or the like has a memory to be used for a correction process. Various methods for testing such a memory have been proposed.[0005]For example, JP-A-2004-93421 (Patent Document 1) discloses a method approach for detecting a defective part of a memory including the step of connecting a tester to the memory to test it based on control signals from the tester.SUMMARY OF THE INVENTION[0006]When a test is carried out as disclosed in Patent Document 1, the problem of a cost increase arises because a tester must be used. Further, since such a test is carried out be...

Claims

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Application Information

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Patent Type & AuthorityPatents(United States)
IPC IPC(8): H04N5/217H04N25/00
CPCH04N5/376H04N5/378H04N25/75H04N25/74
InventorSHOYAMA, HIDEKI
OwnerSONY CORP