Array substrate and preparation method thereof, display panel, and display device

Abstract

The present invention discloses an array substrate, comprising: a photosensitive component formed on a base substrate, and a thin film transistor and a conductive layer formed on the side of the photosensitive component away from the base substrate; the photosensitive component comprises a first electrode, a photosensitive layer, and a second electrode arranged in a stacked manner, the first electrode being arranged close to the base substrate; the first electrode being electrically connected to a first electrode of the thin film transistor, and the second electrode being electrically connected to the conductive layer; wherein the first electrode is a source electrode or a drain electrode of the thin film transistor. In the array substrate of the embodiment of the present invention, during the preparation process, the photosensitive component is first formed, and then the thin film transistor is formed on the photosensitive component, thereby avoiding the influence of hydrogen element on the thin film transistor during the formation of the photosensitive component, and the source and drain layer pattern of the thin film transistor can be formed by a single graphic process, thereby simplifying the preparation process.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, a display panel, and a display device. Background Art

[0002] At present, large-size display panels are developing towards high reliability, high resolution, and high color gamut, and the requirements for the backplane preparation process are also constantly increasing. At present, compensation technology is mainly used to improve the display quality of display panels (panels). Optical sensors are built into the panel for compensation. Specifically, a photosensitive component (PIN) with a photoelectric current sensing function is combined with a thin film transistor (TFT) as a switch. It can detect real-time optical changes and then control the display panel through an external circuit.

[0003] In the existing top-gate array substrate structure, in order to prevent the channel of the TFT switch from being affected by light during the manufacturing process, Figure 1 As shown, a light shielding layer 2' is disposed on the substrate 1', and the light shielding layer 2' can be formed by patterning any metal conductive film having a light shielding function. Figure 1 In the structure shown, the photosensitive component 9' is formed on the source and drain layer. Since a large amount of hydrogen elements will be generated when the photosensitive component 9' is manufactured, and the hydrogen elements have a great influence on the electrical properties of the TFT, it is necessary to avoid the hydrogen elements from being deposited on the TFT during the manufacturing process. This requires two patterning processes to form the pattern of the source and drain layer, that is, after forming the buffer layer 7' (ILD) pattern on the gate layer 6', the source and drain layer 8' is formed. The source and drain layer 8' needs to be patterned for the first time. This patterning process retains the source and drain layer metal on the gate layer 6' of the TFT to prevent the hydrogen elements from affecting the TFT during the subsequent formation of the photosensitive component 9'. After the photosensitive component 9' is formed, the source and drain layer 8' is patterned for the second time to etch away the source and drain layer metal on the gate layer 6' of the TFT to form a complete source and drain layer pattern, and then a passivation layer 10' (PVX) is formed, and a via is formed on the passivation layer 10'. The photosensitive component 9' is connected to the external signal of the panel through the metal layer 11' at the via.

[0004] In the above process, a two-step patterning process is required to form the source and drain layer patterns, and the manufacturing process is complicated, which affects the yield of the product. Summary of the invention

[0005] The present invention provides an array substrate and a preparation method thereof, a display panel and a display device, so as to solve the problem of complex process for forming source and drain layer patterns in the prior art in the preparation of the array substrate.

[0006] In a first aspect, the present invention provides an array substrate, comprising:

[0007] A photosensitive component formed on a substrate, and a thin film transistor and a conductive layer formed on a side of the photosensitive component away from the substrate;

[0008] The photosensitive component includes a first electrode, a photosensitive layer and a second electrode which are stacked, wherein the first electrode is arranged close to the substrate; the first electrode is electrically connected to the first electrode of the thin film transistor, and the second electrode is electrically connected to the conductive layer; wherein the first electrode is the source or drain of the thin film transistor.

[0009] Optionally, the first electrode is a light shielding layer, and the first electrode covers the orthographic projection of the active layer of the thin film transistor on the base substrate.

[0010] Optionally, the conductive layer is provided in the same layer as the first electrode of the thin film transistor.

[0011] Optionally, the thin film transistor is a top gate structure.

[0012] Optionally, a stacked buffer layer and an insulating layer are formed between the first electrode and the first pole, the buffer layer is arranged close to the base substrate, a first via is arranged on the buffer layer, and a second via is arranged on the insulating layer, and the first pole is electrically connected to the first electrode through the first via and the second via.

[0013] Optionally, a third via hole is further provided on the buffer layer, a fourth via hole is further provided on the insulating layer, and the conductive layer is electrically connected to the second electrode through the third via hole and the fourth via hole.

[0014] Optionally, the material of the photosensitive layer is a PIN-type semiconductor material.

[0015] In a second aspect, the present invention further provides a method for preparing an array substrate, comprising:

[0016] forming a photosensitive component on a base substrate, the photosensitive component comprising a first electrode, a photosensitive layer and a second electrode stacked in sequence, wherein the first electrode is disposed close to the base substrate;

[0017] A thin film transistor and a conductive layer are formed on the photosensitive component, wherein the first electrode is electrically connected to a first electrode of the thin film transistor, the second electrode is electrically connected to the conductive layer, and the first electrode is a source or drain of the thin film transistor.

[0018] In a third aspect, the present invention further provides a display panel, comprising the above array substrate.

[0019] In a fourth aspect, the present invention further provides a display device, comprising the above-mentioned display panel.

[0020] Compared with the prior art, the embodiments of the present invention have the following advantages:

[0021] The array substrate of the embodiment of the present invention has a photosensitive component formed on a base substrate, and a thin film transistor and a conductive layer formed on the photosensitive component, wherein the photosensitive component includes a first electrode, a photosensitive layer, and a second electrode stacked, the first electrode is arranged close to the base substrate, the first electrode of the photosensitive component is electrically connected to the first electrode of the thin film transistor, and the second electrode of the photosensitive component is electrically connected to the conductive layer. In the preparation process, the photosensitive component is formed first, and then the thin film transistor is formed on the photosensitive component, so that the influence of hydrogen element on the thin film transistor during the formation of the photosensitive component is avoided, and the source and drain layer pattern of the thin film transistor can be formed by a single graphic process, which simplifies the preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The figure shows a schematic structural diagram of an array substrate in the prior art;

[0023] Figure 2 FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;

[0024] Figure 3 FIG. 1 is a flow chart of a method for preparing an array substrate according to an embodiment of the present invention;

[0025] Figure 4a ~e are schematic diagrams of the layer structure formed during the preparation process of the array substrate. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] like Figure 2 As shown, the array substrate of the embodiment of the present invention includes a photosensitive component 3 formed on a base substrate 1 , and a thin film transistor 5 and a conductive layer 6 formed on a side of the photosensitive component 3 away from the base substrate 1 .

[0028] The photosensitive component 3 includes a first electrode 31, a photosensitive layer 32, and a second electrode 33, which are stacked, wherein the first electrode 31 is arranged close to the base substrate 1. The first electrode 31 is electrically connected to the first electrode of the thin film transistor 5, and the second electrode 33 is electrically connected to the conductive layer 6. The first electrode is the source or drain of the thin film transistor 5.

[0029] It can be understood that the first electrode 31 of the above-mentioned photosensitive component 3 is electrically connected to the source or drain of the thin film transistor 5, the second electrode 33 is electrically connected to the conductive layer 6, the conductive layer 6 can be electrically connected to the peripheral circuit of the array substrate, and the photosensitive component 3 with photocurrent sensing function is combined with a thin film transistor 5 with a switch to form a device that can detect real-time optical changes. After being connected to the peripheral circuit through the conductive layer 6, the photosensitive component is regulated, and the display quality is improved by this compensation technology.

[0030] The array substrate of the embodiment of the present invention has a photosensitive component 3 formed on a base substrate 1, and a thin film transistor 5 and a conductive layer 6 formed on the photosensitive component 3, wherein the photosensitive component 3 includes a first electrode 31, a photosensitive layer 32, and a second electrode 33 which are stacked, and the first electrode 31 is arranged close to the base substrate 1, and the first electrode 31 of the photosensitive component 3 is electrically connected to the first electrode of the thin film transistor 5, and the second electrode 33 of the photosensitive component 3 is electrically connected to the conductive layer 6. In the preparation process, the photosensitive component 3 is formed first, and then the thin film transistor 5 is formed on the photosensitive component 3, so that the influence of hydrogen element on the thin film transistor 5 during the formation of the photosensitive component 5 is avoided, and the source and drain layer pattern of the thin film transistor 5 can be formed by a single graphic process, which simplifies the preparation process.

[0031] Specifically, Figure 2 As shown, the thin film transistor 5 is a top-gate thin film transistor as an example for description, but it can be understood that the structure of the present invention is also applicable to a bottom-gate structure.

[0032] The first electrode 31 may be a light shielding layer, and the first electrode 31 covers the positive projection of the active layer 51 of the thin film transistor 5 on the base substrate 1, which can prevent the channel of the thin film transistor 5 from being affected by the light below the base substrate 1 and deteriorating the electrical characteristics of the thin film transistor.

[0033] The first electrode 31 simultaneously functions as a light shield and an electrode of the photosensitive device, that is, the light shielding layer can be used as an electrode of the photosensitive device 3. In the preparation process, the process steps are simplified, and a light shielding electrode layer can be formed on the substrate, and the light shielding layer and the first electrode can be formed through a single patterning process.

[0034] A photosensitive layer 32 is formed on the first electrode 31. The specific material of the photosensitive layer 32 can be a PIN type semiconductor material with a thickness of about 1 um. A second electrode 33 is formed on the photosensitive layer 32. The material of the second electrode 33 can be a transparent conductive layer material such as ITO.

[0035] The specific formation process of the first electrode 31, photosensitive layer 32 and second electrode 33 of the above-mentioned photosensitive component 3 can be as follows: a first electrode layer with a shading effect is deposited on the substrate, a PIN film layer of about 1 um is deposited on the first electrode layer by chemical vapor deposition, and then a transparent conductive second electrode layer is sputtered on the PIN film layer, and then a wet etching and then dry etching process is used to form the pattern of the photosensitive component 3.

[0036] After the photosensitive component 3 is formed, a thin film transistor 5 is formed thereon. The manufacturing process of the thin film transistor 5 can refer to the existing process and will not be described in detail here.

[0037] Furthermore, the conductive layer 6 is provided in the same layer as the first electrode of the thin film transistor 5, that is, the conductive layer 6 is provided in the same layer as the source and drain layer 55 of the thin film transistor 5, and the material of the conductive layer 6 can be the same as the material of the source and drain layer 55. This structure can simplify the manufacturing process, and the pattern of the source and drain layer 55 and the pattern of the conductive layer 6 are formed simultaneously through one-step patterning. The conductive layer 6 is used to connect with the peripheral circuit of the array substrate to control the photosensitive component 3.

[0038] It is understandable that in the prior art, since the photosensitive component 5 is located above the thin film transistor 3, the hydrogen element generated during the formation of the photosensitive component 5 will affect the electrical characteristics of the thin film transistor 5. Therefore, the source and drain layers are not completely patterned before the photosensitive component 5 is formed, and the source and drain layers above the active layer of the thin film transistor are retained. After the photosensitive component is formed, the source and drain layers are patterned for the second time to form a complete source and drain layer pattern. In the present application, since the photosensitive component 5 is formed before the thin film transistor 3, when the thin film transistor 3 is subsequently formed, there is no need to consider the influence of the hydrogen element on it, and only one patterning process is required to form the source and drain layer pattern. Therefore, the manufacturing process of the present application is simpler, and the formation steps of the thin film transistor are simplified.

[0039] Specifically, a stacked buffer layer 4 and an insulating layer 54 are formed between the first electrode 31 and the first electrode of the thin film transistor 5 , that is, between the first electrode 31 and the source-drain layer 55 , wherein the buffer layer 4 is arranged close to the base substrate 1 , and the buffer layer 4 and the insulating layer 54 completely cover the photosensitive component 3 .

[0040] A first via hole is provided on the buffer layer 4, and a second via hole is provided on the insulating layer 54. The first electrode of the thin film transistor 5 is electrically connected to the first electrode 31 through the first via hole and the second via hole. Similarly, the electrical connection between the first electrode of the thin film transistor 5 and the light shielding layer is also achieved, which can improve the electrical characteristics of the thin film transistor. It can be understood that the first via hole and the second via hole can be formed by an exposure and etching process before forming the source and drain layer. While depositing the source and drain layer, the first electrode of the thin film transistor 5 is electrically connected to the first electrode 31 through the metal material of the source and drain layer.

[0041] Similarly, a third via hole is provided on the insulating layer 4 , and a fourth via hole is provided on the insulating layer 54 . The conductive layer 6 is electrically connected to the second electrode through the third via hole and the fourth via hole.

[0042] The electrical connection between the thin film transistor 5 and the photosensitive component 3 and the electrical connection between the photosensitive component 3 and the peripheral circuit of the array substrate in the embodiment of the present invention can be realized through the via holes located in the buffer layer 4 and the insulating layer 54 and the conductive source and drain layer material located in the via holes. Only one exposure and etching is required to form these four via holes and realize electrical connection. Figure 1 As shown, the source-drain layer also serves as an electrode of the photosensitive component, and the other electrode of the photosensitive component needs to be connected to the peripheral circuit through a via located thereon and then through a conductive metal, and the electrical connection between the light shielding layer and the source-drain layer requires another via to be realized, and these two vias need to be formed in two exposure etching processes. Obviously, compared with the present application, the process is more complicated. The solution of the present application is simpler in the overall design of the Array process.

[0043] The above description is based on the top-gate structure of the thin film transistor 5. It is understandable that in the bottom-gate structure, a similar structure can be used. After forming the photosensitive component 3, the thin film transistor 5 and the conductive layer 6 are formed, and any one of the source and drain electrodes of the thin film transistor 5 is electrically connected to the first electrode 31 of the photosensitive component 3, and the conductive layer 6 is electrically connected to the second electrode 33 of the photosensitive component. The patterning process of the source and drain layer pattern of the thin film transistor of the array substrate can also be simplified. The specific structure is similar to that of the above embodiment and will not be repeated here.

[0044] The present invention also provides a method for preparing an array substrate. Figure 3 As shown, the following steps are included:

[0045] Step 100: forming a photosensitive component on a base substrate. The photosensitive component includes a first electrode, a photosensitive layer, and a second electrode stacked in sequence. The first electrode is disposed close to the base substrate.

[0046] The first electrode may be a light shielding layer, and its specific formation process may be to first form a first electrode layer with a light shielding function on the base substrate 1, deposit a PIN film layer of about 1 um on the light shielding conductive layer by chemical vapor deposition, and then sputter-deposit a transparent conductive second electrode layer on the PIN film layer, and then form the pattern of the photosensitive component 3 by a process of wet etching followed by dry etching. The layer structure schematic diagram of its formation process is shown in FIG. Figure 4a As shown in ~b.

[0047] Step 200, forming a thin film transistor and a conductive layer on the photosensitive component, wherein the first electrode layer is electrically connected to the first electrode of the thin film transistor, the second electrode is electrically connected to the conductive layer, and the first electrode is the source or drain of the thin film transistor.

[0048] After completing step 100 , the thin film transistor 5 and the conductive layer 6 are formed. The conductive layer 6 can be provided at the same layer as the source and drain layer of the thin film transistor 5 .

[0049] Specifically, after completing step 100, a buffer layer 4 is chemically vapor deposited, and the material of the buffer layer can be SiOx or SiNx; an active layer 51 is deposited, and patterned to form a channel; a gate insulating layer 52 and a gate metal 53 are made, and the material of the gate insulating layer 52 can be SiOx, and the gate metal 53 can be any metal material with good conductivity, and then patterned again to form a pattern of the gate insulating layer 52 and the gate metal 53. The schematic diagram of the layer structure formed in the above process is shown in FIG. Figure 4c ~e. Then, an insulating layer 54 is deposited. The material of the insulating layer 54 can be SiOx. Before depositing the insulating layer 54, the area of ​​the active layer 51 that is not covered by the gate metal 53 and the gate insulating layer 52 needs to be conductorized. After the insulating layer 54 is formed, it is patterned to form a conductive layer 6, and a first via hole, a second via hole, a third via hole, and a fourth via hole are formed. After the via holes are completed, an active layer 55 is deposited and patterned to complete the electrical connection between the first electrode 31 and the first electrode of the thin film transistor 5, and the electrical connection between the second electrode 33 and the conductive layer 6. After completing the above steps, a subsequent passivation layer 7 can be deposited to protect the thin film transistor 5. After completing this step, a conductive layer 6 is formed. Figure 2 The structure shown.

[0050] In the method for preparing the above-mentioned array substrate, a photosensitive component 3 is first formed, and then a thin film transistor 5 is formed on the photosensitive component 3, thereby avoiding the influence of hydrogen element on the thin film transistor 5 during the formation of the photosensitive component 3. The source and drain layer pattern of the thin film transistor 5 can be formed by a single graphical treatment, thereby simplifying the preparation process.

[0051] An embodiment of the present invention further provides a display panel, comprising the array substrate of the above embodiment.

[0052] An embodiment of the present invention further provides a display device, including the display panel of the above embodiment. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, electronic paper, etc.

[0053] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0054] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0055] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An array substrate, characterized in that: include: A photosensitive component formed on a substrate, and a thin film transistor and a conductive layer formed on a side of the photosensitive component away from the substrate; The photosensitive component comprises a first electrode, a photosensitive layer and a second electrode which are stacked, wherein the first electrode is arranged close to the substrate; the first electrode is electrically connected to the first electrode of the thin film transistor, and the second electrode is electrically connected to the conductive layer; wherein the first electrode is the source electrode or the drain electrode of the thin film transistor; The first electrode is a light shielding layer, and the first electrode covers the orthographic projection of the active layer of the thin film transistor on the base substrate; A buffer layer is formed between the thin film transistor and the first electrode, and the buffer layer completely covers the photosensitive component.

2. The array substrate according to claim 1, characterized in that: The conductive layer is arranged in the same layer as the first electrode of the thin film transistor.

3. The array substrate according to claim 2, characterized in that: The thin film transistor has a top gate structure.

4. The array substrate according to claim 2, characterized in that: A stacked buffer layer and an insulating layer are formed between the first electrode and the first pole, the buffer layer is arranged close to the base substrate, a first via hole is arranged on the buffer layer, and a second via hole is arranged on the insulating layer, and the first pole is electrically connected to the first electrode through the first via hole and the second via hole.

5. The array substrate according to claim 4, characterized in that: A third via hole is further provided on the buffer layer, a fourth via hole is further provided on the insulating layer, and the conductive layer is electrically connected to the second electrode through the third via hole and the fourth via hole.

6. The array substrate according to any one of claims 1 to 5, characterized in that: The material of the photosensitive layer is a PIN type semiconductor material.

7. A method for preparing an array substrate, characterized in that: include: forming a photosensitive component on a base substrate, the photosensitive component comprising a first electrode, a photosensitive layer and a second electrode stacked in sequence, wherein the first electrode is disposed close to the base substrate; forming a thin film transistor and a conductive layer on the photosensitive component, wherein the first electrode is electrically connected to a first electrode of the thin film transistor, the second electrode is electrically connected to the conductive layer, and the first electrode is a source electrode or a drain electrode of the thin film transistor; The first electrode is a light shielding layer, and the first electrode covers the orthographic projection of the active layer of the thin film transistor on the base substrate; A buffer layer is formed between the thin film transistor and the first electrode, and the buffer layer completely covers the photosensitive component.

8. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 6.

9. A display device, characterized in that: Comprising the display panel as claimed in claim 8.

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