Vertical bonding structure, stacked chip packaging structure and method

Abstract

The present invention provides a vertical wire bonding structure, a stacked chip packaging structure and a method, including: providing a welding wire and a welding head splitting knife, the welding head splitting knife fixes the position of the welding wire and forms a solder ball at the end of the welding wire; bonding the welding wire to a set welding pad through the solder ball; moving the welding head splitting knife vertically upward along the welding wire to a set position; disconnecting the welding wire at a set cutting point below the welding head splitting knife while maintaining the cross-sectional shape of the welding wire, so as to form a vertical wire bonding structure at the set welding pad, and removing the remaining welding wires through the welding head splitting knife. The vertical wire bonding structure, the stacked chip packaging structure and the method of the present invention directly cut off the welding wire in the air without moving the welding wire, and do not change the cross-section of the welding wire. It has the advantages of easy control of the welding wire length, high signal transmission efficiency, no deviation of the welding wire position, simple operation, low cost, etc., and can greatly improve the quality of the stacked packaged chip.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and in particular to a vertical wiring structure, a stacked chip packaging structure and a method. Background Art

[0002] In recent years, "faster, smaller, cheaper, and more reliable" has become the goal to promote the development of semiconductor technology. The semiconductor manufacturing field has continuously reduced the minimum feature size and increased the packaging stack to increase the density of integrated circuits to meet the "smaller" goal. On this basis, "faster, cheaper, and more reliable" cannot be ignored.

[0003] All computing and communication systems of integrated circuits need to be powered by the power transmission subsystem. The power transmission subsystem converts the high voltage of the power supply into different voltages required by each discrete device in the integrated circuit and transmits them. In stacked packaged chips, the wires connecting each layer of chips and used to transmit power signals determine the magnitude of signal transmission loss, which poses a challenge to the machine that provides vertical leads for the upper and lower chips.

[0004] like Figure 1 to Figure 3 As shown, in the prior art, due to the limitations of the existing machine, the method for forming the vertical wire bonding structure 2 is as follows: forming a solder ball 22 at the end of the solder wire 21; bonding the solder ball 22 to the first solder pad 11; the soldering head cleaver 3 moves up a certain distance and clamps the solder wire 21, and drags the solder wire 21 to a second solder pad 12 (medium plane); applying pressure to the solder wire 21 by the soldering head cleaver 3, and grinding the solder wire 21 on the second solder pad 12 to thin the solder wire 21 at the stress point; and then vertically stretching the solder wire 21 above the first solder pad 11 by the soldering head cleaver 3, and breaking the solder wire 21 at the thinned position by external force.

[0005] However, the above method has the following problems:

[0006] 1. Since the solder ball has been bonded to the set pad, the solder wire will inevitably be deformed in the process of dragging it to the dielectric plane. Due to the large deformation, even if the solder wire is pulled vertically upward, the solder wire on the solder ball cannot be restored to be completely vertical, resulting in the upper end of the solder wire being offset, which affects the bonding quality.

[0007] 2. Since the wire is broken by reducing the stress difference by thinning the cross section of the wire, the broken end of the wire will be deformed, that is, the cross section is elliptical or linear, and the length of the deformation is related to factors such as the applied force and the diameter of the wire. There are uncertainties, so the length of the wire is not easy to control; and the deformation of the wire cross section will affect the transmission efficiency of the signal.

[0008] 3. The process of grinding the welding wire based on the dielectric plane adds additional costs.

[0009] 4. The need to grind and thin the second solder joint increases the number of process steps, which in turn increases the process time, resulting in too low WPH (wafer per hour) of the machine (if a new process method is applied, the vertical wire bonding process time can be reduced by half).

[0010] Therefore, how to simplify the preparation method of the vertical wire bonding structure based on the existing machine and improve the quality of the vertical wire bonding structure has become one of the problems that technical personnel in this field need to solve urgently. Summary of the invention

[0011] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a vertical bonding structure, a stacked chip packaging structure and a method for solving the problems of wire deviation, low transmission efficiency and high preparation cost of the vertical bonding structure in the prior art.

[0012] To achieve the above-mentioned object and other related objects, the present invention provides a vertical wiring method, which at least includes:

[0013] A welding wire and a welding head splitter are provided, wherein the welding head splitter fixes the position of the welding wire and forms a welding ball at the end of the welding wire;

[0014] Bonding the bonding wire to a set bonding pad via the bonding ball;

[0015] The welding head cutter is moved vertically upward along the welding line to a set position;

[0016] The welding wire is disconnected at a set cutting point below the welding head wrecking knife while maintaining the cross-sectional shape of the welding wire to form a vertical wire bonding structure at the set welding pad, and the remaining welding wire is removed by the welding head wrecking knife.

[0017] Preferably, the material of the bonding wire includes gold, copper, aluminum, silver or palladium.

[0018] Preferably, the welding head wrecking knife is made of ceramic.

[0019] Preferably, the method for forming a solder ball further comprises: arranging an electronic flame extinguishing rod at the end of the solder wire, and melting the end of the solder wire by electric sparks to form a solder ball.

[0020] Preferably, the method of disconnecting the welding wire further comprises: using a laser to act on a set cutting point of the welding wire to increase the particle activity of the welding wire material at the cutting point, and the welding head splitter clamps the welding wire and pulls it upward to disconnect the welding wire at the cutting point.

[0021] Preferably, the method for breaking the welding wire further comprises: using electric sparks to increase the particle activity of the welding wire material at the cutting point, and the welding head splitter clamps the welding wire and pulls it upward to break the welding wire at the cutting point.

[0022] More preferably, an electronic flame extinguishing rod is arranged around the cut-off point to avoid electric spark sputtering.

[0023] Preferably, the method for disconnecting the welding wire further comprises: using a blade to cut the welding wire in two horizontally opposite directions at the same time, so as to disconnect the welding wire at the cutting point.

[0024] To achieve the above-mentioned object and other related objects, the present invention further provides a stacked chip packaging method, which at least comprises:

[0025] providing a carrier;

[0026] forming a rewiring layer on the upper surface of the carrier;

[0027] The vertical bonding method is used to form a vertical bonding structure on the upper surface of the rewiring layer; a first chip is bonded on the upper surface of the rewiring layer, the first chip is electrically connected to the rewiring layer; the upper surface of the first chip is lower than the upper surface of the vertical bonding structure;

[0028] forming an insulating layer on the upper surface of the rewiring layer, wherein the insulating layer covers the rewiring layer, the first chip and the vertical bonding structure, and the upper surface of the insulating layer is not higher than the upper surface of the vertical bonding structure;

[0029] removing the carrier;

[0030] forming a solder bump on the lower surface of the rewiring layer, wherein the solder bump is electrically connected to the rewiring layer;

[0031] A second chip is bonded to the upper surface of the insulating layer, and the second chip is electrically connected to the vertical bonding structure.

[0032] Preferably, the insulating layer is formed on the upper surface of the rewiring layer by a compression molding process, a transfer molding process, a liquid sealing molding process, a vacuum lamination process or a spin coating process.

[0033] To achieve the above-mentioned and other related purposes, the present invention further provides a vertical bonding structure, which at least includes:

[0034] A solder ball and a solder wire, wherein the solder wire is bonded to a set solder pad through the solder ball;

[0035] Wherein, the welding wire is vertically arranged on the welding pad, and the cross section of the welding wire remains consistent.

[0036] Preferably, the material of the bonding wire and the bonding ball includes gold, copper, aluminum, silver or palladium.

[0037] Preferably, the cross-section of the welding wire comprises a circle.

[0038] Preferably, the diameter of the welding wire is set to 15-100 microns.

[0039] Preferably, the height of the solder ball is 50-100 microns.

[0040] Preferably, the length of the welding wire is 100-1500 microns.

[0041] To achieve the above-mentioned object and other related objects, the present invention further provides a packaging structure of stacked chips, wherein the packaging structure of stacked chips at least comprises:

[0042] A rewiring layer, a first chip, the vertical bonding structure, an insulating layer, solder bumps and a second chip;

[0043] The first chip and the vertical bonding structure are bonded to the rewiring layer, the insulating layer covers the rewiring layer, the first chip and the vertical bonding structure, and the upper surface of the insulating layer is flush with the upper surface of the vertical bonding structure, and the second chip is bonded to the vertical bonding structure to achieve electrical connection between the second chip and the vertically corresponding pads in the rewiring layer.

[0044] Preferably, the insulating layer comprises a polyimide layer, a silicone layer, an epoxy resin layer, a curable polymer-based material layer or a curable resin-based material layer.

[0045] As described above, the vertical bonding structure, stacked chip packaging structure and method of the present invention have the following beneficial effects:

[0046] The vertical bonding structure, stacked chip packaging structure and method of the present invention directly cut the bonding wires in the air without moving the bonding wires and without changing the cross-section of the bonding wires. It has the advantages of easy control of the bonding wire length, high signal transmission efficiency, no deviation of the bonding wire position, simple operation and low cost, thereby greatly improving the quality of the stacked packaged chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 The diagram shows the principle of bonding solder balls in the prior art.

[0048] Figure 2 It is a schematic diagram showing the principle of thinning welding wire in the prior art.

[0049] Figure 3 The figure shows a schematic diagram of the principle of disconnecting welding wires in the prior art.

[0050] Figure 4 It is a schematic diagram showing the flow of the vertical bonding method of the present invention.

[0051] Figures 5 to 10 It is a schematic diagram showing the principle of the vertical wiring method of the present invention.

[0052] Fig.11 It is a schematic diagram showing the flow of the stacked chip packaging method of the present invention.

[0053] Figure 12 to Figure 16 It is a schematic diagram showing the principle of the stacked chip packaging method of the present invention.

[0054] Component number description

[0055] 1 Set the pad

[0056] 11 First pad

[0057] 12 Second pad

[0058] 2 Vertical bonding structure

[0059] 21. Welding wire

[0060] 22 Solder balls

[0061] 3 Welding head splitter

[0062] 4 Electronic flame extinguisher

[0063] 501 Carrier

[0064] 502 peeling layer

[0065] 51 Rewiring Layer

[0066] 511 Dielectric layer

[0067] 512 Metal Wire Layer

[0068] 52 First Chip

[0069] 53 Solder micro bumps

[0070] 54 Insulation layer

[0071] 55 Solder Bumps

[0072] 551 Metal Column

[0073] 552 First solder ball

[0074] 56 Second chip

[0075] 57 Second solder ball

[0076] Steps S11 to S14

[0077] Steps S21 to S27 DETAILED DESCRIPTION

[0078] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0079] See also Figures 4 to 16 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0080] Embodiment 1

[0081] like Figure 4 As shown, this embodiment provides a vertical wiring method, and the vertical wiring method includes:

[0082] Step S11 : providing a bonding wire 21 and a bonding head blade 3 , wherein the bonding head blade 3 fixes the position of the bonding wire 21 and forms a solder ball 22 at the end of the bonding wire 21 .

[0083] Specifically, Figure 5 As shown, the material of the welding wire 21 includes but is not limited to gold, copper, aluminum, silver and palladium. Any conductive material is applicable to the present invention. In this embodiment, the material of the welding wire 21 is preferably gold. The welding head splitter 3 is an insulating material. In this embodiment, the welding head splitter 3 is made of ceramic. The welding head splitter 3 includes two symmetrical clamping parts, which can fix and move the position of the welding wire 21 by clamping in two directions.

[0084] Specifically, Figure 6 As shown, an electronic flame extinguisher 4 is arranged at the end of the welding wire 21 , and the end of the welding wire 21 is melted by electric sparks to form a welding ball 22 , and the welding ball 22 is located below the welding head splitter 3 .

[0085] Step S12 : bonding the bonding wire 21 to the set bonding pad 1 through the solder ball 22 .

[0086] Specifically, Figure 7As shown, the surface of the setting pad 1 is cleaned, and the solder ball 22 is bonded to the surface of the setting pad 1 by van der Waals force, molecular force or atomic force.

[0087] Step S13: vertically move the welding head blade 3 upward along the welding line 21 to a set position.

[0088] Specifically, Figure 8 As shown, the welding head blade 3 moves vertically upward with the center of the welding ball 22 as a reference point, and the welding wire 21 remains vertical without deformation.

[0089] Step S14: Fig. 9 As shown, the welding wire 21 is disconnected at a set cutting point below the welding head wrench 3 while maintaining the cross-sectional shape of the welding wire 21, as shown in FIG. Fig.10 As shown, a vertical bonding structure 2 is formed on the set bonding pad 1 , and the remaining bonding wires 22 are removed by the bonding head cutter 3 .

[0090] Specifically, as an embodiment of the present invention, a laser is used to act on the set cutting point of the welding wire 21 to increase the particle activity of the welding wire material at the cutting point, and the welding head splitter 3 clamps the welding wire 21 and pulls it upward to break the welding wire 21 at the cutting point.

[0091] Specifically, as another embodiment of the present invention, an electronic flame extinguisher is arranged around the cutting point, and electric sparks are used to increase the particle activity of the welding wire material at the cutting point, and the welding head splitter 3 clamps the welding wire 21 and pulls it upward to break the welding wire 21 at the cutting point. The electronic flame extinguisher is used to avoid electric spark sputtering.

[0092] Specifically, as another embodiment of the present invention, a blade is used to cut the welding wire 21 in two horizontally opposite directions at the same time, so as to disconnect the welding wire 21 at the cutting point. Cutting can be achieved by using two independent blades or by using scissors. Any method that can achieve simultaneous cutting in two opposite directions is applicable to the present application and is not limited to this embodiment.

[0093] like Fig.10 As shown, this embodiment also provides a vertical wiring structure 2, including:

[0094] The solder ball 22 and the bonding wire 21 , wherein the bonding wire 21 is bonded to the set bonding pad 1 through the solder ball 22 .

[0095] Specifically, the materials of the bonding wire 21 and the bonding ball 22 include gold, copper, aluminum, silver or palladium, which are not described in detail herein.

[0096] Specifically, the height of the solder ball 22 is set to be 50-100 microns.

[0097] like Fig.10 As shown, the welding wire 21 is vertically arranged on the setting welding pad 1, and the cross section of the welding wire 21 remains consistent.

[0098] Specifically, in this embodiment, the cross section of the welding wire 21 includes a circle, and the diameter of the welding wire 21 is set to 15 to 100 microns. The diameters of the welding wires 21 used by different materials and different processes are different and can be set as needed, which will not be described in detail here. The length of the welding wire 21 is 100 to 1500 microns and can be set as needed.

[0099] After the wire bonding of the present invention is completed, the welding head splitter does not move the wire in the left and right directions, and the wire will not be deformed in the vertical direction. At the same time, the wire and the center of the solder ball will not be offset, which is convenient for subsequent interconnection positioning. The present invention increases the particle activity of the wire material or cuts in two relative directions at the same time to avoid cross-sectional deformation of the wire cutting point, thereby greatly improving the transmission efficiency and making it easy to control the length of the wire.

[0100] Embodiment 2

[0101] like Figures 4 to 16 As shown, this embodiment provides a stacked chip packaging method, such as Fig.11 As shown, in this embodiment, the stacked chip packaging method is a fan-out stacked packaging method, comprising:

[0102] Step S21: Fig.12 As shown, a carrier 501 is provided.

[0103] Specifically, the material of the carrier 501 includes, but is not limited to, one or a composite material of two or more of silicon, glass, silicon oxide, ceramic, polymer, and metal, and its shape can be round, square, or any other desired shape; this embodiment uses the carrier 501 to prevent the chip from cracking, warping, breaking, and other problems during the subsequent preparation process. The step of forming a peeling layer 502 on the carrier 501 is also included.

[0104] Step S22: Fig.12 As shown, a rewiring layer 51 is formed on the upper surface of the carrier 50 .

[0105] Specifically, a dielectric layer 511 is formed on the upper surface of the stripping layer 502, and a groove is formed in the dielectric layer 511 by photolithography and etching processes, and the groove is defined in the shape of the metal wire layer 512; the metal wire layer 512 is formed in the groove. The material of the metal wire layer 512 can be, but not limited to, one material or a combination of two or more materials selected from copper, aluminum, nickel, gold, silver, and titanium, and can be formed by processes such as PVD, CVD, sputtering, electroplating, or chemical plating. The material of the dielectric layer 511 can be a low-k dielectric material; more specifically, the dielectric layer 511 can be one material selected from epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass, and fluorine-containing glass, and can be formed by processes such as spin coating, CVD, and plasma-enhanced CVD.

[0106] Step S23: Fig.12 As shown, a vertical wiring structure 2 is formed on the upper surface of the rewiring layer 51 .

[0107] Specifically, the vertical bonding structure 2 is formed by the vertical bonding method described in the first embodiment, which will not be described in detail here.

[0108] Step S24 : bonding a first chip 52 on the upper surface of the rewiring layer 51 , wherein the first chip 52 is electrically connected to the rewiring layer 51 , and the upper surface of the first chip 52 is lower than the upper surface of the vertical bonding structure 2 .

[0109] Specifically, the first chip 52 is bonded to the upper surface of the rewiring layer 51 via solder micro-bumps 53; the material of the solder micro-bumps 53 may be at least one of copper, nickel, tin and silver.

[0110] It should be noted that the order of step S23 and step S24 can be interchanged and is not limited to this embodiment.

[0111] Step S25: Fig.13 As shown, an insulating layer 54 is formed on the upper surface of the rewiring layer 51 , and the insulating layer 54 covers the rewiring layer 51 and the first chip 52 . The upper surface of the insulating layer 54 is not higher than the upper surface of the vertical bonding structure 2 .

[0112] Specifically, the insulating layer 54 is formed on the upper surface of the rewiring layer 51 by a compression molding process, a transfer molding process, a liquid sealing molding process, a molded bottom filling process, a capillary bottom filling process, a vacuum lamination process or a spin coating process. In this embodiment, the insulating layer 54 is formed on the upper surface of the rewiring layer 51 by a molded bottom filling process. The insulating material can be smoothly and quickly filled in the gap between the vertical wiring structure 2 and the first chip 52, effectively avoiding interface stratification. The molded bottom filling is not restricted like the capillary bottom filling process in the prior art, which greatly reduces the process difficulty and can be used for smaller connection gaps, and is more suitable for stacked structures. The material of the insulating layer 54 includes but is not limited to a polyimide layer, a silicone layer, an epoxy resin layer, a curable polymer-based material layer or a curable resin-based material layer. In this embodiment, the height of the insulating layer 54 is higher than the height of the vertical bonding structure 2. A portion of the insulating layer 54 and a portion of the vertical bonding structure 2 are removed by a chemical mechanical polishing process so that the upper surface of the insulating layer 54 is flush with the upper surface of the vertical bonding structure 2.

[0113] Step S26: removing the carrier 501.

[0114] Specifically, Fig.14 As shown, a grinding process or a thinning process is used to remove the carrier 501 and the peeling layer 502. In this embodiment, the peeling layer 502 is torn off to remove the carrier 501.

[0115] Step S27 : forming a solder bump 55 on the lower surface of the re-distribution layer 51 , wherein the solder bump 55 is electrically connected to the re-distribution layer 51 .

[0116] Specifically, Fig.15 As shown, a metal column 551 is formed on the lower surface of the rewiring layer 51, and a first solder ball 552 is formed on the lower surface of the metal column 551. The material of the metal column 551 can be one material or a combination of two or more materials selected from copper, aluminum, nickel, gold, silver, and titanium, and can be formed by any process selected from physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, electroplating, or chemical plating. The material of the first solder ball 552 can be one material or a combination of two or more materials selected from copper, aluminum, nickel, gold, silver, and titanium, and can be formed by a ball implantation reflow process.

[0117] Step S28: Fig.16 As shown, a second chip 56 is bonded to the upper surface of the insulating layer 54 , and the second chip 56 is electrically connected to the vertical bonding structure 2 through a second solder ball 57 .

[0118] Specifically, the second chip 56 can be bonded to the vertical bonding structure 2 via the second solder balls 57 by using a flip-chip bonding process, and the second chip 56 is electrically connected to the rewiring layer 51 via the vertical bonding structure 2 .

[0119] The stacked chip packaging method in this embodiment is a fan-out stacked packaging. In actual use, the vertical bonding structure of the present invention can be applied to various packaging methods requiring vertical bonding, and is not limited to this embodiment.

[0120] like Fig.16 As shown, this embodiment further provides a stacked chip packaging structure, and the stacked chip packaging structure includes:

[0121] The rewiring layer 51 , the first chip 52 , the vertical bonding structure 2 , the insulating layer 54 , the solder bumps 55 and the second chip 56 .

[0122] Specifically, the first chip 52 and the vertical bonding structure 2 are bonded to the rewiring layer 51, the insulating layer 54 covers the rewiring layer 51, the first chip 52 and the vertical bonding structure 2, and the upper surface of the insulating layer 54 is flush with the upper surface of the vertical bonding structure 2, and the second chip 2 is bonded to the vertical bonding structure 2 through the second solder ball 57 to achieve electrical connection between the second chip 56 and the vertically corresponding solder pad in the rewiring layer 51.

[0123] In the stacked chip packaging structure of the present invention, the solder pads in the rewiring layer 51 are set to correspond vertically to the solder pads on the second chip 56. On this basis, the higher the verticality of the solder wires 21 in the vertical wiring structure 2, the higher the bonding accuracy, the more economical the second solder balls 57 directly between the second chip 56 and the vertical wiring structure 2, and the higher the transmission efficiency.

[0124] In summary, the present invention provides a vertical wire bonding structure, a stacked chip packaging structure and a method, including: providing a welding wire and a welding head splitting knife, the welding head splitting knife fixes the position of the welding wire and forms a solder ball at the end of the welding wire; bonding the welding wire to a set welding pad through the solder ball; moving the welding head splitting knife vertically upward along the welding wire to a set position; disconnecting the welding wire at a set cutting point below the welding head splitting knife while maintaining the cross-sectional shape of the welding wire, so as to form a vertical wire bonding structure at the set welding pad, and the remaining welding wires are removed by the welding head splitting knife. The vertical wire bonding structure, the stacked chip packaging structure and the method of the present invention directly cut off the welding wire in the air without moving the welding wire, and do not change the cross-section of the welding wire. It has the advantages of easy control of the welding wire length, high signal transmission efficiency, no deviation of the welding wire position, simple operation, low cost, etc., and can greatly improve the quality of the stacked packaged chip. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0125] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A vertical wiring method, It is characterized in that The vertical wiring method at least comprises: A welding wire and a welding head splitter are provided, wherein the welding head splitter clamps the welding wire and fixes the position of the welding wire to form a welding ball at the end of the welding wire; Bonding the bonding wire to a set bonding pad via the bonding ball; The welding head cutter is moved vertically upward along the welding line to a set position; The welding wire is cut off at a set cutting point below the welding head wrench while maintaining the cross-sectional shape of the welding wire to form a vertical wire bonding structure at the set welding pad, and the remaining welding wire is removed by the welding head wrench; Among them, the method for disconnecting the welding wire further includes: using laser to act on the set cutting point of the welding wire to increase the particle activity of the welding wire material at the cutting point, and the welding head splitting knife clamps the welding wire and pulls it upward to disconnect the welding wire at the cutting point; or, using electric sparks to increase the particle activity of the welding wire material at the cutting point, and the welding head splitting knife clamps the welding wire and pulls it upward to disconnect the welding wire at the cutting point.

2. The vertical wiring method according to claim 1, Features: The material of the bonding wire includes gold, copper, aluminum, silver or palladium.

3. The vertical wiring method according to claim 1, Features: The material of the welding head wrecking knife includes ceramic.

4. The vertical bonding method according to claim 1, Features: The method for forming a solder ball further comprises: arranging an electronic flame extinguishing rod at the end of the solder wire, and melting the end of the solder wire by electric sparks to form a solder ball.

5. The vertical wiring method according to claim 1, Features: An electronic flame extinguishing rod is arranged around the cut-off point to avoid electric spark sputtering.

6. A stacked chip packaging method, It is characterized in that The stacked chip packaging method at least comprises: providing a carrier; forming a rewiring layer on the upper surface of the carrier; A vertical bonding structure is formed on the upper surface of the rewiring layer by using the vertical bonding method according to any one of claims 1 to 5; a first chip is bonded on the upper surface of the rewiring layer, the first chip is electrically connected to the rewiring layer; the upper surface of the first chip is lower than the upper surface of the vertical bonding structure; forming an insulating layer on the upper surface of the rewiring layer, wherein the insulating layer covers the rewiring layer, the first chip and the vertical bonding structure, and the upper surface of the insulating layer is not higher than the upper surface of the vertical bonding structure; removing the carrier; forming a solder bump on the lower surface of the rewiring layer, wherein the solder bump is electrically connected to the rewiring layer; A second chip is bonded to the upper surface of the insulating layer, and the second chip is electrically connected to the vertical bonding structure.

7. The stacked chip packaging method according to claim 6, Features: The insulating layer is formed on the upper surface of the rewiring layer by using a compression molding process, a transfer molding process, a liquid sealing molding process, a vacuum lamination process or a spin coating process.

8. A vertical bonding structure, prepared based on the vertical bonding method according to any one of claims 1 to 5, It is characterized in that The vertical bonding structure at least comprises: A solder ball and a solder wire, wherein the solder wire is bonded to a set solder pad through the solder ball; Wherein, the welding wire is vertically arranged on the welding pad, and the cross section of the welding wire remains consistent.

9. The vertical bonding structure according to claim 8, Features: The materials of the bonding wire and the bonding ball include gold, copper, aluminum, silver or palladium.

10. The vertical bonding structure according to claim 8, Features: The cross-section of the welding wire includes a circle.

11. The vertical bonding structure according to claim 10, Features: The diameter of the welding wire is set to be 15 to 100 microns.

12. The vertical bonding structure according to claim 8, Features: The height of the solder ball is 50 to 100 microns.

13. The vertical bonding structure according to claim 8, Features: The length of the welding wire is 100 to 1500 microns.

14. A packaging structure of stacked chips, It is characterized in that The packaging structure of the stacked chips at least includes: A rewiring layer, a first chip, a vertical wiring structure according to any one of claims 8 to 13, an insulating layer, a solder bump and a second chip; The first chip and the vertical bonding structure are bonded to the rewiring layer, the insulating layer covers the rewiring layer, the first chip and the vertical bonding structure, and the upper surface of the insulating layer is flush with the upper surface of the vertical bonding structure, and the second chip is bonded to the vertical bonding structure to achieve electrical connection between the second chip and the vertically corresponding pads in the rewiring layer.

15. The stacked chip packaging structure according to claim 14, Features: The insulating layer includes a polyimide layer, a silicone layer, an epoxy resin layer, a curable polymer-based material layer or a curable resin-based material layer.

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