A MEMS chip with TSV structure and wafer-level airtight packaging method thereof

Abstract

The present invention discloses a MEMS chip with a TSV structure and a wafer-level airtight packaging method thereof. The MEMS chip of the present invention covers an insulating oxide layer on the inner wall of the deep groove of the cover plate to form an oxidized deep groove, and the oxidized deep groove is filled with deep groove polysilicon to form a TSV structure. The electrical signal of the MEMS structure can be connected to the top metal pattern through the first bonding metal block and the TSV conductive column, and can also be connected to the top metal pattern through the second bonding metal block, the metal wire and the deep groove polysilicon, so as to achieve the purpose of conducting two electrical signals with one TSV structure. The method of the present invention only adds a processing step of etching a concave cavity under the cover plate to the cover plate wafer manufacturing step, and then covers the inner wall of the deep groove with an insulating oxide layer to form an oxidized deep groove, and fills the oxidized deep groove with deep groove polysilicon to form a TSV structure, so as to achieve the purpose of conducting two electrical signals with one TSV structure. The manufacturing process is simple, and the obtained MEMS chip is small in size and low in cost.

Description

Technical Field

[0001] The invention relates to a process method for MEMS wafer-level airtight packaging, in particular to a MEMS chip with a TSV structure and a wafer-level airtight packaging method thereof, belonging to the technical field of chip packaging. Background Art

[0002] MEMS (Micro-Electro-Mechanical System) chips usually have movable structures, which are very fragile and need to be protected by sealed cavity packaging. The traditional packaging method is to use ceramic tube shells, metal tube shells, preformed plastic tube shells, etc. for cavity packaging, but the MEMS movable structure (MEMS structure for short) is easily contaminated or damaged during the packaging process. Therefore, in most MEMS chip manufacturing processes, a wafer-level airtight packaging method is used to add a cover plate to the MEMS structure to protect the movable part (ie, MEMS structure), and then perform packaging similar to ordinary electronic components. Wafer-level packaging technology is a processing technology that encapsulates the wafer with electronic chips as a whole, and then cuts it into individual electronic chips after testing. The subsequent processing of the chip after wafer-level packaging is convenient, and does not require an ultra-clean environment above Class 1000. No special protection is required when cutting the wafer, which saves processing costs.

[0003] TSV (Through-Silicon-Via) wafer-level packaging technology is the one with the smallest chip area in wafer-level airtight packaging. It is a method of directly making deep holes or deep grooves on the cover wafer of the electronic chip to lead the electrical signal out of the electronic chip. The TSV structure is a component of the sealed cavity. For MEMS accelerometers, gyroscopes, clocks and other chips, their structural materials are usually Si, and the cover is generally made of the same Si material as the MEMS structure, with an upper concave cavity made on it. The main function of the cover is to form a sealed cavity together with the base plate (the base plate is generally made with a lower concave cavity), providing a space for free movement for the MEMS structure sealed in the cavity, and at the same time, it can ensure that the MEMS structure is not disturbed by the external environment. The base plate can be an integrated circuit chip or a Si material without circuits.

[0004] Taking into account the stress and process compatibility issues of subsequent processing, MEMS chip TSV wafer-level airtight packaging usually makes an annular deep groove on the cover wafer, forms an insulating deep groove wall through an oxidation process, and then fills the deep groove with doped polycrystalline Si to form TSV. The cover Si part surrounded by the annular deep groove actually plays the role of a lead. In this method, due to the aspect ratio of the deep groove etching reaching (20-30):1 and the requirements of subsequent processing, the area of ​​TSV cannot be too small. Depending on the product, TSV can occupy up to 40% of the area of ​​the entire MEMS chip, which reduces the superiority of TSV and brings many changes to the design of the MEMS movable structure.

[0005] In TSV wafer-level packaging technology used in integrated circuits and other electronic devices, the deep grooves are generally filled with metal, with no cavities and no movable structures. Patents CN201811494478, CN109461749A, CN109273403A, CN10868194U and other patents are all about integrated circuit wafer-level packaging technology.

[0006] Patents CN109686722A and CN109599378A describe integrated circuit packaging transfer substrate technology with TSV, CN109671692A describes TSV exposure manufacturing technology, CN109560039A describes a method for reducing TSV thermal stress, and CN201821708520.8 describes a TSV chip packaging method for a MEMS infrared detector that forms a getter and anti-reflection layer inside the cover.

[0007] Patent US9362139B2 describes sealing the MEMS structure in a sealed cavity surrounded by a TSV cover and an integrated circuit base. The electrical signal of the MEMS structure is not directly led out through the TSV, but is transmitted to the conductive column through a horizontal metal wire, and the conductive column is then transmitted to the TSV through a horizontal metal wire. This method has a large area, and one TSV can only transmit one electrical signal.

[0008] Patent US9611137B2 describes the manufacture of TSV on the back of a CMOS-MEMS chip and flipping an integrated circuit chip on it. Patents US9422153B2, US9351081B2, and US9196752B2 describe the formation of TSV on the back cover of a MEMS chip-level package to lead out electrical signals. TSV itself is not a component of the MEMS airtight package.

[0009] US9318376B1 describes a method of depositing heavily doped polycrystalline Si in a trench and thermally diffusing doped surrounding substrate Si materials to form a low resistivity TSV conductive column.

[0010] Patents US9355895B2 and US7915080B2 describe a rewiring method for electroplating filled TSVs, which is used for wafer-level packaging of common integrated circuits.

[0011] Figure 1 The present invention shows an existing wafer-level airtight packaged MEMS chip. The sealed cavity formed by the upper concave cavity 120 on the upper surface of the base plate 125 and the lower concave cavity 112 on the lower surface of the cover plate 108 provides a freely movable sealed space for the MEMS structure 140. There is a bonding material layer 118 between the MEMS structure layer 115 and the base plate layer 125 to provide an airtight mechanical connection. The bonding material layer 118 can be a conductive material, such as aluminum, gold, copper, gold-tin alloy and other metals, or an insulating material, such as silicon dioxide. The isolation groove 110 on the cover plate 108 separates the cover plate 108 into a cover plate area 132 and a conductive column 138. The isolation groove 110 is filled with an insulating material, such as silicon dioxide, or a composite layer of silicon dioxide and polysilicon. In fact, the conductive pillar 138, the isolation groove 110 and the cover area 132 together constitute the upper cover. The conductive pillar 138 and the isolation groove 110 constitute a through silicon via (TSV) unit. The electrical signal of the MEMS structure 140 is transmitted to the top metal 130 through the conductive area 145 of the bonding metal 102, the conductive pillar 138 and the contact hole 148. Each TSV unit can only conduct one electrical signal. There must be as many TSV units as there are signals in each MEMS structure. Summary of the invention

[0012] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a MEMS chip with a TSV structure and a wafer-level airtight packaging method thereof. Each TSV structure of the chip with a TSV structure of the present invention can lead out two electrical signals; compared with the traditional wafer-level packaging method, only the processing step of the cover wafer is added, so that each TSV structure can conduct two electrical signals, and the MEMS chip area can be made smaller, which not only reduces the cost but also facilitates the design of the MEMS structure.

[0013] In order to solve the above technical problems, the present invention provides a MEMS chip with a TSV structure, which is composed of a cover plate, a MEMS structure layer and a bottom plate. The materials of the cover plate, the MEMS structure layer and the bottom plate are all single crystal silicon. There is at least one upper concave cavity on the bottom plate, and at least one lower concave cavity on the cover plate. The upper concave cavity and the lower concave cavity together form a sealed cavity. The MEMS structure of the MEMS structure layer is located in the sealed cavity and can move freely in the sealed cavity. The bottom plate is mechanically connected to the MEMS structure layer through a bottom plate insulating layer. The material of the bottom plate insulating layer is SiO2. The cover plate is bonded to the MEMS structure layer through a bonding metal layer.

[0014] The cover plate is composed of a cover plate sealing area, a TSV isolation groove, a TSV conductive column and a lower concave cavity area. The TSV isolation groove is located between the cover plate sealing area and the TSV conductive column and between the TSV conductive column and the lower concave cavity area. The TSV isolation groove is composed of an oxidized deep groove and a deep groove polysilicon filled in the oxidized deep groove. The oxidized deep groove is composed of a deep groove etched on the cover plate and an insulating oxide layer covering the inner wall of the deep groove.

[0015] The MEMS structure layer includes a MEMS sealing area, a first MEMS bonding column, a second MEMS bonding column and a MEMS structure;

[0016] The bonding metal layer includes a metal sealing ring, a first bonding metal block, a second bonding metal block and a metal wire, wherein the sealing metal ring is eutectic bonded to the MEMS sealing area, the first bonding metal block is eutectic bonded to the first MEMS bonding column, the second bonding metal block is eutectic bonded to the second MEMS bonding column, and the metal wire simultaneously connects the second bonding metal block and the deep trench polysilicon;

[0017] There is an insulating layer on the cover plate, and contact holes are etched on the insulating layer, in which TSV conductive columns and deep groove polysilicon are exposed; a top metal pattern is deposited in the insulating layer and the contact hole, and the electrical signal of the MEMS structure is led out through the first bonding metal block, the TSV conductive column and the top metal pattern in the contact hole, and the other way is led out through the second bonding metal block, the metal wire, the deep groove polysilicon and the top metal pattern in the contact hole.

[0018] In the MEMS chip with TSV structure of the present invention, the electrical signal of the MEMS structure connected to the first MEMS bonding column is connected to the top metal pattern through the first metal bonding block, TSV conductive column and contact hole; the electrical signal of the MEMS structure connected to the second MEMS bonding column is connected to the top metal pattern through the second metal bonding block, metal wire, deep groove polysilicon and contact hole; in this way, the purpose of conducting two electrical signals by one TSV structure is achieved.

[0019] The metal sealing ring, the first bonding metal block and the second bonding metal block are located on the same plane.

[0020] The material of the bonding metal layer is a metal that can eutectically bond with Si at a temperature below 500°C.

[0021] In order to solve the above technical problems, the present invention also provides a wafer-level airtight packaging method for a MEMS chip with a TSV structure, comprising the following steps:

[0022] (1) Making the bottom plate disc:

[0023] A heavily doped single crystal silicon wafer is selected as a bottom plate wafer substrate, the bottom plate wafer substrate is thermally oxidized, a bottom plate insulating layer is grown on the surface of the bottom plate wafer substrate, and the bottom plate wafer substrate with the bottom plate insulating layer grown thereon is etched to form an upper concave cavity, thereby completing the manufacture of the bottom plate wafer;

[0024] (2) Making MEMS structure wafers:

[0025] Bonding a double-sided polished single-crystal silicon wafer to the bottom plate wafer produced in step (1), and grinding it to 10-100 μm to form a MEMS structure layer; etching the MEMS structure layer to form a MEMS sealing area and a MEMS bonding column, and then deep silicon etching to form a MEMS structure, thereby completing the production of the MEMS structure wafer;

[0026] (3) Fabrication of a cover wafer with a TSV structure:

[0027] Another double-sided polished single-crystal silicon wafer is used as the cover wafer substrate, and a concave cavity is etched on the inner surface of the cover wafer substrate, and then a deep groove is etched; after thermal oxidation etching, an insulating oxide layer is generated on the surface of the cover wafer substrate and the inner wall of the deep groove, and the insulating oxide layer of the deep groove and its inner wall together form an oxidized deep groove, and then polysilicon is deposited on the insulating oxide layer, and the polysilicon filled in the oxidized deep groove becomes deep groove polysilicon; the polysilicon is etched back to remove all the polysilicon on the surface of the insulating oxide layer, and only the deep groove polysilicon in the oxidized deep groove is retained to form a TSV isolation groove; and then the insulating oxide layer is etched to expose part of the cover wafer substrate , forming a cover plate sealing area, a TSV conductive column and a lower concave cavity area, the TSV conductive column and other parts of the cover plate wafer are electrically insulated by the TSV isolation groove to form a complete TSV structure; then a bonding metal layer is deposited on the cover plate wafer substrate, and etched to form a metal sealing ring, a first bonding metal block, a second bonding metal block and a metal wire, wherein the metal sealing ring is located above the cover plate sealing area, the first bonding metal block is located above the TSV conductive column, the second bonding metal block is located above the insulating oxide layer in the lower concave cavity, and the metal wire connects the second bonding metal block and the deep trench polysilicon, thus completing the manufacture of a cover plate wafer with a TSV structure;

[0028] (4) Fabrication of a bonding wafer with a TSV structure:

[0029] Align and bond the cover wafer with TSV structure made in step (3) and the MEMS structure wafer made in step (2) to form a bonded wafer with TSV structure; wherein the first bonding metal block is eutectic bonded to the first MEMS bonding column, and the electrical signal of the part connected to the first MEMS bonding column in the MEMS structure is connected to the TSV conductive column; the second bonding metal block is eutectic bonded to the second MEMS bonding column, and the electrical signal of the part connected to the second MEMS bonding column in the MEMS structure is connected to the deep groove polysilicon through a metal wire; the sealing metal ring 46 is eutectic bonded to the MEMS sealing area to form a sealing bonding surface, and the cover wafer, the sealing metal ring, the sealing bonding surface, the MEMS sealing area, the bottom plate insulating layer and the bottom plate wafer together form a sealing cavity to provide a free-moving sealing space for the MEMS structure;

[0030] (5) Making thinned wafers:

[0031] Grinding and polishing the cover wafer of the bonded wafer with TSV structure manufactured in step (4) to expose the deep groove polysilicon and form a thinned wafer;

[0032] (6) Making finished wafers:

[0033] An insulating layer is formed on the thinned wafer in step (5), and the insulating layer is etched to form contact holes, in which the TSV conductive pillars and deep groove polysilicon are respectively exposed; a top layer of metal is then deposited on the insulating layer, and the contact holes are also filled with the top layer of metal, and the deep groove polysilicon and the TSV conductive pillars are connected to the top layer of metal through the contact holes; the top layer of metal is etched to form a top layer of metal pattern, and the top layer of metal pattern is respectively connected to the TSV conductive pillars and the deep groove polysilicon, thereby completing the production of a finished wafer;

[0034] (7) Cutting to form a MEMS chip with TSV structure:

[0035] Cutting the finished wafers by a common wafer cutting method to form a MEMS chip with a TSV structure, wherein the bottom plate wafer is cut to become a bottom plate of the MEMS chip with a TSV structure, and the cover plate wafer is cut to become a cover plate of the MEMS chip with a TSV structure;

[0036] The etching mentioned above refers to mask etching.

[0037] The metal sealing ring, the first bonding metal block and the second bonding metal block in step (3) are on the same plane.

[0038] The material of the bonding metal layer in step (3) is a metal that can eutectic bond with Si at a temperature below 500° C., such as Au, Al or Au—Sn.

[0039] Compared with the prior art, the method of the present invention only adds one processing step of etching the concave cavity under the cover plate in step (3), and then covers the inner wall of the deep groove with an insulating oxide layer to form an oxidized deep groove, and fills the oxidized deep groove with deep groove polysilicon to form a TSV structure, so that the electrical signal of the MEMS structure can not only be connected to the top metal pattern through the first metal bonding block and the TSV conductive column, but also can be connected to the top metal pattern through the second metal bonding block, the metal wire and the deep groove polysilicon, thus achieving the purpose of conducting two electrical signals with a TSV structure, the manufacturing process is simple, and the obtained MEMS chip is small in size and low in cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a cross-sectional view of a conventional wafer-level packaged MEMS chip.

[0041] Figure 2 — Figure 3 It is the process of making the base plate wafer.

[0042] Figure 4 — Figure 6 It is the process of manufacturing MEMS structure wafers.

[0043] Figure 7 — Fig.14 It is a process for manufacturing a cover wafer with a TSV structure.

[0044] Fig.15 It is the process of making bonding wafers.

[0045] Fig.16 It is the process of making thinned wafers.

[0046] Fig.17 — Fig. 20 It is the process of making finished wafers.

[0047] Fig.21 4 is a cross-sectional view of a MEMS chip having a TSV structure according to the present invention.

[0048] Fig. 22 yes Fig.21 Top view of the middle M part. DETAILED DESCRIPTION

[0049] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0050] A wafer-level hermetic packaging method for a MEMS chip having a TSV structure comprises the following steps:

[0051] (1) Making the bottom plate disc 1:

[0052] A heavily doped single crystal silicon wafer is used as the bottom plate wafer substrate 10, the resistivity of the bottom plate wafer substrate 10 is 0.001-0.1Ω*CM, the thickness is 300-500μm, and 1-2μm SiO2 is grown on the surface of the bottom plate wafer substrate 10 through a thermal oxidation process as a bottom plate insulating layer 12, such as Figure 2 As shown, the bottom plate insulating layer 12 plays an insulating role in subsequent processes;

[0053] The surface of the bottom plate wafer substrate 10 having the bottom plate insulating layer 12 is subjected to the processes of coating, exposure, development, etching SiO2 and Si, degumming, cleaning, etc., to etch out an upper cavity 15, the depth of which is 10 to 100 μm; Figure 3 As shown, at the same time, the area protected by the photoresist during etching forms a bottom plate sealing area 16 and a support column 17, and the bottom plate insulating layer 12 on their surface forms an insulating bonding surface 12a. At this point, the production of the bottom plate wafer 1 is completed.

[0054] (2) Fabrication of MEMS structure wafer 2:

[0055] exist Figure 3 A double-sided polished single-crystal silicon wafer is bonded to the bottom plate wafer 1 shown in the figure. The resistivity of the double-sided polished single-crystal silicon wafer is 0.001-0.1Ω*CM, and the conductive property is good. The thickness is 300-500μm. After grinding and polishing, it is thinned to 10-100μm to form a MEMS structure layer 18. Figure 4 As shown, the MEMS structure layer 18 is mechanically connected to the bottom plate sealing area 16 and the support column 17 through the insulating bonding surface 12a, but there is no electrical connection;

[0056] The MEMS structure layer 18 is subjected to the processes of coating, exposure, development, etching Si, debonding, cleaning, etc. to form the MEMS bonding column 24 and the MEMS sealing area 22. Figure 5 As shown, the height of the MEMS bonding pillar 24 is 0.5 to 5 μm;

[0057] Continue to perform processing steps such as coating, exposure, development, etching Si, degumming, and cleaning on the MEMS structure layer 18 to form a MEMS structure 25. Figure 6 As shown, the MEMS bonding column 24 and the MEMS sealing area 22 are protected by the photoresist and are not etched. The area corresponding to the MEMS bonding column 24 becomes the anchor point 27 of the MEMS structure. In this way, the MEMS structure wafer 2 is manufactured.

[0058] (3) Manufacturing a cover wafer 3 having a TSV structure:

[0059] Another double-sided polished single crystal silicon wafer is used as the cover wafer substrate 30, whose resistivity is 0.001-0.1Ω*CM, good conductivity, and the wafer thickness is 300-800μm. Figure 7 As shown, the inner surface 30a is subjected to the processes of coating, exposure, development, etching Si, debonding, cleaning, etc. to form a lower concave cavity 32 with a depth of 1 to 2 μm;

[0060] The inner surface 30a of the cover wafer substrate 30 with the lower concave cavity 32 is subjected to the processes of coating, exposure, development, etching Si, debonding, cleaning, etc. to form a deep groove 34. Figure 8 As shown, its width is 3 to 15 μm and its depth is 50 to 300 μm, and it serves as an electrical signal isolation trench of a through silicon via (TSV). The lower concave cavity 32 is protected by the photoresist during etching and is not etched;

[0061] The cover wafer substrate 30 is thermally oxidized to form an insulating oxide layer 36 on the surface of the entire cover wafer substrate 30. The thickness of the insulating oxide layer 36 is equal to the depth of the lower cavity 32. The surface of the deep groove 34 is also covered by the insulating oxide layer 36 to form an oxidized deep groove 37. Fig. 9 As shown; during thermal oxidation, about 0.45 μm Si is consumed for each 1 μm SiO2 layer generated. Assuming that the depth of the lower cavity 32 is h and the thickness of the insulating oxide layer 36 is also h, the surface 36a of the insulating oxide layer in the lower cavity 32 is 0.55h higher than the surface 32a of the lower cavity 32 before thermal oxidation, that is, 0.45h lower than the inner surface 30a of the cover wafer substrate 30 before thermal oxidation, as shown in FIG. Fig.10 As shown, at the same time, the oxidation interface 35 below the insulating oxide layer 36 on the other parts except the lower concave cavity 32 is 0.45h lower than the inner surface 30a of the thermally oxidized front cover wafer substrate 30, so the insulating oxide layer surface 36a in the lower concave cavity 32 and the oxidation interface 35 of other parts are on the same horizontal line;

[0062] In-situ doped polysilicon 38 is deposited on the insulating oxide layer 36 of the cover wafer substrate 30 after thermal oxidation, and at the same time, the deep oxidation trench 37 is also filled with deep trench polysilicon 38a. Fig.11 As shown; heavily doped polysilicon is a good conductive material. In the prior art, the thermal fluidity of heavily doped polysilicon is often used to fill the gaps in the TSV. In the present invention, in addition to filling the TSV gaps, it is also used as a conductor to lead the MEMS signal out of the sealed cavity;

[0063] The polysilicon 38 is etched back to completely remove the polysilicon 38 on the surface 36a of the insulating oxide layer. At this time, only the deep groove polysilicon 38a in the deep oxidation groove 37 is retained. Fig.12As shown; the so-called etch back is to etch the polysilicon uniformly without photoresist as a mask;

[0064] The insulating oxide layer 36 from which the polysilicon 38 is removed is subjected to the processes of coating, exposure, development, etching SiO2, degumming, cleaning, etc., and a portion of the insulating oxide layer 36 is etched away to form a cover sealing area 42, a TSV conductive column 43, and a lower concave cavity area 44. The area not etched under the protection of the photoresist forms TSV isolation grooves 40a and 40b, as shown in FIG. Fig.13 As shown;

[0065] The cover wafer substrate 30 is further processed, and a bonding metal layer 45 is deposited thereon by sputtering, evaporation, or electroplating. The bonding metal layer 45 is made of a metal that can be eutectic bonded with Si in a low temperature region (below 500° C.), such as Au, Al, Au-Sn, etc., and has a thickness of 0.2 μm to 2 μm. Then, the bonding metal layer 45 is divided into four parts, namely, a metal sealing ring 46, a first bonding metal block 47, a second bonding metal block 48, and a metal wire 49, by processes such as coating, exposure, development, etching SiO2, degumming, and cleaning. Fig.14 As shown, the metal sealing ring 46 is located above the cover sealing area 42, the first bonding metal block 47 is located above the TSV conductive column 43, the second bonding metal block 48 is located above the insulating oxide layer 36 in the lower cavity 32, the metal wire 49 connects the second bonding metal block 48, and forms an electrical contact surface 49a with the deep trench polysilicon 38a in the TSV, the second bonding metal block 48 is electrically connected to the deep trench polysilicon 38a, and the first bonding metal block 47 and the second bonding metal block 48 are on the same plane, thereby forming a cover wafer 3 with a TSV structure.

[0066] (4) Fabrication of a bonding wafer 4 having a TSV structure:

[0067] The cover wafer 3 with the TSV structure and the MEMS structure wafer 2 are aligned and bonded to form a bonding wafer 4 with a TSV structure, as shown in FIG. Fig.15As shown, the first bonding metal block 47 on the cover wafer 3 is eutectically bonded to the Si on the first MEMS bonding column 24a of the MEMS structure wafer 2 to form a first conductive bonding surface 57, and the electrical signal of the portion of the MEMS structure 25 connected to the first MEMS bonding column 24a is connected to the TSV conductive column 43 of the TSV structure; the second bonding metal block 48 on the cover wafer 3 is eutectically bonded to the Si on the second MEMS bonding column 24b of the MEMS structure wafer 2 to form a second conductive bonding surface 58, and the electrical signal of the portion of the MEMS structure 25 connected to the first MEMS bonding column 24a is connected to the TSV conductive column 43 of the TSV structure. The electrical signal of the part connected to the S bonding column 24b is connected to the deep groove polysilicon 38a in the TSV isolation groove 40b through the second conductive bonding surface 58, the metal wire 49 and the electrical contact surface 49a; the sealing metal ring 46 on the cover wafer 3 is eutectic bonded with the Si on the MEMS sealing area 22 to form a sealing bonding surface 55, and the cover wafer 3, the sealing metal ring 46, the sealing bonding surface 55, the MEMS sealing area 22, the bottom plate insulating layer 12 and the bottom plate wafer 1 form a sealed cavity 53, providing a freely movable sealed space for the MEMS structure 25.

[0068] (5) Making a thinned disc 5:

[0069] The cover plate wafer 3 of the bonded wafer 4 is ground and polished to expose the deep groove polysilicon 38a, form the cover plate outer surface 30e, and form a thinned wafer 5, such as Fig.16 As shown, at this time, the TSV conductive pillar 43 is electrically insulated from other parts of the cover wafer 3 by the TSV isolation grooves 40a and 40b to form a complete TSV structure 59, and the oxide deep groove 37 plays an insulating role.

[0070] (6) Making finished wafer 6:

[0071] An insulating layer 60 is formed on the outer surface 30e of the cover of the thinned wafer 5, such as Fig.17 As shown, its thickness is usually 0.5 to 5 μm, and there are many choices of materials, such as CVD silicon dioxide, CVD silicon nitride, SOG, polyimide, etc., or a combination thereof;

[0072] Contact holes 62a, 62b, 62c and 62d are formed on the surface of the insulating layer 60 through processes such as coating, exposure, development, etching, degumming and cleaning, wherein the TSV conductive pillars 43 are exposed in the contact holes 62a and 60d, and the deep trench polysilicon 38a is exposed in the contact holes 62b and 62c. Fig.18 As shown;

[0073] A top metal 65 is deposited on the insulating layer 60 with the contact holes 62a, 62b, 62c and 62d, as the material for the metal wiring and the package pad, such as Fig.19As shown, the contact holes 62a, 62b, 62c and 62d are all filled with the top metal 65, and the deep trench polysilicon 38a and the TSV conductive pillar 43 are all connected to the top metal 65;

[0074] Through the processes of coating, exposure, developing, etching, degumming, cleaning, etc., the top metal 65 is etched into top metal patterns 65a, 65b, 65c and 65d, such as Fig. 20 As shown, the top metal patterns 65a and 65d are connected to the TSV conductive column 43, and the top metal patterns 65b and 65c are connected to the deep trench polysilicon 38a; the top metal patterns 65a, 65b, 65c, and 65d act as wires and pressure-bonded metal blocks in subsequent packaging, thereby completing the production of the finished wafer 6.

[0075] (7) Cutting to form a MEMS chip 7 having a TSV structure:

[0076] The finished wafer 6 is cut by a common wafer cutting method to form a MEMS chip 7 with a TSV structure, wherein the bottom plate wafer 1 is cut into a bottom plate 1' of the MEMS chip 7, and the cover plate wafer 3 is cut into a cover plate 3' of the MEMS chip 7. Fig.21 shown.

[0077] The structure of the MEMS chip 7 with TSV structure of the present invention is as follows Fig.21 As shown, it includes a base plate 1', a MEMS structure layer 18, a bonding metal layer 45, a cover plate 3', an insulating layer 60 and top metal patterns 65a, 65b, 65c, 65d;

[0078] The material of the bottom plate 1' is single crystal silicon, and its resistivity is 0.001-0.1Ω*CM, and its thickness is 300-500μm. Five upper concave cavities 15 are etched on the bottom plate 1', and the depth of the upper concave cavities 15 is 10-100μm. The upper concave cavities 15 isolate the bottom plate 1' into a bottom plate sealing area 16 and a support column 17. The bottom plate sealing area 16 and the support column 17 are both provided with a bottom plate insulating layer 12, and the material of the bottom plate insulating layer 12 is SiO2, and the thickness is 1-2μm.

[0079] The material of the MEMS structure layer 18 is also single crystal silicon, with a thickness of 10 to 100 μm. The MEMS structure layer 18 includes a MEMS sealing area 22, a first MEMS bonding column 24a, a second MEMS bonding column 24b and a MEMS structure 25. The heights of the first MEMS bonding column 24a and the second MEMS bonding column 24b are both 0.5 to 5 μm.

[0080] The bottom plate 1' is mechanically connected to the MEMS structure layer 18 through the bottom plate insulating layer 12, and there is no electrical connection between the bottom plate 1' and the MEMS structure layer 18;

[0081] The cover plate 3' is made of single crystal silicon. The cover plate 3' has a lower concave cavity 32, two TSV isolation grooves 40a and two TSV isolation grooves 40b. The TSV isolation grooves 40a and 40b isolate the cover plate 3' into a cover plate sealing area 42, a TSV conductive column 43 and a lower concave cavity area 44. The TSV isolation grooves 40a and 40b are composed of an oxidized deep groove 37 covered with an insulating oxide layer 36 and a deep groove polysilicon 38a filled in the oxidized deep groove 37.

[0082] The cover plate 3' is bonded to the MEMS structure layer 18 through a bonding metal layer 45. The material of the bonding metal layer 45 is a metal that can be eutectic bonded with Si in a low temperature zone (below 500°C), such as Au, Al, Au-Sn, etc., with a thickness of 0.2μm to 2μm. The bonding metal layer 45 includes a metal sealing ring 46, a first bonding metal block 47, a second bonding metal block 48, and a metal wire 49. Among them, the first bonding metal block 47 and the second bonding metal block 48 are on the same plane, the sealing metal ring 46 is eutectic bonded to the MEMS sealing area 22, the first bonding metal block 47 is eutectic bonded to the first MEMS bonding column 24a, and the first MEMS bonding column 24a in the MEMS structure 25 is eutectic bonded to the first MEMS bonding column 24a. The electrical signal of the portion connected to the bonding column 24a is connected to the TSV conductive column 43 through the first bonding metal block 47; the second bonding metal block 48 is eutectic bonded to the second MEMS bonding column 24b, and the metal wire 49 simultaneously connects the second bonding metal block 48 and the deep trench polysilicon 38a, and the electrical signal of the portion connected to the second MEMS bonding column 24b in the MEMS structure 25 is connected to the deep trench polysilicon 38a in the TSV isolation groove 40b through the second bonding metal block 48 and the metal wire 49; the cover plate 3', the sealing metal ring 46, the MEMS sealing area 22, the bottom plate insulating layer 12 and the bottom plate 1' together form a sealed cavity 53, providing a freely movable sealed space for the MEMS structure 25.

[0083] An insulating layer 60 is also made on the cover plate 3'. The thickness of the insulating layer 60 is 0.5-5μm. The material can be CVD silicon dioxide, CVD silicon nitride, SOG, polyimide or a combination thereof. Contact holes 62a, 62b, 62c and 62d are etched on the insulating layer 60, wherein the TSV conductive pillars 43 are exposed in the contact holes 62a and 60d, and the deep groove polysilicon 38a is exposed in the contact holes 62b and 62c; there are top metal patterns 65a, 65b, 65c and 65d on the insulating layer 60, wherein the top metal patterns 65a and 65d are connected to the TSV conductive pillars 43, and the top metal patterns 65b and 65c are connected to the deep groove polysilicon 38a; the top metal patterns 65a, 65b, 65c, 65d play the role of wires and metal bonding pads in subsequent packaging.

[0084] from Fig.21It can be seen that the first signal connected to the first MEMS bonding column 24a in the MEMS structure 25 is connected to the top-level metal graphics 65a and 65d through the first metal bonding block 47 and the TSV conductive column 43; similarly, the second signal connected to the second MEMS bonding column 24b in the MEMS structure 25 is connected to the top-level metal graphics 65b and 65c through the second metal bonding block 48, the metal wire 49, and the deep trench polysilicon 38a in the TSV isolation groove 40b; in this way, the purpose of conducting two electrical signals by one TSV structure is achieved.

[0085] In order to more clearly illustrate the method of leading out two electrical signals from a TSV structure, Fig. 22 Shown Fig.21 The top view of the middle M portion, in which the insulating layer 60 is not drawn, the TSV isolation grooves 40a and 40b are actually the two sides of the isolation groove of the circular or elliptical ring TSV structure 59, the deep groove polysilicon 38a is electrically isolated from the TSV conductive column 43 and other parts of the cover plate 3' by the annular oxide deep groove 37, and of course, the TSV conductive column 43 and other parts of the cover plate 3' are also electrically insulated by the TSV isolation grooves 40a and 40b; the top metal pattern 65c leads out the electrical signal of the deep groove polysilicon 38a, and the top metal pattern 65d leads out the electrical signal of the TSV conductive column 43.

Claims

1. A MEMS chip with a TSV structure, which is composed of a cover plate, a MEMS structure layer and a base plate. The materials of the cover plate, the MEMS structure layer and the base plate are all single crystal silicon. The base plate has at least one upper cavity, and the cover plate has at least one lower cavity. The upper cavity and the lower cavity together form a sealed cavity. The MEMS structure of the MEMS structure layer is located in the sealed cavity and can move freely in the sealed cavity. The base plate is mechanically connected to the MEMS structure layer through a base plate insulating layer. The material of the base plate insulating layer is SiO2. The cover plate is bonded to the MEMS structure layer through a bonding metal layer. The invention is characterized in that: The cover plate is composed of a cover plate sealing area, a TSV isolation groove, a TSV conductive column and a lower concave cavity area. The TSV isolation groove is located between the cover plate sealing area and the TSV conductive column and between the TSV conductive column and the lower concave cavity area. The TSV isolation groove is composed of an oxidized deep groove and a deep groove polysilicon filled in the oxidized deep groove. The oxidized deep groove is composed of a deep groove etched on the cover plate and an insulating oxide layer covering the inner wall of the deep groove. The MEMS structure layer includes a MEMS sealing area, a first MEMS bonding column, a second MEMS bonding column and a MEMS structure; The bonding metal layer includes a metal sealing ring, a first bonding metal block, a second bonding metal block and a metal wire, wherein the sealing metal ring is eutectic bonded to the MEMS sealing area, the first bonding metal block is eutectic bonded to the first MEMS bonding column, the second bonding metal block is eutectic bonded to the second MEMS bonding column, and the metal wire simultaneously connects the second bonding metal block and the deep trench polysilicon; There is an insulating layer on the cover plate, and contact holes are etched on the insulating layer, in which TSV conductive columns and deep groove polysilicon are exposed; a top metal pattern is deposited in the insulating layer and the contact hole, and the electrical signal of the MEMS structure is led out through the first bonding metal block, the TSV conductive column and the top metal pattern in the contact hole, and the other way is led out through the second bonding metal block, the metal wire, the deep groove polysilicon and the top metal pattern in the contact hole.

2. The MEMS chip with TSV structure according to claim 1, characterized in that: The material of the bonding metal layer is a metal that can eutectically bond with Si at a temperature below 500°C.

3. The MEMS chip with TSV structure according to claim 1 or 2, characterized in that: The surface of the lower concave cavity of the cover plate is also covered with an insulating oxide layer, and the second bonding metal block is located on the insulating oxide layer of the lower concave cavity.

4. The MEMS chip with TSV structure according to claim 3, characterized in that: The metal sealing ring, the first bonding metal block and the second bonding metal block are located on the same plane.

5. A wafer-level hermetic packaging method for a MEMS chip having a TSV structure, comprising the following steps: (1) Making the bottom plate disc: A heavily doped single crystal silicon wafer is selected as a bottom plate wafer substrate, the bottom plate wafer substrate is thermally oxidized, a bottom plate insulating layer is grown on the surface of the bottom plate wafer substrate, and the bottom plate wafer substrate with the bottom plate insulating layer grown thereon is etched to form an upper concave cavity, thereby completing the manufacture of the bottom plate wafer; (2) Making MEMS structure wafers: Bonding a double-sided polished single-crystal silicon wafer to the bottom plate wafer produced in step (1), and grinding it to 10 to 100 μm to form a MEMS structure layer; Etch the MEMS structure layer to form the MEMS sealing area and MEMS bonding column, and then perform deep silicon etching to form the MEMS structure to complete the production of the MEMS structure wafer; (3) Fabrication of a cover wafer with a TSV structure: Another double-sided polished single-crystal silicon wafer is used as the cover wafer substrate, and a concave cavity is etched on the inner surface of the cover wafer substrate, and then a deep groove is etched; after thermal oxidation etching, an insulating oxide layer is generated on the surface of the cover wafer substrate and the inner wall of the deep groove, and the insulating oxide layer of the deep groove and its inner wall together form an oxidized deep groove, and then polysilicon is deposited on the insulating oxide layer, and the polysilicon filled in the oxidized deep groove becomes deep groove polysilicon; the polysilicon is etched back to remove all the polysilicon on the surface of the insulating oxide layer, and only the deep groove polysilicon in the oxidized deep groove is retained to form a TSV isolation groove; and then the insulating oxide layer is etched to expose part of the cover wafer substrate , forming a cover plate sealing area, a TSV conductive column and a lower concave cavity area, the TSV conductive column and other parts of the cover plate wafer are electrically insulated by the TSV isolation groove to form a complete TSV structure; then a bonding metal layer is deposited on the cover plate wafer substrate, and etched to form a metal sealing ring, a first bonding metal block, a second bonding metal block and a metal wire, wherein the metal sealing ring is located above the cover plate sealing area, the first bonding metal block is located above the TSV conductive column, the second bonding metal block is located above the insulating oxide layer in the lower concave cavity, and the metal wire connects the second bonding metal block and the deep trench polysilicon, thus completing the manufacture of a cover plate wafer with a TSV structure; (4) Fabrication of a bonding wafer with a TSV structure: Align and bond the cover wafer with TSV structure made in step (3) and the MEMS structure wafer made in step (2) to form a bonded wafer with TSV structure; wherein the first bonding metal block is eutectic bonded to the first MEMS bonding column, and the electrical signal of the part connected to the first MEMS bonding column in the MEMS structure is connected to the TSV conductive column; the second bonding metal block is eutectic bonded to the second MEMS bonding column, and the electrical signal of the part connected to the second MEMS bonding column in the MEMS structure is connected to the deep groove polysilicon through a metal wire; the sealing metal ring is eutectic bonded to the MEMS sealing area to form a sealing bonding surface, and the cover wafer, the sealing metal ring, the sealing bonding surface, the MEMS sealing area, the bottom plate insulating layer and the bottom plate wafer together form a sealing cavity to provide a free-moving sealing space for the MEMS structure; (5) Making thinned wafers: Grinding and polishing the cover wafer of the bonded wafer with TSV structure manufactured in step (4) to expose the deep groove polysilicon and form a thinned wafer; (6) Making finished wafers: An insulating layer is formed on the thinned wafer in step (5), and the insulating layer is etched to form contact holes, in which the TSV conductive pillars and deep groove polysilicon are respectively exposed; a top layer of metal is then deposited on the insulating layer, and the contact holes are also filled with the top layer of metal, and the deep groove polysilicon and the TSV conductive pillars are connected to the top layer of metal through the contact holes; the top layer of metal is etched to form a top layer of metal pattern, and the top layer of metal pattern is respectively connected to the TSV conductive pillars and the deep groove polysilicon, thereby completing the production of a finished wafer; (7) Cutting to form a MEMS chip with TSV structure: Cutting the finished wafers by a common wafer cutting method to form a MEMS chip with a TSV structure, wherein the bottom plate wafer is cut to become a bottom plate of the MEMS chip with a TSV structure, and the cover plate wafer is cut to become a cover plate of the MEMS chip with a TSV structure; The etching mentioned above refers to mask etching.

6. The wafer-level airtight packaging method of a MEMS chip with a TSV structure according to claim 5, characterized in that: The metal sealing ring, the first bonding metal block and the second bonding metal block in step (3) are on the same plane.

7. The wafer-level airtight packaging method of a MEMS chip with a TSV structure according to claim 5 or 6, characterized in that: The material of the bonding metal layer in step (3) is a metal that can eutectic bond with Si at a temperature below 500°C.

8. The wafer-level airtight packaging method of a MEMS chip with a TSV structure according to claim 7, characterized in that: The material of the bonding metal layer is Au, Al or Au-Sn.

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