A pulse latch unit structure

Abstract

The present invention relates to a pulse latch unit structure, comprising a first PMOS tube, a first NMOS tube, a second PMOS tube, a second NMOS tube and a gate control unit DUC, and realizing a latching function of an input signal. The present invention can be widely used in the structure of constructing a latch, and is suitable for fields with high requirements on the reliability and comprehensive cost of the latch.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuit anti-single particle upset reinforcement, and in particular to a pulse latch unit structure. Background Art

[0002] With the rapid development of semiconductor technology, digital integrated circuits are increasingly susceptible to single-particle upsets caused by space radiation. Latches are sequential circuit units with storage structures that work in space radiation environments for a long time. As the basic structure of latches, the necessary single-particle upset reinforcement design for latch units is of great significance to improving the reliability of integrated circuits.

[0003] Currently, the main problems with the structural design of the latch unit are: the latch unit has low portability, large area overhead and high power consumption. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a novel pulse latch unit in view of the defects involved in the background technology.

[0005] The present invention adopts the following technical solutions to solve the above technical problems:

[0006] A pulse latch unit structure comprises a first PMOS tube, a first NMOS tube, a second PMOS tube, a second NMOS tube and a gate control unit;

[0007] The gate control unit comprises a first input terminal, a second input terminal and an inverting output terminal, wherein the second input terminal is used to input an external inverted clock signal, and the inverting input terminal is used to invert and output the signal input from the first signal input terminal;

[0008] The source of the first NMOS tube is respectively connected to the source of the second PMOS tube, the first input terminal of the gate control unit, the gate of the first NMOS tube, and the gate of the second PMOS tube, and the drain of the first NMOS tube is connected to the drain of the first PMOS tube;

[0009] The source of the first PMOS tube is connected to an external power supply, and the gate is connected to the gate of the second NMOS tube and the inverting output end of the gate control unit respectively;

[0010] The drain of the second PMOS tube is connected to the source of the second NMOS tube;

[0011] The source of the second NMOS tube is grounded.

[0012] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0013] The present invention has the characteristics of strong portability and low area cost, and adopts clock control technology to effectively reduce power consumption cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a structural schematic diagram of the present invention. DETAILED DESCRIPTION

[0015] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0016] The present invention can be implemented in many different forms and should not be considered to be limited to the embodiments described herein. On the contrary, these embodiments are provided to make this disclosure thorough and complete, and will fully express the scope of the present invention to those skilled in the art. In the accompanying drawings, components are enlarged for clarity.

[0017] like Figure 1 As shown, the present invention discloses a pulse latch unit structure, comprising a first PMOS tube, a first NMOS tube, a second PMOS tube, a second NMOS tube and a gate control unit;

[0018] The gate control unit comprises a first input terminal, a second input terminal and an inverting output terminal, wherein the second input terminal is used to input an external inverted clock signal, and the inverting input terminal is used to invert and output the signal input from the first signal input terminal;

[0019] The source of the first NMOS tube is respectively connected to the source of the second PMOS tube, the first input terminal of the gate control unit, the gate of the first NMOS tube, and the gate of the second PMOS tube, and the drain of the first NMOS tube is connected to the drain of the first PMOS tube;

[0020] The source of the first PMOS tube is connected to an external power supply, and the gate is respectively connected to the gate of the second NMOS tube and the inverting output end of the gate control unit;

[0021] The drain of the second PMOS tube is connected to the source of the second NMOS tube;

[0022] The source of the second NMOS tube is grounded.

[0023] The working principle of the pulse latch unit proposed in the present invention is described below. The specific working principle is as follows:

[0024] The signal at the signal input terminal I is first directly transmitted to the signal output terminal OUT. At this time, the signal at the signal output terminal OUT will generate two kinds of feedback respectively: the first is directly fed back to the gates of the first NMOS tube and the second PMOS tube, and the second is fed back to the gates of the first PMOS tube and the second NMOS tube after passing through the gating unit DUC. Furthermore, after transmission through the MOS tube, the signal output terminal OUT will maintain the original value unchanged, thereby realizing the function of temporarily storing the signal.

[0025] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless defined as herein.

[0026] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A pulse latch unit structure, characterized in that: It includes a first PMOS tube, a first NMOS tube, a second PMOS tube, a second NMOS tube and a gate control unit; The gate control unit comprises a first input terminal, a second input terminal and an inverting output terminal, wherein the second input terminal is used to input an external inverted clock signal, and the inverting input terminal is used to invert and output the signal input from the first signal input terminal; The source of the first NMOS tube is respectively connected to the source of the second PMOS tube, the first input terminal of the gate control unit, the gate of the first NMOS tube, and the gate of the second PMOS tube, and the drain of the first NMOS tube is connected to the drain of the first PMOS tube; The source of the first PMOS tube is connected to an external power supply, and the gate is connected to the gate of the second NMOS tube and the inverting output end of the gate control unit respectively; The drain of the second PMOS tube is connected to the source of the second NMOS tube; The source of the second NMOS tube is grounded.

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