Semiconductor device with shallow trench isolation structure and preparation method thereof
By setting a buffer layer and an insulating dielectric layer in the trench of the semiconductor device, the problem of the formation of conductive channels in the dynamic random access memory is solved, the leakage current and stress distribution are improved, and the electrical performance of the device is improved and yield.
Patent Information
- Application Number
- CN201811037270.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2018-09-06
- Publication Date
- 2025-01-10
- Estimated Expiration
- 2038-09-06
AI Technical Summary
After the existing shallow trench isolation layer is reduced in size in dynamic random access memory, it is easy to form conductive channels, resulting in leakage current problems and affecting the electrical performance and product yield of semiconductor devices.
At least one trench is formed on the substrate, the groove wall of the trench is provided with a buffer layer, and the insulating dielectric layer is filled with the surface of the buffer layer, and the insulating dielectric layer is filled with the trench to prevent the hot carrier from jumping to form a conductive channel. The buffer layer reduces stress between the substrate and the insulating dielectric layer.
The formation of conductive channels is effectively prevented, the leakage current problem of semiconductor devices is improved, and the stress distribution between the substrate and the insulating dielectric layer is improved.
Smart Images
Figure CN110880472B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device with a shallow trench isolation structure and a method for preparing the semiconductor device with the shallow trench isolation structure. Background Art
[0002] The shallow trench isolation (STI) process is a commonly used semiconductor device isolation process. The shallow trench isolation process can be used to isolate multiple memory cells and enable the multiple memory cells to work independently without being affected by voltage or current changes of adjacent memory cells.
[0003] As the size of current dynamic random access memory (DRAM) shrinks, the width of the shallow trench isolation layer becomes smaller, and hot carriers jumping into the shallow trench isolation layer can easily form a conductive channel, thereby generating leakage current, affecting the electrical performance and product yield of semiconductor devices.
[0004] Therefore, it is necessary to study a new semiconductor device with a shallow trench isolation structure and a method for preparing a semiconductor device with a shallow trench isolation structure.
[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute the prior art that is already known to a person of ordinary skill in the art. Summary of the invention
[0006] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art in that a conductive channel is easily formed, and to provide a semiconductor device with a shallow trench isolation structure in which a conductive channel is not easily formed, and a method for preparing a semiconductor device with a shallow trench isolation structure.
[0007] Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
[0008] According to one aspect of the present disclosure, a semiconductor device having a shallow trench isolation structure is provided, comprising:
[0009] a substrate having at least one groove disposed thereon;
[0010] A buffer layer is provided on the groove wall of the groove;
[0011] The insulating dielectric layer is disposed on the surface of the buffer layer and fills the groove.
[0012] In an exemplary embodiment of the present disclosure, the buffer layer includes:
[0013] A first buffer thin layer, disposed on the groove wall of the groove;
[0014] The second buffer thin layer is arranged between the first buffer thin layer and the insulating medium layer.
[0015] In an exemplary embodiment of the present disclosure, the thickness of the first buffer thin layer is greater than or equal to 5 nm and less than or equal to 30 nm.
[0016] In an exemplary embodiment of the present disclosure, the thickness of the second buffer thin layer is greater than or equal to 10 nm and less than or equal to 100 nm.
[0017] In an exemplary embodiment of the present disclosure, the first buffer thin layer is one or more of silicon oxide, polysilicon, and silicon oxynitride.
[0018] In an exemplary embodiment of the present disclosure, the second buffer thin layer is one or more of silicon oxide, polysilicon, and silicon oxynitride.
[0019] In an exemplary embodiment of the present disclosure, the insulating dielectric layer is one or both of silicon nitride and silicon oxynitride.
[0020] In an exemplary embodiment of the present disclosure, the thickness of the insulating dielectric layer is greater than or equal to 10 nm and less than or equal to 200 nm.
[0021] According to one aspect of the present disclosure, a method for preparing a semiconductor device having a shallow trench isolation structure is provided, comprising:
[0022] Providing a substrate, and forming at least one trench on the substrate;
[0023] forming a buffer layer on the groove wall of the groove;
[0024] An insulating dielectric layer is formed on the surface of the buffer layer, and the insulating dielectric layer fills the trench.
[0025] In an exemplary embodiment of the present disclosure, forming a buffer layer on the groove wall of the groove includes:
[0026] forming a polysilicon layer on a groove wall of the groove;
[0027] forming a first silicon oxide layer on a surface of the polysilicon layer;
[0028] The polysilicon layer is subjected to an in-situ water vapor generation process to form a second silicon oxide layer.
[0029] In an exemplary embodiment of the present disclosure, the thickness of the polysilicon layer is greater than or equal to 5 nm and less than or equal to 30 nm.
[0030] In an exemplary embodiment of the present disclosure, the thickness of the first silicon oxide layer is greater than or equal to 10 nm and less than or equal to 100 nm.
[0031] In an exemplary embodiment of the present disclosure, the polysilicon layer is formed by a low pressure chemical vapor deposition method, and the reaction temperature is greater than or equal to 400° C. and less than or equal to 800° C.
[0032] In an exemplary embodiment of the present disclosure, the first silicon oxide layer is formed by an atomic layer deposition method, and the reaction temperature is greater than or equal to 500° C. and less than or equal to 1000° C.
[0033] In an exemplary embodiment of the present disclosure, the reaction temperature of the in-situ steam generation process is greater than or equal to 900° C. and less than or equal to 1100° C.
[0034] In an exemplary embodiment of the present disclosure, the polysilicon layer is formed by atomic layer deposition or fluid chemical vapor deposition, and the first silicon oxide layer is formed by chemical vapor deposition or fluid chemical vapor deposition.
[0035] In an exemplary embodiment of the present disclosure, the insulating dielectric layer is one or both of silicon nitride and silicon oxynitride.
[0036] In an exemplary embodiment of the present disclosure, the thickness of the insulating dielectric layer is greater than or equal to 10 nm and less than or equal to 200 nm.
[0037] In an exemplary embodiment of the present disclosure, the insulating dielectric layer is formed on the surface of the buffer layer by atomic layer deposition at a temperature greater than or equal to 400° C. and less than or equal to 800° C.
[0038] In an exemplary embodiment of the present disclosure, the insulating dielectric layer is formed on the surface of the buffer layer by chemical vapor deposition or fluid chemical vapor deposition.
[0039] In an exemplary embodiment of the present disclosure, at least one trench is formed on the substrate, comprising:
[0040] forming a silicon dioxide film on the substrate;
[0041] forming a photomask layer on the silicon dioxide film;
[0042] The photomask layer, the silicon dioxide film and the substrate are masked and etched to form at least one groove.
[0043] It can be seen from the above technical solution that the present invention has at least one of the following advantages and positive effects:
[0044] The semiconductor device with shallow trench isolation structure and the preparation method thereof of the present invention are provided with at least one trench on the substrate, a buffer layer is provided on the trench wall of the trench, an insulating dielectric layer is provided on the surface of the buffer layer, and the insulating dielectric layer fills the trench. On the one hand, it is difficult for hot carriers to jump to the insulating dielectric layer, so that no conductive channel is formed, which can improve the leakage current of the semiconductor device; on the other hand, the buffer layer is provided between the substrate and the insulating dielectric layer, which can improve the stress between the substrate and the insulating dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0045] The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
[0046] Figure 1 It is a schematic structural diagram of forming a pad silicon oxide layer and a pad silicon nitride layer on a silicon substrate in the related art;
[0047] Figure 2 is Figure 1 A schematic diagram of a structure in which a shallow groove is formed on the basis of the substrate;
[0048] Figure 3 is Figure 2 A schematic diagram of a dielectric material of silicon dioxide formed on the basis of a structure;
[0049] Figure 4 is Figure 3 A schematic diagram of a structure in which excess dielectric material near silicon dioxide is removed;
[0050] Figure 5 is Figure 4 A schematic diagram of a three-dimensional structure of a semiconductor device ground onto a silicon surface based on the method;
[0051] Figure 6 is a schematic diagram of leakage current of a semiconductor device having a shallow trench isolation structure in the related art;
[0052] Figure 7 It is a schematic diagram of the three-dimensional structure of a semiconductor device with a shallow trench isolation structure according to the present invention ground to a silicon surface;
[0053] Figure 8 It is a schematic flow chart of a method for preparing a semiconductor device with a shallow trench isolation structure according to the present invention;
[0054] Fig. 9 It is a schematic diagram of a structure in which a pad oxide layer, a photomask layer and a pattern are formed on a substrate;
[0055] Fig.10 is Fig. 9 A schematic diagram of a structure in which a groove is formed on the basis of the present invention;
[0056] Fig.11 is Fig.10 A schematic diagram of a structure for removing a photomask layer based on the above;
[0057] Fig.12 is Fig.11 A schematic diagram of a structure in which a polysilicon layer is formed on the basis of;
[0058] Fig.13 is Fig.12 A schematic diagram of a structure in which a first silicon oxide layer is formed on the basis of
[0059] Fig.14 is Fig.13 A schematic diagram of a structure in which a second silicon oxide layer is formed on the basis of
[0060] Fig.15 is Fig.14 A schematic diagram of a structure in which an insulating dielectric layer is formed on the basis of
[0061] Fig.16 It is a schematic diagram of the electron distribution structure of the semiconductor device with shallow trench isolation structure of the present invention.
[0062] The main components in the figure are described as follows:
[0063] 1. Silicon substrate; 2. Pad silicon oxide layer; 3. Pad silicon nitride layer; 4. Shallow trench; 5. Dielectric material of silicon dioxide;
[0064] 6. Pad silicon dioxide film; 7. Polysilicon film; 8. Carbon film; 9. Silicon oxynitride film; 10. Photoresist; 11. Groove;
[0065] 121, a polysilicon layer; 122, a first silicon oxide layer; 123, a second silicon oxide layer;
[0066] 13. Silicon nitride layer; 14. Source; 15. Drain. DETAILED DESCRIPTION
[0067] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.
[0068] Reference Figure 1 to Figure 5A schematic structural diagram of each process of forming a shallow trench isolation structure in the related technology shown; currently, a pad silicon oxide layer 2 is first formed on a silicon substrate 1, and a pad silicon nitride layer 3 is formed on the pad silicon oxide layer 2; then a shallow trench 4 is formed by a mask and etching process; then a liquid solvent containing a dielectric material is evenly coated on the surface of the wafer by a spin coating method to fill the shallow trench 4 formed above, and then heat treated to remove the solvent, and a dielectric material 5 of silicon dioxide (SiO2) is formed after curing (Curing) on the surface of the wafer. The hot carriers of highly integrated semiconductor MOS transistors usually have high energy, and the hot carriers can easily jump into the shallow trench isolation layer composed of SiO2. The hot carriers that jump into the shallow trench isolation layer are mainly negative charges, i.e., electrons. In addition, referring to Figure 6 The schematic diagram of hot carriers forming a conductive channel in the related art is shown. The source 14 and the drain 15 are respectively arranged on both sides of the dielectric material 5 of silicon dioxide.
[0069] The present invention provides a semiconductor device with a shallow trench isolation structure, referring to Figure 7 The three-dimensional structural schematic diagram of the semiconductor device with a shallow trench isolation structure of the present invention is shown; the semiconductor device may include a substrate, a buffer layer and an insulating dielectric layer; at least one trench 11 is provided on the substrate; the buffer layer is provided on the trench wall of the trench 11; the insulating dielectric layer is provided on the surface of the buffer layer and fills the trench 11.
[0070] In this example embodiment, the substrate may be a silicon substrate 1 , and the substrate may also be silicon nitride, silicon carbide, or the like.
[0071] In this example embodiment, the buffer layer may include a first buffer thin layer and a second buffer thin layer. The first buffer thin layer has a thickness greater than or equal to 5 nm and less than or equal to 30 nm. The second buffer thin layer has a thickness greater than or equal to 10 nm and less than or equal to 100 nm.
[0072] The first buffer thin layer is arranged on the groove wall of the groove 11, that is, the first buffer thin layer covers the groove wall of the groove 11 to form a new first groove, and the width of the first groove is narrower than the width of the original groove 11. In this exemplary embodiment, the first buffer thin layer is a polysilicon layer 121 that is processed by an in-situ water vapor generation process to form a second silicon oxide layer 123, that is, the polysilicon layer 121 is first formed, and then the polysilicon layer 121 is processed by an in-situ water vapor generation process to form the second silicon oxide layer 123. The second silicon oxide layer 123 formed by the in-situ water vapor generation process has fewer interface defects with the silicon substrate 1 and the first silicon oxide layer 122. In addition, the high temperature process of the in-situ water vapor generation process can reduce the internal stress of the silicon substrate 1. Of course, the first buffer thin layer can also be polysilicon or silicon oxynitride, or a mixture thereof.
[0073] The second buffer thin layer is arranged between the first buffer thin layer and the insulating dielectric layer, that is, the second buffer thin layer is arranged on the groove wall of the first groove formed by the first buffer thin layer, and the second buffer thin layer forms a new second groove, and the width of the second groove is narrower than the width of the first groove. In this example embodiment, the material of the second buffer thin layer is silicon oxide. Of course, the second buffer thin layer can also be polysilicon or silicon oxynitride, or a mixture thereof.
[0074] In this exemplary embodiment, the insulating dielectric layer is disposed in the second trench formed by the second buffer thin layer and fills the second trench. The insulating dielectric layer may be a silicon nitride layer 13, and the thickness of the silicon nitride layer 13 may be greater than or equal to 10 nm and less than or equal to 200 nm. The insulating dielectric layer may be a highly polar covalent compound with a dense structure. For example, the insulating dielectric layer may also be silicon oxynitride or a mixture of silicon nitride and silicon oxynitride.
[0075] Furthermore, the present invention also provides a method for preparing a semiconductor device having a shallow trench isolation structure, referring to Figure 8 The schematic flowchart of the method for preparing a semiconductor device with a shallow trench isolation structure is shown; the method may include the following steps:
[0076] Step S10: providing a substrate and forming at least one trench 11 on the substrate.
[0077] In step S20 , a buffer layer is formed on the wall of the trench 11 .
[0078] Step S30 , forming an insulating dielectric layer on the surface of the buffer layer, and the insulating dielectric layer fills the trench 11 .
[0079] The following describes in detail the various steps of the method for preparing the semiconductor device with a shallow trench isolation structure.
[0080] Step S10: providing a substrate and forming at least one trench 11 on the substrate.
[0081] In this example embodiment, the substrate may be a silicon substrate 1. Fig. 9 The schematic diagram of the structure of forming a pad oxide layer, a photomask layer and a pattern on a substrate is shown; a pad silicon dioxide film 6 is first oxidized on a silicon substrate 1, and the thickness of the pad silicon dioxide film 6 is greater than or equal to 50nm and less than or equal to 150nm. Then a photomask layer and a photoresist 10 are deposited on the pad silicon dioxide film 6, and the photomask layer is a polysilicon film 7, a carbon film 8, and a silicon oxynitride film 9 from bottom to top; wherein the thickness of the polysilicon film 7 is greater than or equal to 30nm and less than or equal to 80nm, the thickness of the carbon film 8 is greater than or equal to 50nm and less than or equal to 150nm, and the thickness of the silicon oxynitride film 9 is greater than or equal to 20nm and less than or equal to 50nm.
[0082] Reference Fig.10 As shown in Fig. 9 The schematic diagram of the structure of forming a groove 11 on the basis of the present invention; the silicon substrate 1, the pad silicon dioxide film 6, the polysilicon film 7, the carbon film 8 and the silicon oxynitride film 9 can be etched by photolithography, etching and other processes to form the groove 11, and the depth-to-width ratio of the groove 11 is 10 to 30.
[0083] Reference Fig.11 As shown in Fig.10 The residual polysilicon film 7, carbon film 8, silicon oxynitride film 9 and photoresist 10 can be removed by etching, cleaning, mechanical planarization and other processes.
[0084] In step S20 , a buffer layer is formed on the wall of the trench 11 .
[0085] In this exemplary embodiment, the polysilicon layer 121 may be formed on the wall of the trench 11 by a low pressure chemical vapor deposition method. Fig.12 As shown in Fig.11 The thickness of the polysilicon layer 121 is greater than or equal to 5nm and less than or equal to 30nm. The polysilicon layer 121 provides material for the subsequent in-situ water vapor generation process to form the second silicon oxide layer 123. The reaction temperature for forming the polysilicon layer 121 is greater than or equal to 400°C and less than or equal to 800°C.
[0086] Reference Fig.13 As shown in Fig.12 The first silicon oxide layer 122 is formed on the surface of the polysilicon layer 121 by atomic layer deposition; the thickness of the first silicon oxide layer 122 is greater than or equal to 10nm and less than or equal to 100nm. The reaction temperature for forming the first silicon oxide layer 122 is greater than or equal to 500°C and less than or equal to 1000°C.
[0087] Reference Fig.14 As shown in Fig.13 The second silicon oxide layer 123 is formed on the basis of the polysilicon layer 121 by an in-situ water vapor generation process. The reaction temperature of the in-situ water vapor generation process is greater than or equal to 900° C. and less than or equal to 1100° C. The second silicon oxide layer 123 formed by the in-situ water vapor generation process has fewer interface defects with the silicon substrate 1 and the first silicon oxide layer 122. In addition, the high temperature process of the in-situ water vapor generation process can reduce the internal stress of the silicon substrate 1.
[0088] The polysilicon layer 121 may be formed by an atomic layer deposition method or a fluid chemical vapor deposition method, and the first silicon oxide layer 122 may be formed by a chemical vapor deposition method or a fluid chemical vapor deposition method.
[0089] Step S30 , forming an insulating dielectric layer on the surface of the buffer layer, and the insulating dielectric layer fills the trench 11 .
[0090] In this exemplary embodiment, the insulating dielectric layer is a silicon nitride layer 13. The silicon nitride layer 13 may be formed on the surface of the buffer layer by atomic layer deposition. Fig.15 As shown in Fig.14 The thickness of the silicon nitride layer 13 is greater than or equal to 10nm and less than or equal to 200nm. The temperature of the atomic layer deposition method is greater than or equal to 400°C and less than or equal to 800°C. The insulating dielectric layer can also be formed on the surface of the buffer layer by chemical vapor deposition or fluid chemical vapor deposition.
[0091] The semiconductor device with shallow trench isolation structure and the preparation method thereof of the present invention are provided with at least one trench 11 on the substrate, a buffer layer is provided on the trench wall of the trench 11, an insulating dielectric layer is provided on the surface of the buffer layer, and the insulating dielectric layer fills the trench 11. Fig.16 The schematic diagram of the electron distribution structure of the semiconductor device with shallow trench isolation structure of the present invention is shown. It is difficult for hot carriers to jump to the insulating dielectric layer, so that no conductive channel is formed, which can improve the leakage current of the semiconductor device; the buffer layer is arranged between the substrate and the insulating dielectric layer, which can improve the stress between the substrate and the insulating dielectric layer.
[0092] The features, structures or characteristics described above may be combined in one or more embodiments in any suitable manner, and if possible, the features discussed in each embodiment are interchangeable. In the above description, many specific details are provided to provide a full understanding of the embodiments of the present invention. However, those skilled in the art will appreciate that the technical solution of the present invention may be practiced without one or more of the specific details, or other methods, components, materials, etc. may be adopted. In other cases, known structures, materials or operations are not shown or described in detail to avoid blurring various aspects of the present invention.
[0093] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned over so that it is upside down, the component described as being "upper" will become the component "lower". Other relative terms, such as "high", "low", "top", "bottom", etc., are also used to have similar meanings. When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.
[0094] In this specification, the terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising", "including" and "having" are used to express an open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.
[0095] It should be understood that the present invention is not limited in its application to the detailed structure and arrangement of the components proposed in this specification. The present invention can have other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present invention. It should be understood that the present invention disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All these different combinations constitute multiple alternative aspects of the present invention. The embodiments described in this specification illustrate the best mode known for implementing the present invention and will enable those skilled in the art to utilize the present invention.
Claims
1. A method for preparing a semiconductor device having a shallow trench isolation structure, characterized in that: include: Providing a substrate, and forming at least one trench on the substrate; forming a buffer layer on the groove wall of the groove; forming an insulating dielectric layer on the surface of the buffer layer, wherein the insulating dielectric layer fills the groove; Forming a buffer layer on the groove wall of the groove comprises: forming a polysilicon layer on a groove wall of the groove; forming a first silicon oxide layer on a surface of the polysilicon layer; The polysilicon layer is subjected to an in-situ water vapor generation process to form a second silicon oxide layer.
2. The method for preparing a semiconductor device with a shallow trench isolation structure according to claim 1, characterized in that: The thickness of the polysilicon layer is greater than or equal to 5 nm and less than or equal to 30 nm.
3. The method for preparing a semiconductor device with a shallow trench isolation structure according to claim 1, characterized in that: The thickness of the first silicon oxide layer is greater than or equal to 10 nm and less than or equal to 100 nm.
4. The method for preparing a semiconductor device with a shallow trench isolation structure according to claim 1, characterized in that: The polysilicon layer is formed by low pressure chemical vapor deposition, and the reaction temperature is greater than or equal to 400° C. and less than or equal to 800° C.
5. The method for preparing a semiconductor device with a shallow trench isolation structure according to claim 1, characterized in that: The first silicon oxide layer is formed by atomic layer deposition, and the reaction temperature is greater than or equal to 500° C. and less than or equal to 1000° C.
6. The method for preparing a semiconductor device with a shallow trench isolation structure according to claim 1, characterized in that: The reaction temperature of the in-situ steam generation process is greater than or equal to 900° C. and less than or equal to 1100° C.
7. The method for preparing a semiconductor device with a shallow trench isolation structure according to claim 1, characterized in that: The polysilicon layer is formed by atomic layer deposition or fluid chemical vapor deposition, and the first silicon oxide layer is formed by chemical vapor deposition or fluid chemical vapor deposition.
8. The method for preparing a semiconductor device with a shallow trench isolation structure according to claim 1, characterized in that: The insulating dielectric layer is one or both of silicon nitride and silicon oxynitride.
9. The method for preparing a semiconductor device with a shallow trench isolation structure according to claim 8, characterized in that: The thickness of the insulating dielectric layer is greater than or equal to 10 nm and less than or equal to 200 nm.
10. The method for preparing a semiconductor device with a shallow trench isolation structure according to claim 8, characterized in that: The insulating dielectric layer is formed on the surface of the buffer layer by atomic layer deposition at a temperature greater than or equal to 400° C. and less than or equal to 800° C.
11. The method for preparing a semiconductor device with a shallow trench isolation structure according to claim 8, characterized in that: The insulating dielectric layer is formed on the surface of the buffer layer by chemical vapor deposition or fluid chemical vapor deposition.
12. The method for preparing a semiconductor device with a shallow trench isolation structure according to claim 1, characterized in that: At least one trench is formed on the substrate, comprising: forming a silicon dioxide film on the substrate; forming a photomask layer on the silicon dioxide film; The photomask layer, the silicon dioxide film and the substrate are masked and etched to form at least one groove.
13. A semiconductor device with a shallow trench isolation structure, prepared by the method for preparing a semiconductor device with a shallow trench isolation structure according to any one of claims 1 to 12, characterized in that: include: a substrate having at least one groove disposed thereon; A buffer layer is provided on the groove wall of the groove; The insulating dielectric layer is disposed on the surface of the buffer layer and fills the groove.
14. The semiconductor device with shallow trench isolation structure according to claim 13, characterized in that: The buffer layer comprises: A first buffer thin layer, disposed on the groove wall of the groove; The second buffer thin layer is arranged between the first buffer thin layer and the insulating medium layer.
15. The semiconductor device with shallow trench isolation structure according to claim 14, characterized in that: The thickness of the first buffer thin layer is greater than or equal to 5 nm and less than or equal to 30 nm.
16. The semiconductor device with shallow trench isolation structure according to claim 14, characterized in that: The thickness of the second buffer thin layer is greater than or equal to 10 nm and less than or equal to 100 nm.
17. The semiconductor device with shallow trench isolation structure according to claim 14, characterized in that: The first buffer thin layer is silicon oxide.
18. The semiconductor device with shallow trench isolation structure according to claim 14, characterized in that: The second buffer thin layer is silicon oxide.
19. The semiconductor device with shallow trench isolation structure according to claim 13, characterized in that: The insulating dielectric layer is one or both of silicon nitride and silicon oxynitride.
20. The semiconductor device with shallow trench isolation structure according to claim 19, characterized in that: The thickness of the insulating dielectric layer is greater than or equal to 10 nm and less than or equal to 200 nm.
Citation Information
Patent Citations
Semiconductor device with shallow trench groove isolation structure
CN208767277U