Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package is disclosed, comprising a first semiconductor chip having a first through substrate via (TSV), a second semiconductor chip stacked on the first semiconductor chip, and a first adhesive layer disposed between the first semiconductor chip and the second semiconductor chip. The second semiconductor chip comprises a second through substrate via connected to the first through substrate via. Sides of the first adhesive layer are recessed from sides of the first semiconductor chip and the second semiconductor chip.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0114330 filed on September 21, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor package and a method for manufacturing the same. Background Art

[0004] Due to the progress in the electronics industry and consumer demands, electronic devices are increasingly miniaturized and lightened, and thus semiconductor packages used in electronic devices are required to have high performance and high capacity, as well as further miniaturization and weight reduction. For high performance and high capacity, as well as miniaturization and weight reduction, research and development of semiconductor chips including through substrate vias (TSVs) and semiconductor packages including such semiconductor chips stacked therein have been conducted. Summary of the invention

[0005] According to an exemplary embodiment of the present inventive concept, a semiconductor package includes a first semiconductor chip having a first through substrate via (TSV), a second semiconductor chip stacked on the first semiconductor chip, and a first adhesive layer (e.g., a non-conductive film) disposed between the first semiconductor chip and the second semiconductor chip. The second semiconductor chip includes a second through substrate via connected to the first through substrate via. Sides of the first adhesive layer are recessed from sides of the first semiconductor chip and the second semiconductor chip.

[0006] According to an exemplary embodiment of the present inventive concept, a semiconductor package includes: a base substrate having a wiring circuit; semiconductor chips stacked in a direction perpendicular to an upper surface of the base substrate; a first adhesive layer disposed between the base substrate and a lowermost semiconductor chip; and a second adhesive layer. A side of the first adhesive layer is recessed from a side of the lowermost semiconductor chip; each adhesive layer is disposed between corresponding two adjacent semiconductor chips of the semiconductor chip and has a side recessed from the side of the corresponding two adjacent semiconductor chips.

[0007] According to an exemplary embodiment conceived in the present invention, a semiconductor package includes: a first semiconductor chip and a second semiconductor chip, stacked in a vertical direction, and an adhesive layer, arranged between the first semiconductor chip and the second semiconductor chip, each of the first semiconductor chip and the second semiconductor chip having a semiconductor substrate with a lower surface and an upper surface opposite to each other, a semiconductor device layer arranged on the lower surface of the substrate, and a silicon through hole penetrating the semiconductor substrate and the semiconductor device layer, the substrate through hole of the first semiconductor chip is connected to the substrate through hole of the second semiconductor chip, and the side of the adhesive layer is a concave surface recessed from the side of the first semiconductor chip and the second semiconductor chip.

[0008] According to an exemplary embodiment of the present invention, a method for manufacturing a semiconductor package is provided as follows. Each semiconductor chip and each first uncured adhesive layer are alternately stacked with each other. The first uncured adhesive layer is cured at a first temperature under a first pressure so that the first uncured adhesive layer is cured to form a first cured adhesive layer, and the side of each first cured adhesive layer is recessed from the side of the corresponding two adjacent semiconductor chips. The first pressure is formed by using a pressurized fluid. The first temperature is higher than the curing temperature of the first uncured adhesive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a cross-sectional view showing a semiconductor package according to example embodiments;

[0011] Figure 2 It shows Figure 1 an enlarged cross-sectional view of area "A";

[0012] Figure 3 is an enlarged cross-sectional view of a non-conductive film employed in a semiconductor package according to example embodiments;

[0013] Figure 4 is a cross-sectional view showing a semiconductor package according to example embodiments;

[0014] Figure 5 is a cross-sectional view showing a semiconductor package according to example embodiments;

[0015] Figure 6 yes Figure 5 an enlarged cross-sectional view of region "B";

[0016] Figure 7 is a process flow chart illustrating a method of manufacturing a semiconductor device according to an example embodiment;

[0017] Figure 8 is a graph of curing temperature and pressure versus time illustrating a hydrostatic bonding process employed in a method of manufacturing a semiconductor package according to an example embodiment;

[0018] Figures 9 to 12 is a cross-sectional view for describing a method of manufacturing a semiconductor package according to example embodiments; and

[0019] Fig.13 is a block diagram illustrating a configuration of a semiconductor package according to example embodiments. DETAILED DESCRIPTION

[0020] Hereinafter, example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0021] Figure 1 is a cross-sectional view showing a semiconductor package according to example embodiments;

[0022] like Figure 1 As shown, the semiconductor package 200 may include a first semiconductor chip 100A, a second semiconductor chip 100B, a third semiconductor chip 100C, and a fourth semiconductor chip 100D. The first to fourth semiconductor chips 100A, 100B, 100C, and 100D may be electrically connected to semiconductor chips adjacent to each other through second to fourth connection bumps 170B, 170C, and 170D.

[0023] In addition, the first to fourth semiconductor chips 100A, 100B, 100C, and 100D may be bonded to each other through the non-conductive film (or adhesive layer) 150. The side surface CS of each non-conductive film 150 may be recessed from the side surfaces of corresponding two adjacent semiconductor chips of the first to fourth semiconductor chips 100A, 100B, 100C, and 100D. Figure 1 As shown in the cross-sectional view shown, the side CS of the non-conductive film 150 may have a concave surface. In an exemplary embodiment, the side CS of the non-conductive film 150 may have different recess depths. Such a shape may enhance the bonding strength with the molding member, or may prevent defects from being generated in subsequent processes after the process of stacking semiconductor chips, which will be described more fully below.

[0024] The first to fourth semiconductor chips 100A, 100B, 100C, and 100D may be memory chips or logic chips. In an example embodiment, the first to fourth semiconductor chips 100A, 100B, 100C, and 100D may all be memory chips of the same kind. In another example embodiment, some of the first to fourth semiconductor chips 100A, 100B, 100C, and 100D may be memory chips, while the others are logic chips. In a specific embodiment, the first semiconductor chip 100A may be a logic chip, and the second to fourth semiconductor chips 100B, 100C, and 100D may be memory chips.

[0025] For example, the memory chip may be a volatile memory chip such as a dynamic random access memory (DRAM) chip and a static random access memory (SRAM) chip, or may be a nonvolatile memory chip such as a phase change random access memory (PRAM) chip, a magnetoresistive random access memory (MRAM) chip, a ferroelectric random access memory (FeRAM) chip, and a resistive random access memory (RRAM) chip. In some example embodiments, the first to fourth semiconductor chips 100A, 100B, 100C, and 100D may be high bandwidth memory (HBM) DRAM.

[0026] The logic chip may be, for example, a microprocessor, an analog device, or a digital signal processor.

[0027] Although the semiconductor package 200 in which the first to fourth semiconductor chips 100A, 100B, 100C, and 100D are stacked is shown in the present exemplary embodiment, the number of semiconductor chips that can be stacked in the semiconductor package 200 is not limited thereto. For example, two, three, or even more semiconductor chips (e.g., eight chips) may be stacked in the semiconductor package 200.

[0028] The first to fourth semiconductor chips 100A, 100B, 100C, and 100D may be the same chip, and as shown in FIG. Figure 1 As shown, they may have the same surface area. In some example embodiments, the first to fourth semiconductor chips 100A, 100B, 100C, and 100D may have different surface areas. Not all sides of the semiconductor chips may be aligned to be substantially coplanar, and, for example, at least a portion of the sides of the semiconductor chips may have a stepped alignment.

[0029] In this case, the side surface of the non-conductive film may be recessed from at least the side surface of the semiconductor chip near the center of the stack.

[0030] Each of the first to fourth semiconductor chips 100A, 100B, 100C, and 100D may include a semiconductor substrate 110, a semiconductor device layer 120, a through substrate via (TSV) 130, a lower connection pad 142, an upper connection pad 144, and first to fourth connection bumps 170A, 170B, 170C, and 170D. However, as shown in the present exemplary embodiment, the fourth semiconductor chip 100D disposed on top may not include the through substrate via 130.

[0031] The semiconductor substrate 110 of each semiconductor chip 100A to 100D may include an upper surface and a lower surface opposite to the upper surface. The semiconductor device layer 120 may be disposed on the lower surface of the semiconductor substrate 110, and the wiring structure 140 may be disposed in the semiconductor device layer 120. The substrate through hole 130 may penetrate the semiconductor substrate 110 to connect the upper surface and the lower surface of the semiconductor substrate 110, thereby connecting to the wiring structure 140. The lower connection pad 142 may be formed on the semiconductor device layer 120, and may be electrically connected to the substrate through hole 130 through the wiring structure 140. In some examples, the substrate through hole 130 may extend not only through the semiconductor substrate 110, but also through the entire semiconductor chip (100A, 100B, 100C or 100D). The substrate through hole 130 may be a through silicon via.

[0032] The semiconductor substrate 110 of each semiconductor chip 100A to 100D can be formed by a crystalline semiconductor material. For example, the semiconductor substrate 110 can be formed by a semiconductor material such as silicon and germanium, or a compound semiconductor material such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) and indium phosphide (InP). In addition, the semiconductor substrate 110 can have a silicon on insulator (SOI) structure. For example, the semiconductor substrate 110 may include a buried oxide (BOX) layer. The semiconductor substrate 110 may include a conductive region, such as a well doped with impurities or a structure doped with impurities. In addition, the semiconductor substrate 110 may include various device isolation structures, such as a shallow trench isolation (STI) structure.

[0033] The semiconductor device layer 120 may be formed to include a wiring structure 140 to connect each of the individual devices to other wirings formed in the semiconductor substrate 110. The wiring structure 140 may include a metal wiring layer and a via plug. For example, the wiring structure 140 may be a multilayer structure in which two or more metal wiring layers or two or more via plugs are alternately stacked.

[0034] The through substrate via 130 may extend from the upper surface of the semiconductor substrate 110 toward the lower surface thereof, and may further extend into the semiconductor device layer 120. For example, the through substrate via 130 may partially penetrate the semiconductor device layer 120 to be connected to the wiring structure 140. A portion of the through substrate via 130 may at least have a pillar shape. As described above, the semiconductor chip (e.g., the fourth semiconductor chip 100D) disposed at the uppermost layer may not include the through substrate via 130.

[0035] The lower connection pad 142 may be disposed on the semiconductor device layer 120 and may be electrically connected to the wiring structure 140 within the semiconductor device layer 120. The lower connection pad 142 may be electrically connected to the substrate through-hole 130 through the wiring structure 140. For example, the lower connection pad 142 may include at least one of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au).

[0036] In addition, a lower passivation layer (not shown) may be formed on the semiconductor device layer 120 to protect the wiring structure 140 within the semiconductor device layer 120 and other structures disposed thereunder from external stress and humidity. The lower connection pad 142 may be partially exposed from the lower passivation layer to be connected to one of the corresponding connection bumps of the first to fourth connection bumps 170A to 170D.

[0037] The upper connection pads 144 may be formed on the upper surface of the semiconductor substrate 110 to be electrically connected to the through substrate vias 130. The upper connection pads 144 may include the same material as the lower connection pads 142. Also, an upper passivation layer (not shown) may be formed on the upper surface of the semiconductor substrate 110 to surround a portion of the through substrate vias 130.

[0038] Each of the first to fourth connection bumps 170A, 170B, 170C, and 170D may be disposed on the corresponding lower connection pads 142 of the first to fourth semiconductor chips 100A, 100B, 100C, and 100D, respectively. For example, the first connection bump 170A may be formed of a pillar structure, a ball structure, or a solder layer.

[0039] In the present example embodiment, the first connection bumps 170A may be disposed on the lower connection pads 142 of the first semiconductor chip 100A so that the semiconductor package 200 is electrically connected to an external wiring circuit (eg, Figure 5Through the first connection bumps 170A, at least one of a control signal, a power signal, and a ground signal for the operation of the first to fourth semiconductor chips 100A, 100B, 100C, and 100D may be received from an external source; data signals to be stored in the first to fourth semiconductor chips 100A, 100B, 100C, and 100D may be received from an external source; alternatively, data stored in the first to fourth semiconductor chips 100A, 100B, 100C, and 100D may be transmitted to the outside.

[0040] The second semiconductor chip 100B may be mounted on an upper surface of the first semiconductor chip 100 A. The second semiconductor chip 100B may be electrically connected to the first semiconductor chip 100A through second connection bumps 170B disposed between the first semiconductor chip 100A and the second semiconductor chip 100B.

[0041] Between the upper surface of the first semiconductor chip 100A and the lower surface of the second semiconductor chip 100B, a first non-conductive film (or a first adhesive layer) 150 may be provided to bond the second semiconductor chip 100B to the first semiconductor chip 100A. In a similar manner, the third semiconductor chip 100C may be mounted on the upper surface of the second semiconductor chip 100B, and the fourth semiconductor chip 100D may be mounted on the upper surface of the third semiconductor chip 100C. Between the second semiconductor chip 100B and the third semiconductor chip 100C, a third connection bump 170C and a second non-conductive film (or a second adhesive layer) 150 surrounding the side of the third connection bump 170C may be provided. Between the third semiconductor chip 100C and the fourth semiconductor chip 100D, a fourth connection bump 170D and a third non-conductive film 150 may be provided, and the third non-conductive film 150 surrounds the side of the fourth connection bump 170D.

[0042] The molding member 180 may surround the side surfaces of the first to fourth semiconductor chips 100A, 100B, 100C, and 100D and the side surfaces of the non-conductive film 150. In some example embodiments, the molding member 180 may cover the upper surface of the fourth semiconductor chip 100D. Alternatively, in other example embodiments, the molding member 180 may be formed to expose the upper surface of the fourth semiconductor chip 100D to the outside (please refer to Figure 4 ). The molding member 180 may include epoxy molding compound (EMC) or the like.

[0043] As described above, for miniaturization and light weight of the semiconductor package, a stacked structure of the first to fourth semiconductor chips 100A, 100B, 100C, and 100D including the through substrate vias 130 is adopted. In the process of stacking the semiconductor chips, in order to achieve uniform, electrically reliable, and structurally reliable bonding between the first to fourth semiconductor chips 100A, 100B, 100C, and 100D, the non-conductive film 150 may be used as an interlayer bonding material combined with the second to fourth connection bumps 170B, 170C, and 170D.

[0044] However, after bonding the semiconductor chip in the semiconductor package manufacturing process, if the non-conductive film overflows around the semiconductor chip, subsequent processes may not be properly performed due to the overflow of the non-conductive film. For example, the portion protruding from between the semiconductor packages 200 may cause an overhang or even a defective bonding with the molding member 180. In severe cases, such overhangs may prevent the molding member 180 from surrounding the corresponding side of the semiconductor substrate 110 by connecting to each other.

[0045] Therefore, in order to reduce the portion of the non-conductive film 150 that may overflow, the semiconductor package manufacturing process may be performed by reducing the thickness of the non-conductive film or by increasing the viscosity of the non-conductive film. However, if the thickness of the non-conductive film 150 is reduced or the viscosity of the non-conductive film 150 is increased only relative to the height of the connection bump, the non-conductive film may cause an insufficient filling problem. Therefore, semiconductor chips adjacent to each other may not be bonded to have a uniform thickness, or gaps between semiconductor chips may be generated in the non-conductive film 150.

[0046] In order to solve the above-mentioned problem, as described above, the semiconductor package 200 according to the inventive concept may include a non-conductive film 150 having a side surface recessed from the side surfaces of the adjacent semiconductor chips 100A, 100B, 100C, and 100D. More specifically, the side surface of the non-conductive film 150 may have a concave surface. The non-conductive film 150 may be formed by using a pressurized fluid (e.g., such as air or N 2 The recessed or concave side of the non-conductive film 150 is obtained by solidifying the non-conductive film 150 disposed between the stacked first to fourth semiconductor chips 100A, 100B, 100C and 100D through a hydrostatic bonding process using a gas (eg, a gas).

[0047] As a result, before or during the curing process, the non-conductive film 150 can be prevented from excessively overflowing to form an overhang and simultaneously preventing insufficient filling problems. Therefore, the bonding strength between the molding member 180 and the non-conductive film 150 can be increased, thereby improving the reliability of the semiconductor package.

[0048] The non-conductive film 150 may be used to bond the stacked semiconductor chips 100A, 100B, 100C, and 100D. The non-conductive film 150 may include an adhesive resin. The adhesive resin may be a thermosetting resin. The adhesive resin may include, for example, at least one of a bisphenol epoxy resin, a novolac epoxy resin, a phenolic resin, a urea resin, a melamine resin, an unsaturated polyester resin, and a resorcinol resin.

[0049] The non-conductive film 150 employed in the present exemplary embodiment may have a relatively low viscosity so that a concave side of the non-conductive film 150 may be obtained. For example, the non-conductive film 150 in an uncured state may have a viscosity equal to or less than about 1,000 Pa·s, where the viscosity is the minimum viscosity of the non-conductive film 150 and is a measurement taken at about 100° C. The error range of the measured temperature at 100° C. may be about ±5° C.

[0050] In some example embodiments, the non-conductive film 150 may include flux and / or ceramic filler. The flux may be used for soldering in a semiconductor package manufacturing process to form an electrical connection between semiconductor chips. The flux may increase the spreadability and / or wettability of the solder, and the flux may be pre-coated on the area to be coated with the solder, or may be included in the non-conductive film 150. The flux may be classified as resin-based, organic, and inorganic, wherein fluxes commonly used in electronic devices may include resin-based fluxes. For example, a resin-based flux may include rosin, modified rosin, and synthetic resins. Depending on the particle size and its percentage, a ceramic filler may be used to adjust the viscosity of the non-conductive film.

[0051] Figure 2 is an enlarged cross-sectional view showing Figure 1 The area "A" is shown in FIG.

[0052] Figure 2A non-conductive film 150 located between the first semiconductor chip 100A and the second semiconductor chip 100B is shown. As described above, the side CS of the non-conductive film 150 may have a side recessed from the semiconductor substrate 110 of the first semiconductor chip 100A and the semiconductor device layer 120 of the second semiconductor chip 100B. The recessed side CS may have a concave surface. The molding member 180 may have an area protruding into the recessed area between the first semiconductor chip 100A and the second semiconductor chip 100B to contact the side CS of the non-conductive film 150. The recessed side CS may have a shape recessed by a predetermined depth W from the side of the first semiconductor chip 100A and the second semiconductor chip 100B. For example, the bottom of the recessed side CS may be located at a predetermined depth W from the area between the first semiconductor chip 100A and the second semiconductor chip 100B. The predetermined depth W of the molding member 180 may be relatively large in the area between the first semiconductor chip 100A and the second semiconductor chip 100B.

[0053] Since the final height H between the first semiconductor chip 100A and the second semiconductor chip 100B becomes slightly smaller than the initial thickness of the non-conductive film 150 through the compression and curing process after the semiconductor package manufacturing process is completed, the non-conductive film 150 may overflow into the adjacent areas (e.g., the side surfaces) of the semiconductor chips 100A and 100B during the semiconductor package manufacturing process. However, in the present exemplary embodiment, the non-conductive film 150 may be cured under the pressure applied by the pressurized fluid during the hydrostatic bonding process, thereby obtaining the side surfaces CS recessed from the side surfaces of the first conductor chip 100A and the second semiconductor chip 100B. Throughout this process, the non-conductive film 150 may be compressed using the pressure applied by the pressurized fluid, and the internal voids in the non-conductive film 150 may be removed. Therefore, the non-conductive film 150 may be more firmly bonded to the connection bumps 170B and / or the first semiconductor chip 100A and the second semiconductor chip 100B.

[0054] Factors controlling the concave side surface CS of the non-conductive film 150 include the viscosity of the non-conductive film 150 in an uncured state and the processing conditions of the hydrostatic bonding process (eg, temperature, pressure, curing speed, etc.) Such processing conditions will be described more fully below.

[0055] The recessed non-conductive film 150 between the first semiconductor chip 100A and the second semiconductor chip 100B may be formed without an overhang that may cause a problem in a molding process, thereby preventing defects due to the overhang of the non-conductive film 150 and increasing the filling rate of the non-conductive film 150. For example, the filling rate may be increased by removing voids in the non-conductive film 150. Therefore, the recessed non-conductive film 150 may increase the reliability of the semiconductor package 200 by enhancing the bonding strength between the molding member 180 and the non-conductive film 150.

[0056] The concave side surface CS of the non-conductive film 150 may have different shapes according to the viscosity of the non-conductive film 150 in an uncured state and / or the processing conditions of the hydrostatic bonding. Figure 3 is an enlarged cross-sectional view illustrating a non-conductive film employed in a semiconductor package according to another example embodiment.

[0057] like Figure 3 As shown, the recessed side surface CS′ of the non-conductive film 150 may have a shape that is more recessed from the side surfaces of the first semiconductor chip 100A and the second semiconductor chip 100B than in the previous example embodiment. The recessed side surface CS′ may also include a region C formed to cover portions of the side surfaces of the first semiconductor chip 100A and the second semiconductor chip 100B. The recessed side surface CS′ may be formed when a portion of the non-conductive film 150 in an uncured state that covers portions of the side surfaces of the adjacent semiconductor chips 100A and 100B in a compression process for pre-bonding is recessed during a hydrostatic bonding process.

[0058] As described above, the nonconductive film 150 according to the present example embodiment is not limited to having its entire surface area recessed from the sides of the semiconductor chips 100A and 100B, and for example, the nonconductive film 150 may further include a portion protruding from the sides of the adjacent semiconductor chips or remaining on top thereof.

[0059] The inventive concepts according to example embodiments may be applied to semiconductor packages in various other forms.

[0060] Figure 4 is a cross-sectional view illustrating a semiconductor package according to example embodiments.

[0061] like Figure 4 As shown, in addition to the heat dissipation plate on the uppermost semiconductor chip of the semiconductor chips 100A to 100D, the semiconductor package 200A according to the present example embodiment may have Figure 1 The structure of the exemplary embodiment shown is similar to the structure of the exemplary embodiment shown. Therefore, unless otherwise stated, Figure 1 The description of the example embodiments shown in FIG. 2 can be combined with the description of this specific example embodiment.

[0062] Similar to the aforementioned example embodiments, the semiconductor package 200A according to the present example embodiment may include first to fourth semiconductor chips 100A, 100B, 100C and 100D stacked vertically, and may also include a thermally conductive material layer 210 and a heat sink 220 sequentially disposed on the upper surface of the fourth semiconductor chip 100D.

[0063] The thermally conductive material layer 210 may be disposed between the heat sink 220 and the fourth semiconductor chip 100D, and may cover the upper surface of the fourth semiconductor chip 100D. The thermally conductive material layer 210 may allow the heat generated by the first to fourth semiconductor chips 100A, 100B, 100C and 100D to be released more easily to the heat sink 220. The thermally conductive material layer 210 may be formed by a thermal interface material (TIM). For example, the thermally conductive material layer 210 may be formed by an insulating material or a material containing an insulating material having an electrical insulating property. The thermally conductive material layer 210 may include, for example, epoxy resin. Specific examples of the thermally conductive material 2 layer 10 may include mineral oil, grease, gap filler putty, phase change gel, phase change material pad or particle filled epoxy resin.

[0064] The heat sink 220 may be disposed on the thermally conductive material layer 210. The heat sink 220 may be, for example, a heat sink, a heat radiator, a heat pipe or a liquid-cooled cold plate.

[0065] The thermally conductive material layer 210 completely covering the upper surface of the fourth semiconductor chip 100D can increase the contact area between the fourth semiconductor chip 100D and the thermally conductive material layer 210 , so that the heat generated by the first to fourth semiconductor chips 100A, 100B, 100C and 100D can be more efficiently transferred to the heat sink 220 .

[0066] Figure 5 is a cross-sectional view illustrating a semiconductor package according to example embodiments.

[0067] like Figure 5 As shown, in addition to further including a base substrate, the semiconductor package 200B may include Figure 1 The structure of the exemplary embodiment shown is similar to the structure of the exemplary embodiment shown. Therefore, unless otherwise stated, Figure 1 The description of the example embodiments shown in FIG. 2 can be combined with the description of this specific example embodiment.

[0068] The semiconductor package 200B according to the present example embodiment may include a base substrate 300 and first to fourth semiconductor chips 100A, 100B, 100C and 100D, and the first to fourth semiconductor chips 100A, 100B, 100C and 100D are mounted on the base substrate 300 and stacked sequentially in a direction perpendicular to the upper surface of the base substrate 300.

[0069] The base substrate 300 may be, for example, a printed circuit board, a ceramic board, or an interposer. When the base substrate 300 is a printed circuit board, the base substrate 300 may include a substrate body 310, a lower surface pad 320, an upper surface pad 330, and a solder resist layer (not shown) formed on the lower surface and upper surface of the substrate body 310. Inside the substrate body 310, an internal wiring (not shown) may be formed to electrically connect the lower surface pad 320 and the upper surface pad 330. The lower surface pad 320 and the upper surface pad 330 may be a part of the circuit wiring exposed by the solder resist layer formed on the lower surface and upper surface of the substrate body 310, respectively, and the circuit wiring has been patterned on the lower surface and upper surface of the substrate body 310 covered with Cu foil.

[0070] In some example embodiments, the base substrate 300 may be an interposer. In this case, the base substrate 300 may include a substrate body 310 formed of a semiconductor material, and may include a lower surface pad 320 and an upper surface pad 330 formed on the lower surface and upper surface of the substrate body 310, respectively. The substrate body 310 may be formed, for example, by a silicon wafer. In addition, internal wiring (not shown) may be formed on the lower surface or upper surface of the substrate body 310, or formed inside the substrate body 310. In addition, inside the substrate body 310, a substrate through hole (not shown) may be formed to electrically connect the lower surface pad 320 and the upper surface pad 330.

[0071] The external connection terminals 340 may be bonded to the lower surface of the base substrate 300. For example, the external connection terminals 340 may be bonded to the lower surface pads 320. For example, the external connection terminals 340 may be solder balls or bumps. The external connection terminals 340 may be electrically connected between the semiconductor package 200 and an external device.

[0072] In the present example embodiment, the first to fourth semiconductor chips 100A, 100B, 100C, and 100D may all have the same surface area, and the surface area of ​​the base substrate 300 may be greater than that of each of the first to fourth semiconductor chips 100A, 100B, 100C, and 100D.

[0073] On the base substrate 300, a molding member 180 may be formed to partially or completely encapsulate the first to fourth semiconductor chips 100A, 100B, 100C, and 100D. The molding member 180 may include, for example, an epoxy resin mold compound. Figure 5 As shown, the molding member 180 may be disposed on the base substrate 300 and may have a coplanar surface substantially flat with the side surface of the base substrate 300. Such coplanar side surfaces may be obtained by the same cutting process (please refer to Fig.12 process in the process).

[0074] In a manner similar to the aforementioned example embodiment, the first to fourth semiconductor chips 100A, 100B, 100C, and 100D may be bonded to each other through the second non-conductive film (or second adhesive layer) 150. Each side surface CS2 of the second non-conductive film 150 may be recessed from the side surfaces of two corresponding adjacent semiconductor chips of the semiconductor chips 100A, 100B, 100C, and 100D. The side surface CS2 of the second non-conductive film 150 may have a concave surface.

[0075] The first non-conductive film (or first adhesive layer) 160 may be disposed between the base substrate 300 and the first semiconductor chip 100. In some example embodiments, the first non-conductive film 160 may be formed of the same or similar material as the second non-conductive film 150. In some example embodiments, the first non-conductive film 160 may be formed of a material different from the second non-conductive film 150, for example, a bottom filling material layer. The first non-conductive film 160 may be disposed between the base substrate 300 and the first semiconductor chip 100A to surround the side of the first connection bump 170A. The first non-conductive film 160 may be formed of, for example, epoxy resin. For example, the thickness of the first non-conductive film 160 may be less than the thickness of each non-conductive film 150.

[0076] In one example embodiment, the side CS1 of the first nonconductive film 160 has a first recessed depth, and each side CS2 of the second nonconductive film 150 has a second recessed depth. The first recessed depth may be different from the second recessed depth.

[0077] Figure 6 It is shown Figure 5 An enlarged cross-sectional view of area "B" of FIG. Figure 6 A first non-conductive film 160 is shown between the base substrate 300 and the first semiconductor chip 100A.

[0078] Unlike the second non-conductive film 150 disposed between semiconductor chips of the same size, the first non-conductive film 160 is more likely to overflow due to increased surface tension between the base substrate 300 and the first non-conductive film 160 in an uncured state due to the base substrate 300 having a relatively large surface area bonded below the first non-conductive film 160. Since the base substrate 300 may be similarly used as a carrier substrate during the semiconductor package manufacturing process, the first non-conductive film 160 in an uncured state may flow out onto the upper surface of the base substrate 300, thereby forming an overhang OH (a portion of the non-conductive film extending onto the base substrate 300, such as Figure 6). The overhang OH may cover the upper surface of the base substrate 300, thereby reducing the area of ​​the base substrate 300 on which the molding member 180 is subsequently formed. The reduction in the area of ​​the upper surface of the base substrate 300 may cause a defective connection between the molding member 180 and the base substrate 300, so that the molding member 180 cannot be used as a proper passivation structure. For example, the molding member 180 may be lifted or moisture may penetrate the molding member 180.

[0079] In order to solve the above problem, in the present exemplary embodiment, the side surface of the first non-conductive film 160 may be recessed from between the base substrate 300 and the first semiconductor chip 100B by a hydrostatic bonding process for curing the non-conductive films 160 and 150 in an uncured state in a similar manner to the second non-conductive film 150. By forming the recessed side surface CS1 having a concave surface, an undesirable overhanging portion OH in curing of the non-conductive films 160 and 150 in an uncured state may be avoided.

[0080] As described above, in the present exemplary embodiment, the first non-conductive film 160 and the second non-conductive film 150 in an uncured state can be cured under pressure applied by a pressurized fluid in a hydrostatic bonding process, and thus can have a side surface that is recessed from the side surface of an adjacent semiconductor chip. Through this process, internal voids existing inside the first non-conductive film 160 and the second non-conductive film 150 can be eliminated, and the first non-conductive film 160 and the second non-conductive film 150 can be more firmly bonded to the connection bump. Therefore, a firm bond can be achieved by preventing the generation of defects caused by overflow of the non-conductive films 160 and 150 in an uncured state and by increasing the filling rate of the non-conductive film 150.

[0081] The concave side surfaces CS1 and CS2 of the first non-conductive film 160 and the second non-conductive film 150 can be controlled by controlling the processing conditions (e.g., temperature, pressure, curing speed, etc.) of the hydrostatic bonding process, and can also be controlled by controlling the properties (e.g., viscosity) of the first non-conductive film 160 and the second non-conductive film 150 in an uncured state. For example, the first non-conductive film 160 and the second non-conductive film 150 in an uncured state can have a viscosity of about 1,000 Pa·s or less.

[0082] Figure 7 is a process flow chart illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0083] like Figure 7 As shown, the method of manufacturing a semiconductor package according to the present example embodiment may start by preparing a plurality of semiconductor chips having connection bumps and through-substrate vias ( S71 ).

[0084] In addition to the connection bumps and substrate through-holes, each of the plurality of semiconductor chips may include a semiconductor substrate, a semiconductor device layer, a lower connection pad, and an upper connection pad. The description of each of these components may be similar to Figure 1 Description combination of the semiconductor chip shown in .

[0085] The plurality of semiconductor chips may be memory chips or logic chips, and in some example embodiments, may include memory chips of the same size.

[0086] Subsequently, a plurality of semiconductor chips may be stacked so that an uncured non-conductive film may be disposed between the plurality of semiconductor chips (S73). For example, the uncured non-conductive film corresponds to the above-described non-conductive film in an uncured state and may be an example of an uncured adhesive layer.

[0087] The uncured non-conductive film may include an uncured binder resin. For example, the binder resin may include at least one of the above-mentioned thermosetting resins. The uncured non-conductive film used in this example embodiment may have a sufficiently low viscosity that allows the uncured non-conductive film to obtain a desired shape (e.g., a side with a concave surface) during the hydrostatic bonding process. For example, the uncured non-conductive film may have a viscosity of about 1,000 Pa·s or less.

[0088] In some example embodiments, before stacking a plurality of semiconductor chips, an uncured non-conductive film may be provided on the surface of each semiconductor chip, on which a connection bump is formed. In this case, the uncured non-conductive film may be in a partially cured state (i.e., in the B stage). The uncured non-conductive film used in these example embodiments may not be limited to the film type. For example, the uncured non-conductive film may be applied and used in a paste state.

[0089] Next, the plurality of stacked semiconductor chips may be pre-bonded by thermal compression of the plurality of semiconductor chips ( S75 ).

[0090] The pre-bonding process may be performed so that the plurality of semiconductor chips are kept stacked by a subsequent hydrostatic bonding process. In an environment where the non-conductive film is uncured, the plurality of semiconductor chips may be pre-bonded by utilizing the adhesive properties of the non-conductive film.

[0091] In the pre-compression process, appropriate temperature and / or pressure may be applied to prevent the side of the uncured non-conductive film from protruding. By preventing the uncured non-conductive film from overflowing onto the side of the semiconductor chip, a recessing process of the non-conductive film having a recessed side may be more conveniently performed in a hydrostatic bonding process. In some example embodiments, even when part of the non-conductive film has overflowed onto the side of the semiconductor chip, the non-conductive film may still obtain a side of a desired shape, depending on the viscosity of the uncured non-conductive film and / or the processing conditions of the hydrostatic bonding process.

[0092] Subsequently, the non-conductive film may be cured by using a pressurized fluid using a hydrostatic bonding process (S77).

[0093] In this process, the hydrostatic pressure of the pressurized fluid and the curing temperature of the uncured non-conductive film may be applied to the stacked semiconductor chips, thereby curing the non-conductive film. More specifically, as Figure 8 As shown, in the exemplary hydrostatic bonding process, once the uncured non-conductive film is heated to its curing temperature, it can be immediately subjected to the hydrostatic pressure of the pressurized fluid, and once the uncured non-conductive film is sufficiently cured to form Figure 1 , 4 and 5's non-conductive film, the temperature can be lowered below the curing temperature and the pressure can be released.

[0094] In this process, since the hydrostatic pressure of the pressurized fluid is applied even to the side of the non-conductive film, the side of the uncured non-conductive film can be Figure 8 The side surfaces of the uncured non-conductive film may be recessed from the side surfaces of the plurality of semiconductor chips during the curing process shown. The present invention is not limited thereto. For example, by applying a hydrostatic pressure before applying a temperature higher than the curing temperature to the semiconductor chips, the side surfaces of the uncured non-conductive film may be recessed from the side surfaces of the plurality of semiconductor chips before the curing process. To facilitate such a recessing process, the process may be performed at a temperature and / or pressure slightly higher than that of the hydrostatic bonding process. In some example embodiments, the hydrostatic bonding process may be performed at a temperature of about 200° C. or higher and about 10 atm or higher (relative to the curing temperature). Figure 8 For example, the hydrostatic bonding process may be performed at about 250° C. and about 15 atm.

[0095] Figures 9 to 12 is a cross-sectional view showing a method of manufacturing a semiconductor package according to an example embodiment. Figure 5 The method of manufacturing a semiconductor package 200B shown in FIG. 2 will be described with reference to the method of manufacturing a semiconductor package 200B. Figure 7 Process flow diagram description Figures 9 to 12 .

[0096] Fig. 9 Shown by executing Figure 7 Steps S71 and S73 are provided on the base substrate 300 to form three stacked semiconductor chips. Each stacked semiconductor chip has a structure in which first to fourth semiconductor chips 100A, 100B, 100C and 100D are sequentially stacked while an uncured first non-conductive film 160" and a second non-conductive film 150" are provided therebetween.

[0097] In this example embodiment, the first to fourth semiconductor chips 100A, 100B, 100C, and 100D singulated from the wafer may be stacked on the base substrate 300. The base substrate 300 may be used as a carrier substrate in subsequent processes. The first to fourth semiconductor chips 100A, 100B, 100C, and 100D may be semiconductor chips of the same type (e.g., memory chips). Alternatively, at least one of the first to fourth semiconductor chips 100A, 100B, 100C, and 100D may be a semiconductor chip different from the other semiconductor chips (different memory chips or logic chips).

[0098] For example, by using a semiconductor chip transfer device (not shown), and then by using a carrier substrate, the first semiconductor chip 100A singulated from the wafer can be aligned at a uniform distance (D1) on the carrier substrate (not shown), and the first semiconductor chip 100A can be transferred to the base substrate 300 to have the connection bumps 170A located on the upper surface pads 330 of the base substrate 300. As described above, before the first semiconductor chip 100A is stacked on the base substrate 300, an uncured first non-conductive film 160" can be provided on the lower surface of the first semiconductor chip 100A and / or the upper surface of the base substrate 300. Similarly, the second to fourth semiconductor chips 100, 100C and 100D can be sequentially transferred to provide Fig. 9 The stacking structure shown.

[0099] In other example embodiments, the first to fourth semiconductor chips 100A, 100B, 100C, and 100D may be transferred at a wafer level. Figure 1 In the case of the semiconductor package manufacturing process shown, the first to fourth semiconductor chips 100A, 100B, 100C, and 100D may be singulated to a desired distance after being transferred onto a carrier substrate at a wafer level.

[0100] More specifically, the distance D1 may be a distance that allows the molded member ( Figure 2The distance D1 is a distance between the sides of the first to fourth semiconductor chips 100A, 100B, 100C and 100D and the sides of the first non-conductive film 160 and the second non-conductive film 150. Since the uncured non-conductive films 160" and 150" can be controlled to be recessed rather than protruding in the subsequent process, the distance D1 can be determined to be a suitable size without considering the overhanging portion of the cured non-conductive film (especially, the first non-conductive film 160).

[0101] like Fig.10 As shown, by executing Figure 7 In step S75 , the first to fourth semiconductor chips 100A, 100B, 100C, and 100D in each of the stacked semiconductor chips may be pre-bonded by thermal compression of the stacked semiconductor chips.

[0102] After completing step S75, the base substrate 300 and the first semiconductor chip 100A and the stacked semiconductor chips 100A, 100B, 100C and 100D can be in a temporary bonding state by maintaining the adhesive properties of the uncured first and uncured second non-conductive films 160′ and 150′. For example, step S75 can be performed under the condition that the first uncured non-conductive film 160′ and the second uncured non-conductive film 150′ remain uncured. In addition, appropriate temperature and / or pressure can be applied during the pre-compression process to prevent the side of each of the first uncured non-conductive film 160′ and the second uncured non-conductive film 150′ from protruding from between two adjacent semiconductor chips in the semiconductor chips 100A to 100D. In this case, the first uncured non-conductive film 160′ and the second uncured non-conductive film 150′ can be prevented from overflowing onto the side of the adjacent semiconductor chip, thereby allowing Fig.11 The non-conductive films 150 and 160 are obtained Figure 7 The concave side in step S77.

[0103] like Fig.11 As shown, Fig.10 The stacked semiconductor chips obtained therein may be disposed in a hydrostatic chamber 500 to cure the first uncured non-conductive film 160 ′ and the second uncured non-conductive film 150 ′ by using a pressurized fluid in step S77 .

[0104] The hydrostatic chamber 500 used in the process may include a sealed internal space having an inlet 510 and an outlet 520 for a pressurized fluid. For example, stacked semiconductor chips may be disposed in the internal space and heated to a curing temperature of the first uncured non-conductive film 160′ and the second uncured non-conductive film 150′, and pressurized fluid may be injected therein to apply hydrostatic pressure to each of the stacked semiconductor chips.

[0105] In the hydrostatic bonding process of S77, a predetermined heat and pressure may be applied to the first uncured non-conductive film 160′ and the second uncured non-conductive film 150′ and the connecting bumps 170A, 170B, 170C, and 170D disposed between the base substrate 300 and the first to fourth semiconductor chips 100A, 100B, 100C, and 100D. The first uncured non-conductive film 160′ and the second uncured non-conductive film 150′ may be cured, thereby enhancing the bonding between the semiconductor chips adjacent to the base substrate. The connecting bumps 170A, 170B, 170C, and 170D may include an intermetallic compound to reduce the contact resistance with the upper connecting pad 144 located therebelow.

[0106] Since the hydrostatic pressure of the pressurized fluid is also applied to the sides of the first non-conductive film 160 and the second non-conductive film 150, the first non-conductive film 160 and the second non-conductive film 150 may be recessed from the sides of the adjacent semiconductor chip before or during the curing process. In order to facilitate such a recessing process, such a hydrostatic bonding process may be performed at a higher temperature and / or pressure than a typical hydrostatic bonding process. In some example embodiments, the hydrostatic bonding process of step S77 may be performed at 200°C or higher and 10atm or higher. For example, the hydrostatic bonding process may be performed at about 250°C and about 15atm. In an exemplary embodiment, the pre-bonding process of step S75 may be performed at a temperature lower than the temperature of the hydrostatic bonding process of step S77 and at a pressure lower than the pressure of the hydrostatic bonding process of step S77. For example, the pre-bonding process may be performed at a temperature lower than the curing temperature of the uncured non-conductive films 160″ and 150″, and the hydrostatic bonding process may be performed at a temperature higher than the curing temperature.

[0107] Through the recess process, the internal gaps of the first non-conductive film 160 and the second non-conductive film 150 can be eliminated, and the first non-conductive film 160 and the second non-conductive film 150 can be more firmly bonded to the connection bumps 170A, 170B, 170C, and 170D. Therefore, the recess process can prevent defects caused by overflow of the first uncured non-conductive film 160' and the second uncured non-conductive film 150', and can achieve a firm bond by increasing the filling rate of the first non-conductive film 160 and the second non-conductive film 150.

[0108] like Fig.12 As shown, the molding member 180 may be formed to encapsulate the first to fourth semiconductor chips 100A, 100B, 100C, and 100D disposed on the base substrate 300 .

[0109] The molding member 180 may be formed to surround the side surfaces of the semiconductor chips 100A, 100B, 100C, and 100D, and in the present exemplary embodiment, may be formed to cover the upper surface of the semiconductor chip 100D. In addition, the molding member 180 may be formed to surround the side surfaces of the first non-conductive film 160 and the second non-conductive film 150. Next, the external connection terminal 340 may be formed on the lower surface pad 320 of the base substrate 300. The external connection terminal 340 may electrically connect the semiconductor package to an external device. For example, the external connection terminal 340 may be a solder ball or a bump of various shapes.

[0110] Subsequently, a dicing process may be performed (parts shown by dotted lines may be removed) to separate the semiconductor chips 100A, 100B, 100C, and 100D into Figure 5 The semiconductor package 200B shown. The side of the molding member 180 may have a coplanar surface that is substantially flat with the side of the base substrate 300. In the present exemplary embodiment, since the first non-conductive film 160 and the second non-conductive film 150 have the concave surfaces CS1 and CS2, the bonding surface between the molding member 180 and the first non-conductive film 160 and the second non-conductive film 150 may be increased, so that the bonding strength therebetween is increased. Therefore, the reliability of the semiconductor package may be increased.

[0111] Although it has been combined Figure 9-12 A method of manufacturing the semiconductor package 200B is described, but it is obvious to those skilled in the art that modifications and variations may be made, for example, semiconductor packages 200 and 200A having structures different from the structure of the semiconductor package 200B may be manufactured without departing from the scope of the inventive concept. For example, as described above, Figure 1 and Figure 4 The semiconductor packages 200 and 200A shown in FIG. 3 may be manufactured by using a separate carrier substrate instead of the base substrate 300 in a manner similar to configuring a semiconductor chip stack.

[0112] Fig.13 is a block diagram illustrating a configuration of a semiconductor package according to example embodiments.

[0113] like Fig.13 As shown, the semiconductor device 1000 may include a microprocessor unit (MPU) 1010, a memory 1020, an interface 1030, a graphics processing unit (GPU) 1040, a functional block 1050, and a bus 1060 connecting the MPU 1010, the memory 1020, the interface 1030, the GPU 1040, and the functional block 1050. The semiconductor device 1000 may include both the microprocessor unit 1010 and the graphics processing unit 1040, or may include only one of the two.

[0114] The microprocessor unit 1010 may include a core and an L2 cache. For example, the microprocessor unit 1010 may include multiple cores. Each core in the multiple cores may have the same or different performance characteristics from each other. Each core in the multiple cores may be activated at the same time, or each core in the multiple cores may be activated at different time points from each other.

[0115] The memory 1020 may store the result processed by the functional block 1050, etc. under the control of the microprocessor unit 1010. The interface 1030 may send data or signals to or receive data or signals from an external device. The graphics processing unit 1040 may process a graphics function. For example, the graphics processing unit 1040 may execute a video codec or may process 3D graphics. The functional block may perform various functions. For example, when the semiconductor package 100 is an application processor (AP) used in a mobile device, a portion of the functional block 1050 may perform a communication function. In particular, the semiconductor device 1000 may include a processor such as a processor for displaying images or a display for displaying images. Figure 1 , Figure 4 and Figure 5 The semiconductor packages 200, 200A and 200B described in FIG.

[0116] As described above, according to the exemplary embodiments of the present invention, by controlling the problem of non-conductive film (NFC) flowing out from between semiconductor chips (or between a base substrate and a semiconductor chip) through a hydrostatic bonding process, the space between packages on a base substrate can be reduced, and productivity can be improved. In addition, the reliability of the package can be increased by improving the bonding strength between the side of the non-conductive film and the external molding member.

[0117] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor package, include: A first semiconductor chip having a first through substrate via; a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip having a second through substrate via connected to the first through substrate via; as well as a first adhesive layer disposed between the first semiconductor chip and the second semiconductor chip, wherein the first uncured adhesive layer is cured to form the first adhesive layer by curing the first uncured adhesive layer at a first temperature under a first pressure, so that a side of the first adhesive layer is recessed from a side of the first semiconductor chip and the second semiconductor chip, wherein the first pressure is formed by using a pressurized fluid, and The first temperature is higher than a curing temperature of the first uncured adhesive layer.

2. The semiconductor package according to claim 1, in, The side surface of the first adhesive layer has a concave surface.

3. The semiconductor package according to claim 1, further comprising: include: A molding member surrounds side surfaces of the first and second semiconductor chips and side surfaces of the first adhesive layer.

4. The semiconductor package according to claim 3, in, The molding member is in contact with a side surface of the first adhesive layer.

5. The semiconductor package according to claim 3, further comprising: include: A heat dissipation plate is provided on the second semiconductor chip and the molding member.

6. The semiconductor package according to claim 1, further comprising: include: a base substrate on which the first semiconductor chip is mounted, wherein the base substrate includes a wiring circuit connected to the first substrate through-hole of the first semiconductor chip; and a second adhesive layer disposed between the first semiconductor chip and the base substrate, The side surface of the second adhesive layer is recessed from the side surface of the first semiconductor chip.

7. The semiconductor package according to claim 6, in, The first adhesive layer and the second adhesive layer are formed of different materials.

8. The semiconductor package according to claim 1, further comprising: include: a third semiconductor chip, stacked in a direction perpendicular to the upper surface of the second semiconductor chip and comprising a third substrate through-hole electrically connected to the second substrate through-hole; as well as a second adhesive layer disposed between the second semiconductor chip and the third semiconductor chip, The side surfaces of the second adhesive layer are recessed from the side surfaces of the second semiconductor chip and the third semiconductor chip.

9. The semiconductor package according to claim 1, in, The first semiconductor chip and the second semiconductor chip include memory chips, and the semiconductor package is a high bandwidth memory HBM device.

10. A semiconductor package, include: a base substrate having a wiring circuit; a plurality of semiconductor chips stacked in a direction perpendicular to the upper surface of the base substrate; a first adhesive layer disposed between the base substrate and a lowermost semiconductor chip among the plurality of semiconductor chips, wherein the first uncured adhesive layer is cured to form the first adhesive layer by curing the first uncured adhesive layer at a first temperature under a first pressure, so that a side of the first adhesive layer is recessed from a side of the lowermost semiconductor chip; a plurality of second adhesive layers, each of the second adhesive layers being disposed between corresponding two adjacent semiconductor chips among the plurality of semiconductor chips, and the second uncured adhesive layer being cured to form the second adhesive layer by curing the second uncured adhesive layer at the first temperature under the first pressure, so that the second adhesive layer has a side surface recessed from the side surfaces of the corresponding two adjacent semiconductor chips, wherein the first pressure is formed by using a pressurized fluid, and The first temperature is higher than the curing temperatures of the first uncured adhesive layer and the second uncured adhesive layer.

11. The semiconductor package according to claim 10, in, The base substrate has a surface area greater than that of each of the plurality of semiconductor chips.

12. The semiconductor package according to claim 10, in, Each of the plurality of semiconductor chips has substantially the same surface area.

13. The semiconductor package according to claim 10, in, The side surfaces of the plurality of second adhesive layers have concave surfaces.

14. The semiconductor package according to claim 10, in, The first adhesive layer has a thickness smaller than a thickness of each of the plurality of second adhesive layers.

15. The semiconductor package according to claim 10, in, The side surface of the first adhesive layer has a first recessed depth, each of the side surfaces of the plurality of second adhesive layers has a second recessed depth, and the first recessed depth is different from the second recessed depth.

16. The semiconductor package according to claim 10, further comprising: include: a molding member surrounding the side surfaces of the plurality of semiconductor chips and the side surfaces of the first adhesive layer and the plurality of second adhesive layers, Wherein, the molding member is disposed on a portion of an upper surface of the base substrate.

17. A semiconductor package, include: A first semiconductor chip and a second semiconductor chip are stacked in a vertical direction, each of the first semiconductor chip and the second semiconductor chip having a semiconductor substrate whose lower surface and upper surface are opposite to each other, a semiconductor device layer disposed on the lower surface of the substrate, and a substrate through hole penetrating the semiconductor substrate and the semiconductor device layer; as well as an adhesive layer disposed between the first semiconductor chip and the second semiconductor chip, wherein the substrate through hole of the first semiconductor chip is connected to the substrate through hole of the second semiconductor chip, and the uncured adhesive layer is cured to form the adhesive layer by curing the uncured adhesive layer at a first temperature under a first pressure, so that the side of the adhesive layer is a concave surface recessed from the side of the first semiconductor chip and the second semiconductor chip, wherein the first pressure is formed by using a pressurized fluid, and Wherein, the first temperature is higher than the curing temperature of the uncured adhesive layer.

18. The semiconductor package according to claim 17, in, The adhesive layer has a portion extending on a side surface of at least one of the first semiconductor chip and the second semiconductor chip.

19. The semiconductor package according to claim 17, further comprising: include: a molding member surrounding the side surfaces of the first semiconductor chip and the second semiconductor chip and the concave surface of the adhesive layer, The molding member is filled in the concave surface of the adhesive layer.

20. The semiconductor package according to claim 17, in, The first semiconductor chip is a logic chip, and the second semiconductor chip is a memory chip.

21. A method of manufacturing a semiconductor package, include: stacking each of the plurality of semiconductor chips and each of the plurality of first uncured adhesive layers alternately on one another; as well as curing the plurality of first uncured adhesive layers at a first temperature under a first pressure so that the plurality of first uncured adhesive layers are cured to form a plurality of first cured adhesive layers, a side surface of each of the plurality of first cured adhesive layers being recessed from side surfaces of corresponding two adjacent semiconductor chips of the plurality of semiconductor chips, wherein the first pressure is established by using a pressurized fluid, and The first temperature is higher than the curing temperature of the plurality of first uncured adhesive layers.

22. The method for manufacturing a semiconductor package according to claim 21, further comprising: include: Prior to curing the plurality of first uncured adhesive layers, the plurality of stacked semiconductor chips are pre-bonded to the plurality of first uncured adhesive layers by thermally compressing the plurality of stacked semiconductor chips at a second temperature under a second pressure, wherein the second temperature is lower than the first temperature and the second pressure is lower than the first pressure.

23. The method for manufacturing a semiconductor package according to claim 22, in, The pre-bonding is performed so that each of the plurality of first uncured adhesive layers does not protrude from sides of corresponding two semiconductor chips among the plurality of semiconductor chips.

24. The method for manufacturing a semiconductor package according to claim 21, in, Stacking the plurality of semiconductor chips comprises: disposing a lowermost semiconductor chip among the plurality of semiconductor chips on a base substrate having a wiring circuit; and A second uncured adhesive layer is disposed between the lowermost semiconductor chip and the base substrate.

25. The method for manufacturing a semiconductor package according to claim 24, in, Curing the plurality of first uncured adhesive layers includes curing the second uncured adhesive layer so that the second uncured adhesive layer is cured to form a second cured adhesive layer having a side recessed from a side of the lowermost semiconductor chip.

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