A visible light wide-band high-efficiency PIN photodiode and its preparation method

Abstract

The present invention discloses a high-efficiency PIN photodiode with a wide visible light spectrum and a preparation method thereof. The high-efficiency PIN photodiode with a wide visible light spectrum comprises a chip and a PIN photodiode integrated in the top silicon layer on the chip, and a single PIN photodiode comprises a substrate silicon layer, a SiO2 layer located on the substrate silicon layer, a top silicon layer located on the SiO2 layer, p-type Si, i-type Si and n-type Si located in the top silicon layer, an air hole array located in the i-type Si, and electrodes located on the p-type Si and the n-type Si. The high-efficiency PIN photodiode with a wide visible light spectrum described in the present invention can simultaneously meet the response from the blue light to red light band range and the high absorption rate in this band.

Description

Technical Field

[0001] The present invention relates to the field of optical communication devices, and more specifically, to a high-efficiency PIN photodiode with a wide visible light spectrum and a preparation method thereof. Background Art

[0002] Visible light communication (VLC) has the advantages of being green, environmentally friendly, highly secure, and anti-interference, and has become a research hotspot. Since the sensitivity spectrum of silicon is between 380nm and 1100nm, the visible light detectors of the VLC system are mainly silicon-based photodiodes. However, the sensitive wavelength of the existing visible light silicon-based detectors on the market is 550nm or 620nm, so the quantum efficiency of the spectrum in the blue, cyan, yellow and orange bands is very low. The absorption coefficient of silicon to visible light is different, and the absorption coefficient decreases with the increase of wavelength, so the incident depth of light in each band is quite different, among which the incident depth of blue light is about 0.2μm, and the incident depth of red light is about 10μm. When designing the thickness of the photodiode, if the incident depth of red light is considered, it will affect the absorption rate of blue light. Conversely, if the incident depth of blue light is considered, the transmittance of red light will increase, while the absorption rate will decrease. It is difficult to simultaneously meet the overall high absorption rate from blue light to red light bands in the same photodiode. Summary of the invention

[0003] The present invention aims to overcome at least one of the deficiencies of the above-mentioned prior art and provide a high-efficiency PIN photodiode with a wide visible light spectrum, wherein the high-efficiency PIN photodiode with a wide visible light spectrum can simultaneously meet the response from the blue light to the red light band and the high absorption rate within the band in the same photodiode.

[0004] Another object of the present invention is to provide a method for preparing the high-efficiency PIN photodiode with a wide visible light spectrum.

[0005] The technical solution adopted by the present invention is:

[0006] A high-efficiency PIN photodiode with a wide visible light spectrum comprises a chip and a PIN photodiode integrated in a top silicon layer on the chip, wherein a single PIN photodiode comprises a substrate silicon layer, a SiO2 layer located on the substrate silicon layer, a top silicon layer located on the SiO2 layer, p-type Si, i-type Si and n-type Si located in the top silicon layer, an air hole array located in the i-type Si, and electrodes located on the p-type Si and the n-type Si.

[0007] Visible light wide-spectrum high-efficiency PIN photodiode Since the PIN photodiode is located in the top silicon of the chip and is designed horizontally, the intrinsic region of the photodiode is completely exposed to the air. When light is incident, it can directly irradiate the surface of the intrinsic region. For blue light, the photons of blue light can be directly absorbed in the intrinsic region, thereby improving the quantum efficiency of blue light; but for red light, since the thickness of the top silicon of the chip is relatively thin and the incidence depth of red light is large, when the red light is incident on the intrinsic region, most of the red light will be transmitted out, and the quantum efficiency of red light will be reduced. The visible light wide-spectrum high-efficiency PIN photodiode described in the present invention is designed with an air hole array in the intrinsic layer. The air on the surface of the photodiode and the two-dimensional hole array in the intrinsic layer and the SiO2 film form a structure similar to an optical fiber, so that the red light can be totally reflected in the intrinsic region, thereby increasing the absorption rate of red light. In addition, since the air hole array is evenly distributed, a Bragg grating is formed, which reduces the reflectivity of light and further improves the absorption rate of light. The high-efficiency PIN photodiode with a wide visible light spectrum of the present invention can simultaneously meet the overall high absorption rate from the blue light to the red light band in the same photodiode.

[0008] Preferably, the period P of the air hole array is 400nm-500nm, and the filling rate f (filling rate is the percentage of the area of ​​the air holes to the silicon area in a single period, f = πd 2 / 4p 2 , d is the diameter of the air hole) is 40%-60%.

[0009] Preferably, the chip is a SOI wafer chip.

[0010] Preferably, the i-type Si is located between p-type Si and n-type Si.

[0011] Preferably, the width of the p-type Si is 0.1 μm-100 μm, and the length is consistent with the width of the i-type Si.

[0012] Preferably, the i-type silicon has a width of 1 μm-500 μm and a length consistent with the i-type Si thickness.

[0013] Preferably, the n-type Si has a width of 0.1 μm-100 μm, and a length consistent with the width of the i-type Si.

[0014] The method for preparing the visible light wide-spectrum high-efficiency PIN photodiode comprises the following steps:

[0015] (1) Selecting an SOI chip with a top silicon thickness of 2-5 μm, and sequentially placing the SOI chip in piranha cleaning solution, ethanol, acetone, ethanol, and deionized water for ultrasonic cleaning;

[0016] (2) Spin coating a protective layer on the surface of the SOI chip, then pre-baking it on a hot plate, then photolithography using a photolithography machine, removing the excess protective layer in a developer, and finally hardening it on a hot plate to prepare a mask layer with p-Si;

[0017] (3) Using ion implantation to form B heavily doped p ++ layer is used as a p-type ohmic contact layer with a doping concentration of 10 15 -10 19 cm -3 , removing the mask layer;

[0018] (4) Repeat step (2) to make n ++ layer mask layer, and then use ion implantation to form P heavily doped n ++ layer is used as an n-type ohmic contact layer with a doping concentration of 10 15 -10 19 cm -3 , and then removing the mask layer;

[0019] (5) Repeat the operation process of step (2) to prepare the mask layer of the electrode, and then use electron beam evaporation to deposit 10-30 nm / 90-110 nm thick Pt / Al, then strip off the excess metal in an acetone solution, and finally perform annealing in a N2 environment;

[0020] (6) Repeat the operation process of step (2) to make an i-type Si mask layer, and then use ion implantation to form a P lightly doped n-type Si layer. - layer is used as the intrinsic region, and the doping concentration is 10 12 -10 16 cm -3 , and then remove the mask layer; make a mask layer of the air hole array again, use reactive ion etching or deep reactive ion etching to make the micro-nano optical structure in the intrinsic layer of the photodiode, the air holes are arranged in a cubic lattice, and then remove the mask layer.

[0021] Preferably, the thickness of the Pt / Al is 20nm / 100nm.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention designs an air hole array in the intrinsic layer, and a structure similar to an optical fiber is formed by the air on the surface of the photodiode, the intrinsic region of the photodiode with a two-dimensional hole array, and the SiO2 layer in the SOI, so that the light can be totally reflected in the intrinsic region, thereby increasing the light absorption rate. In addition, since the air hole array is evenly distributed, a Bragg grating is formed, which reduces the reflectivity of the light and further improves the light absorption rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the overall structure of a high-efficiency PIN photodiode with a wide visible light spectrum in an embodiment.

[0024] Figure 2 FIG. 4 is a cross-sectional view of a single PIN photodiode unit in an embodiment.

[0025] Figure 3 Schematic diagram of the device structure obtained in step (1) of the embodiment.

[0026] Figure 4 Schematic diagram of the device structure obtained in step (2) of the embodiment.

[0027] Figure 5 Schematic diagram of the device structure obtained in step (3) of the embodiment.

[0028] Figure 6 Schematic diagram of the device structure obtained in step (4) of the embodiment.

[0029] Figure 7 1 is a top view of the device structure obtained in step (5) of the embodiment.

[0030] Figure 8 Schematic diagram of the device structure obtained in step (6) of the embodiment.

[0031] Description of the drawings: 1. Top silicon layer; 2. SiO2 layer; 3. Substrate silicon layer; 4. p-type Si; 5. n-type Si; 6. Air hole array; 7. i-type Si; 8. Electrode; 10. PIN photodiode; 20. Chip. DETAILED DESCRIPTION

[0032] The drawings of the present invention are only for illustrative purposes and should not be construed as limiting the present invention. In order to better illustrate the following embodiments, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product; it is understandable to those skilled in the art that some well-known structures and their descriptions in the drawings may be omitted.

[0033] Example

[0034] like Figure 1 As shown, a high-efficiency PIN photodiode with a wide visible light spectrum includes a chip 20 and a PIN photodiode 10 integrated on the chip 20, as shown in FIG. Figure 2As shown, a single PIN photodiode includes a substrate silicon layer 3, a SiO2 layer 2 located on the substrate silicon layer 3, a top silicon layer 1 located on the SiO2 layer, p-type Si 4, i-type Si 7 and n-type Si 5 located in the top silicon layer 1, an air hole array 6 located in the i-type Si 7, and an electrode 8 located on the p-type Si 4 and the n-type Si 5, wherein the i-type Si is located between the p-type Si and the n-type Si. More specifically, the period p of the air hole array 6 described in this embodiment is 400nm-500nm, and the filling rate is 40%-60%.

[0035] Furthermore, in this embodiment, the width of the p-type Si is 0.1μm-100μm, and the length is consistent with the width of the i-type Si; the width of the i-type Si is 1μm-500μm, and the length is consistent with the width of the i-type Si; the width of the n-type Si is 0.1μm-100μm, and the length is consistent with the width of the i-type Si.

[0036] The preparation process of the high-efficiency PIN photodiode with a wide visible light spectrum described in this embodiment is as follows:

[0037] (1) Selecting a SOI wafer chip with a top silicon thickness of 2-5 μm, and sequentially placing the SOI wafer chip in piranha cleaning solution, ethanol, acetone, ethanol, and deionized water for ultrasonic cleaning; Figure 3 As shown;

[0038] (2) Spin-coat a protective layer on the surface of the SOI chip, then perform a pre-bake treatment on a hot plate, then use a photolithography machine to perform photolithography, remove the excess protective layer in a developer, and finally perform a hardening treatment on a hot plate to prepare a mask layer with p-Si, such as Figure 4 As shown;

[0039] (3) Using ion implantation to form B heavily doped p ++ layer is used as a p-type ohmic contact layer with a doping concentration of 10 15 -10 19 cm -3 , remove the mask layer, such as Figure 5 As shown;

[0040] (4) Repeat step (2) to make n ++ layer mask layer, and then use ion implantation to form P heavily doped n ++ layer is used as an n-type ohmic contact layer with a doping concentration of 10 15 -10 19 cm -3 , and then remove the mask layer, such as Figure 6 As shown;

[0041] (5) Repeat the operation process of step (2) to prepare the mask layer of the electrode, and then use electron beam evaporation to deposit 20nm / 100nm thick Pt / Al, then strip off the excess metal in acetone solution, and finally anneal in N2 environment, such as Figure 7 As shown;

[0042] (7) Repeat the operation process of step (2) to make an i-type Si mask layer, and then use ion implantation to form a P lightly doped n-type Si layer. - layer is used as the intrinsic region, and the doping concentration is 10 12 -10 16 cm -3 , and then remove the mask layer; make a mask layer of the air hole array again, and use reactive ion etching or deep reactive ion etching to respectively make micro-nano optical structures in the intrinsic layer of the three color photodiodes, wherein the period p of the air hole array is 400nm-500nm, the filling rate f is 40%-60%, and the air holes are arranged in a cubic lattice, and then remove the mask layer, such as Figure 8 shown.

[0043] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the technical solution of the present invention, and are not intended to limit the specific implementation methods of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the claims of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. A method for preparing a high-efficiency PIN photodiode with a wide visible light spectrum, wherein the high-efficiency PIN photodiode with a wide visible light spectrum comprises a chip and a PIN photodiode integrated in the top silicon layer on the chip, wherein a single PIN photodiode comprises a substrate silicon layer, a SiO2 layer on the substrate silicon layer, a top silicon layer on the SiO2 layer, p-type Si, i-type Si and n-type Si in the top silicon layer, an air hole array in the i-type Si, and electrodes on the p-type Si and the n-type Si, wherein: The preparation method comprises the following steps: (1) Selecting an SOI chip with a top silicon thickness of 2-5 μm, and sequentially placing the SOI chip in piranha cleaning solution, ethanol, acetone, ethanol, and deionized water for ultrasonic cleaning; (2) Spin coating a protective layer on the surface of the SOI chip, then pre-baking it on a hot plate, then photolithography using a photolithography machine, removing the excess protective layer in a developer, and finally hardening it on a hot plate to prepare a mask layer with p-Si; (3) Using ion implantation to form B heavily doped p ++ layer is used as a p-type ohmic contact layer with a doping concentration of 10 15 -10 19 cm -3 , removing the mask layer; (4) Repeat step (2) to make n ++ layer mask layer, and then use ion implantation to form P heavily doped n ++ layer is used as an n-type ohmic contact layer with a doping concentration of 10 15 -10 19 cm -3 , and then removing the mask layer; (5) Repeat the operation process of step (2) to prepare the mask layer of the electrode, and then use electron beam evaporation to deposit 10-30 nm / 90-110 nm thick Pt / Al, then strip off the excess metal in an acetone solution, and finally perform annealing in a N2 environment; (6) Repeat the operation process of step (2) to make an i-type Si mask layer, and then use ion implantation to form a P lightly doped n-type Si layer. - layer is used as the intrinsic region, and the doping concentration is 10 12 -10 16 cm -3 , and then remove the mask layer; make a mask layer of the air hole array again, use reactive ion etching or deep reactive ion etching to make the micro-nano optical structure in the intrinsic layer of the photodiode, the air holes are arranged in a cubic lattice, and then remove the mask layer.

2. The method for preparing a high-efficiency PIN photodiode with a wide visible light spectrum according to claim 1, characterized in that: The thickness of the Pt / Al is 20nm / 100nm.

3. The method for preparing a high-efficiency PIN photodiode with a wide visible light spectrum according to claim 1, characterized in that: The period of the air hole array is 400nm-500nm, and the filling rate is 40%-60%.

4. The method for preparing a high-efficiency PIN photodiode with a wide visible light spectrum according to claim 1, characterized in that: The chip is a SOI wafer chip.

5. The method for preparing a high-efficiency PIN photodiode with a wide visible light spectrum according to claim 1, characterized in that: The i-type Si is located between the p-type Si and the n-type Si.

6. The method for preparing a high-efficiency PIN photodiode with a wide visible light spectrum according to claim 1, characterized in that: The width of the p-type Si is 0.1 μm-100 μm, and the length is consistent with the width of the i-type Si.

7. The method for preparing a high-efficiency PIN photodiode with a wide visible light spectrum according to claim 1, characterized in that: The i-type silicon has a width of 1 μm-500 μm, and a length that is consistent with the width of the i-type Si.

8. The method for preparing a high-efficiency PIN photodiode with a wide visible light spectrum according to claim 1, characterized in that: The width of the n-type Si is 0.1 μm-100 μm, and the length is consistent with the width of the i-type Si.

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