EMMC memory logic destruction system and destruction method

Abstract

The present invention relates to an EMMC memory logic destruction system, comprising a trigger signal, an EMMC controller, a high-speed analog switch, an external MCU and an EMMC memory, wherein the trigger signal is electrically connected to the EMMC controller, the EMMC controller is electrically connected to the high-speed analog switch, and the high-speed analog switch is electrically connected to the external MCU and the EMMC memory respectively; the EMMC controller receives the trigger signal and sends a switching signal to the high-speed analog switch, the high-speed analog switch receives the switching signal sent by the EMMC controller, and switches the conduction state according to the switching signal to electrically connect the external MCU to the EMMC memory for reading and writing operations or to electrically connect the EMMC controller to the EMMC memory for logic destruction operations. It also relates to a destruction method. The present invention adopts a high-speed analog switch to enable the external MCU and the EMMC controller to perform read and write or logic destruction operations on the EMMC memory in a time-sharing manner.

Description

Technical Field

[0001] The present invention relates to the technical field of memory logic destruction, and in particular to an EMMC memory logic destruction system and a destruction method. Background Art

[0002] With the development of informatization, data is becoming more and more important, especially in some sensitive occasions, which require the ability to quickly destroy data. Along with this demand, there are currently a large number of SATA hard drives and NVME hard drives with logical destruction products in China. These products can destroy data through destruction signals.

[0003] In the embedded field, some MCUs cannot be directly booted from SATA hard disks or NVME hard disks. They can only be booted from SPI FLASH or EMMC memory. After booting, a hard disk with logical destruction is mounted. This hard disk with logical destruction is not only expensive, but can only destroy the data in the hard disk. Since ordinary MCUs do not have an interface corresponding to EMMC, data stored in SPI FLASH or EMMC memory cannot be destroyed. When the device is accidentally lost or obtained by the enemy, it is easy to cause the leakage of confidential information or sensitive data. Summary of the invention

[0004] The present invention aims at the problems in the prior art and provides an EMMC memory logic destruction system and a destruction method which realize the reading and writing or logic destruction operation of the EMMC memory by time-sharing control of the EMMC memory.

[0005] The technical solution of the present invention to solve the above technical problem is as follows: an EMMC memory logic destruction system, including a trigger signal, an EMMC controller, a high-speed analog switch, an external MCU and an EMMC memory;

[0006] Wherein, the trigger signal is electrically connected to the EMMC controller, so that the EMMC controller outputs a switching signal according to the trigger signal;

[0007] The EMMC controller is electrically connected to the high-speed analog switch, and is used to output a switching signal to the high-speed analog switch according to a trigger signal;

[0008] The high-speed analog switch is electrically connected to the EMMC memory and the external MCU respectively, and is used to switch the conduction state according to the switching signal so that the external MCU is electrically connected to the EMMC memory for reading and writing operations or the EMMC controller is electrically connected to the EMMC memory for logic destruction operations.

[0009] On the basis of the above technical solution, in order to achieve the convenience of use and the stability of the equipment, the present invention can also make the following improvements to the above technical solution:

[0010] Furthermore, the trigger signal is a power-on signal or a destruction signal. When the trigger signal is a power-on signal, the external MCU is electrically connected to the EMMC memory to perform read and write operations; when the trigger signal is a destruction signal, the EMMC controller is electrically connected to the EMMC memory to destroy the data in the EMMC memory.

[0011] Furthermore, it also includes a destroy button, and a destroy signal is sent to the EMMC controller by pressing the destroy button.

[0012] Furthermore, the EMMC controller is electrically connected to the EMMC memory via an SDIO driver, and according to the EMMC interface timing, by programming the SDIO driver, a common EMMC controller without an EMMC interface can destroy the data in the EMMC memory.

[0013] Furthermore, the high-speed analog switch is SGM37222, and four SGM7222 analog switches are used to form a high-speed analog switch switching matrix, and the data transmission rate can reach 500Mhz, thereby effectively ensuring the integrity of the EMMC interface signal.

[0014] Further, the EMMC controller is electrically connected to the CTRL pin of the high-speed analog switch, and sends a switching signal to the high-speed analog switch by controlling the state of the CTRL pin; when the trigger signal is a power-on signal, the EMMC controller controls the pin CTRL to switch to state "0", and the high-speed analog switch switches to electrically connect the external MCU to the EMMC memory for read and write operations; when the trigger signal is a destroy signal, the EMMC control pin CTRL switches to state "1", and the high-speed analog switch reversely switches to electrically connect the EMMC controller to the EMMC memory for a logic destroy operation.

[0015] The present invention also includes a method for destroying EMMC memory logic, which is characterized by comprising the following steps:

[0016] Step 210: Power on the EMMC memory logic destruction system;

[0017] Step 220, read the destruction flag bit, and read the state of the data bit corresponding to the pin CTRL;

[0018] Step 230, destruction enable, determine whether the data in the EMMC memory 150 is being destroyed before power failure, if so, go to step 270 to continue erasing the BLOCK in the memory; otherwise, go to step 240;

[0019] Step 240: Destruction trigger detection, detecting whether the trigger signal is a destruction signal;

[0020] Step 250, determine whether the duration of the destruction signal is greater than 2 seconds, if not, return to step 240 to continue to detect the type of the trigger signal; if yes, execute step 260;

[0021] Step 260, setting the destroy flag, that is, setting the data bit corresponding to the pin CTRL to "1";

[0022] Step 270, erasing Block, erasing data in the EMMC memory 150;

[0023] Step 280, determine whether the full disk erasure is completed, if not, return to step 270 to continue erasing the data in the EMMC memory 150; if yes, execute step 290;

[0024] Step 290, clear the destruction flag bit, and after the destruction is completed, set the data bit corresponding to the pin CTRL to "0".

[0025] The beneficial effects of the present invention are as follows: the present invention adopts a high-speed analog switch to realize the time-sharing reading and writing or logical destruction operation of the EMMC memory by the external MCU and the EMMC controller, thereby ensuring that the data in the EMMC controller is destroyed in time, avoiding information leakage, and improving security; by writing an SDIO driver, an ordinary EMMC controller without an EMMC interface has the function of destroying the data in the EMMC memory, thereby reducing the development cost of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a structural diagram of the EMMC memory logic destruction system;

[0027] Figure 2 A schematic diagram of the circuit structure when the EMMC memory is logically destroyed;

[0028] Figure 3 It is a schematic diagram of the circuit structure when the EMMC memory performs read and write operations;

[0029] Figure 4 Flowchart for logical destruction of EMMC storage. DETAILED DESCRIPTION

[0030] The principles and features of the present invention are described below in conjunction with the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0031] like Figures 1 to 3 As shown, an EMMC memory logic destruction system includes a trigger signal 110, an EMMC controller 120, a high-speed analog switch 130, an external MCU 140 and an EMMC memory 150;

[0032] Wherein, the trigger signal 110 is electrically connected to the EMMC controller 120 of the GD32 series, so that the EMMC controller 120 outputs a switching signal according to the trigger signal 110;

[0033] The EMMC controller 120 is electrically connected to the high-speed analog switch 130 and is used to output a switching signal to the high-speed analog switch 130 according to the trigger signal 110;

[0034] The high-speed analog switch 130 is electrically connected to the EMMC memory 150 and the external MCU 140 respectively, and is used to switch the conduction state according to the switching signal to electrically connect the external MCU 140 to the EMMC memory 150 for read and write operations or to electrically connect the EMMC controller 120 to the EMMC memory 150 for logic destruction operations.

[0035] The trigger signal 110 is a power-on signal or a destroy signal. When the trigger signal 110 is a power-on signal, the external MCU 140 is electrically connected to the EMMC memory 150 to perform read and write operations; when the trigger signal 110 is a destroy signal, the EMMC controller 120 is electrically connected to the EMMC memory 150 to perform a logical destroy operation on the data in the EMMC memory 150.

[0036] A destroy button is also included, and a destroy signal is sent to the EMMC controller 120 by pressing the destroy button.

[0037] The EMMC controller 120 is electrically connected to the EMMC memory 150 through an SDIO driver. According to the EMMC interface timing, by programming the SDIO driver, a common EMMC controller 120 without an EMMC interface can also destroy the data in the EMMC memory 150.

[0038] The high-speed analog switch 130 is SGM37222, and four SGM7222 analog switches are used to form a high-speed analog switch switching matrix. The data transmission rate can reach 500Mhz, thereby effectively ensuring the integrity of the EMMC interface signal.

[0039] The EMMC controller 120 is electrically connected to the CTRL pin of the high-speed analog switch 130, and sends a switching signal to the high-speed analog switch 130 by controlling the state of the CTRL pin; when the trigger signal 110 is a power-on signal, the EMMC controller 120 controls the pin CTRL of the high-speed analog switch 130 to switch to state "0", so that the CMD, RST, CLK, Strobe, D0, D1, D2, and D3 of the EMMC interface are connected to the external MCU 140, that is, the EMMC memory 150 is electrically connected to the external MCU 140 to perform read and write operations; when the trigger signal 110 is a destroy signal, the EMM The C controller 120 first performs a 2S delayed de-jitter operation on the trigger signal 110 to prevent misoperation. After confirming that it is a destruction signal, the EMMC controller 120 controls the pin CTRL of the high-speed analog switch 130 to switch to state "1", and the CMD, RST, CLK, Strobe, D0, D1, D2, and D3 of the EMMC interface are electrically connected to the EMMC controller 120, that is, the EMMC memory 150 is electrically connected to the EMMC controller 120, and a reset command is sent through the RST pin to reset the EMMC memory 150. After the reset is completed, the data in the EMMC memory 150 is erased.

[0040] like Figure 4 The flowchart of the EMMC memory logic destruction method shown includes the following steps:

[0041] Step 210: Power on the EMMC memory logic destruction system;

[0042] Step 220, read the destruction flag bit, and read the state of the data bit corresponding to the pin CTRL;

[0043] Step 230, destruction enable, determine whether the data in the EMMC memory 150 is being destroyed before power failure, if so, go to step 270 to continue erasing the BLOCK in the memory; otherwise, go to step 240;

[0044] Step 240: Destruction trigger detection, detecting whether the trigger signal is a destruction signal;

[0045] Step 250, determine whether the duration of the destruction signal is greater than 2 seconds, if not, return to step 240 to continue to detect the type of the trigger signal; if yes, execute step 260;

[0046] Step 260, setting the destroy flag, that is, setting the data bit corresponding to the pin CTRL to "1";

[0047] Step 270, erasing Block, erasing data in the EMMC memory 150;

[0048] Step 280, determine whether the full disk erasure is completed, if not, return to step 270 to continue erasing the data in the EMMC memory 150; if yes, execute step 290;

[0049] Step 290, clear the destruction flag bit, and after the destruction is completed, set the data bit corresponding to the pin CTRL to "0".

[0050] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An EMMC memory logic destruction system, characterized in that: The invention comprises a trigger signal, an EMMC controller, a high-speed analog switch, an external MCU and an EMMC memory, wherein the trigger signal is electrically connected to the EMMC controller, the EMMC controller is electrically connected to the high-speed analog switch, the EMMC controller is electrically connected to the CTRL pin of the high-speed analog switch, and sends a switching signal to the high-speed analog switch by controlling the state of the CTRL pin of the high-speed analog switch, wherein the high-speed analog switch is electrically connected to the external MCU and the EMMC memory respectively; the EMMC controller receives the trigger signal, wherein the trigger signal is a power-on signal or a destruction signal, and sends a switching signal to the high-speed analog switch, wherein the high-speed analog switch receives the trigger signal from the EMMC controller The switching signal sent by the controller is received, and the conduction state is switched according to the switching signal to electrically connect the external MCU with the EMMC memory for read and write operations or to electrically connect the EMMC controller with the EMMC memory for logic destruction operations: when the trigger signal is a power-on signal, the EMMC controller controls the CTRL pin of the high-speed analog switch to switch to state "0", and the high-speed analog switch switches to electrically connect the external MCU with the EMMC memory for read and write operations; when the trigger signal is a destruction signal, the EMMC controls the CTRL pin of the high-speed analog switch to switch to state "1", and the high-speed analog switch reversely switches to electrically connect the EMMC controller with the EMMC memory for logic destruction operations.

2. The EMMC memory logic destruction system as claimed in claim 1, characterized in that: A destroy button is also included, and a destroy signal is sent to the EMMC controller by pressing the destroy button.

3. The EMMC memory logic destruction system as claimed in claim 1, characterized in that: The EMMC controller is electrically connected to the EMMC memory through an SDIO driver.

4. The EMMC memory logic destruction system as claimed in claim 1, characterized in that: The high-speed analog switch is SGM37222.

5. A method for destroying EMMC memory logic, characterized in that: The steps include: Step 210: Power on the EMMC memory logic destruction system; Step 220, read the destruction flag bit, and read the state of the data bit corresponding to the CTRL pin of the high-speed analog switch; Step 230, destruction enable, determining whether the data in the EMMC memory (150) is being destroyed before power failure, if so, proceeding to step 270 to continue erasing the BLOCK in the memory; Otherwise, execute step 240; Step 240: Destruction trigger detection, detecting whether the trigger signal is a destruction signal; Step 250, determine whether the duration of the destruction signal is greater than 2 seconds, if not, return to step 240 to continue to detect the type of the trigger signal; if yes, execute step 260; Step 260, setting the destroy flag, that is, setting the data bit corresponding to the CTRL pin of the high-speed analog switch to "1", so that the EMMC controller is electrically connected to the EMMC memory; Step 270, erase BLOCK, erase the data in the EMMC memory (150); Step 280, determine whether the full disk erasure is completed, if not, return to step 270 to continue erasing the data in the EMMC memory (150); if yes, execute step 290; Step 290, clear the destruction flag bit. After the destruction is completed, set the data bit corresponding to the CTRL pin of the high-speed analog switch to "0" to electrically connect the external MCU to the EMMC memory.

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