A linear voltage stabilizing circuit and voltage regulating method

Abstract

The present invention discloses a linear voltage stabilization circuit and a voltage adjustment method, which include: a first input circuit, a second input circuit, an adjustment circuit, an output circuit, a sampling circuit and a feedback circuit; the first input circuit is electrically connected to the adjustment circuit and supplies power to the adjustment circuit; the second input circuit is electrically connected to the feedback circuit and supplies power to the feedback circuit; the adjustment circuit is electrically connected to the output circuit, the output circuit is electrically connected to the sampling circuit, the sampling circuit is electrically connected to the feedback circuit, and the feedback circuit is electrically connected to the adjustment circuit to form a sampling feedback adjustment loop; wherein the sampling circuit collects the voltage value of the output circuit; the feedback circuit compares the voltage difference between the voltage value and the reference voltage to obtain a feedback result; the adjustment circuit adjusts the output voltage of the output circuit according to the voltage value input by the first input circuit and the feedback result. The present invention has low voltage stabilization cost, low voltage drop, high conversion efficiency, low heat generation, small PCB area occupation, and reduced packaging volume.

Description

Technical Field

[0001] The present invention relates to the field of power management, and in particular to a linear voltage stabilization circuit and a voltage adjustment method. Background Art

[0002] With the rapid development of science and technology, power management has become an indispensable technology for electronic systems. Currently, there are two types of step-down circuits: series switching step-down and DC linear step-down. The former has many types of components, complex circuits, and high costs; the latter has a high voltage drop in the adjustment circuit, resulting in reduced efficiency. There are several situations:

[0003] 1. Such as Figure 1 Conventional linear step-down chips generally require an input voltage 2V higher than the output voltage to achieve output voltage stability. This results in low efficiency and high heat generation. Under high current conditions, an external heat sink is required to solve the high temperature problem, which indirectly causes an increase in volume.

[0004] 2. Currently, the ultra-low voltage difference linear step-down chip on the market can achieve a voltage drop of 0.1-0.2V to achieve voltage stability.

[0005] 3. Such as Figure 2 , using discrete devices, with NPN and PNP transistors as adjustment tubes, the circuit voltage difference is equivalent to that of conventional linear step-down chips.

[0006] Typically, application system circuits have multiple DC power supplies. Due to high line currents, resulting in high trace lengths, or the high cost of requiring multiple power supply circuits, the nearest available voltage is used as the input voltage and then stepped down to the required DC voltage using a linear step-down circuit. For example, a power supply with 12V and 3.8V power supplies may also require a 3.3V DC power supply within the system circuit. For cost considerations, using solutions 1 and 3 above requires stepping down the 12V to 3.3V. The high voltage drop of the linear step-down circuit results in high heat generation, which increases the overall system temperature. While solution 2 improves efficiency, it also carries a higher component price, making it a less preferred option for product competitiveness. Summary of the Invention

[0007] The present invention aims to provide a linear voltage stabilization circuit and a voltage regulation method, which realize the output voltage stabilization of the present invention with low cost, low voltage drop, high conversion efficiency, and reduced heat generation, thereby occupying a small PCB area and reducing the package volume.

[0008] The technical solutions provided by the present invention are as follows:

[0009] The present invention provides a linear voltage stabilizing circuit, comprising:

[0010] a first input circuit, a second input circuit, an adjustment circuit, an output circuit, a sampling circuit, and a feedback circuit;

[0011] The first input circuit is electrically connected to the voltage input terminal of the adjustment circuit and is used to supply power to the adjustment circuit;

[0012] The second input circuit is electrically connected to the voltage input terminal of the feedback circuit and is used to supply power to the feedback circuit;

[0013] The adjustment circuit is electrically connected to the output circuit, the output circuit is electrically connected to the sampling circuit, the sampling circuit is electrically connected to the feedback circuit, and the feedback circuit is electrically connected to the adjustment circuit to form a sampling feedback adjustment loop; wherein,

[0014] The sampling circuit is used to collect the voltage value of the output circuit;

[0015] The feedback circuit is used to compare the voltage difference between the voltage value and the reference voltage to obtain a feedback result;

[0016] The adjustment circuit is used to adjust the output voltage of the output circuit according to the voltage value input by the first input circuit and the feedback result.

[0017] Further, the feedback circuit includes an error amplifier;

[0018] The first input circuit includes an input power supply and an input filter capacitor;

[0019] The second input circuit includes a power supply for the feedback circuit;

[0020] The output circuit includes an output filter capacitor and a load resistor;

[0021] The adjustment circuit includes an N-channel MOS tube;

[0022] The sampling circuit includes a first sampling resistor and a second sampling resistor:

[0023] The feedback circuit includes a bias resistor and a feedback capacitor;

[0024] The positive terminal of the input power supply is electrically connected to the first pin of the input filter capacitor and the drain of the N-channel MOS transistor, and the negative terminal of the input power supply is grounded; the first pin of the input filter capacitor is electrically connected to the drain of the N-channel MOS transistor, and the second pin of the input filter capacitor is grounded; the source of the N-channel MOS transistor is electrically connected to the first pin of the output filter capacitor, the first pin of the first sampling resistor, and the first pin of the load resistor, and the gate of the N-channel MOS transistor is electrically connected to the second pin of the bias resistor, the output terminal of the error amplifier, and the first pin of the feedback capacitor; the first pin of the output filter capacitor is electrically connected to the first pin of the load resistor, the second pin of the output filter capacitor is grounded, and the second pin of the load resistor is grounded;

[0025] The positive terminal of the feedback circuit power supply is electrically connected to the first pin of the bias resistor, and the negative terminal of the feedback circuit power supply is grounded; the second pin of the bias resistor is electrically connected to the gate of the N-channel MOS tube, the output terminal of the error amplifier, and the first pin of the feedback capacitor;

[0026] The first pin of the feedback capacitor is electrically connected to the second pin of the bias resistor, the gate of the N-channel MOS transistor, and the output terminal of the error amplifier; the second pin of the feedback capacitor is electrically connected to the second pin of the first sampling resistor, the first pin of the second sampling resistor, and the inverting input terminal of the error amplifier;

[0027] The inverting input terminal of the error amplifier is electrically connected to the second pin of the first sampling resistor and the first pin of the second sampling resistor; the non-inverting input terminal of the error amplifier inputs a reference voltage;

[0028] The first pin of the first sampling resistor is electrically connected to the source of the N-channel MOS transistor, the first pin of the output filter capacitor, and the first pin of the load resistor; the second pin of the first sampling resistor is electrically connected to the first pin of the second sampling resistor; and the second pin of the second sampling resistor is grounded.

[0029] Furthermore, the feedback circuit includes a voltage stabilizing diode;

[0030] The first input circuit includes an input power supply and an input filter capacitor;

[0031] The second input circuit includes a power supply for the feedback circuit;

[0032] The output circuit includes an output filter capacitor and a load resistor;

[0033] The adjustment circuit includes an N-channel MOS tube;

[0034] The sampling circuit includes a first sampling resistor and a second sampling resistor:

[0035] The feedback circuit includes a bias resistor and a feedback capacitor;

[0036] The positive terminal of the input power supply is electrically connected to the first pin of the input filter capacitor and the drain of the N-channel MOS transistor, and the negative terminal of the input power supply is grounded; the first pin of the input filter capacitor is electrically connected to the drain of the N-channel MOS transistor, and the second pin of the input filter capacitor is grounded; the source of the N-channel MOS transistor is electrically connected to the first pin of the output filter capacitor, the first pin of the first sampling resistor, and the first pin of the load resistor, and the gate of the N-channel MOS transistor is electrically connected to the second pin of the bias resistor, the negative terminal of the voltage regulator diode, and the first pin of the feedback capacitor; the first pin of the output filter capacitor is electrically connected to the first pin of the load resistor, the second pin of the output filter capacitor is grounded, and the second pin of the load resistor is grounded;

[0037] The positive terminal of the feedback circuit power supply is electrically connected to the first pin of the bias resistor, and the negative terminal of the feedback circuit power supply is grounded; the second pin of the bias resistor is electrically connected to the gate of the N-channel MOS tube, the negative terminal of the voltage regulator diode, and the first pin of the feedback capacitor;

[0038] The first pin of the feedback capacitor is electrically connected to the second pin of the bias resistor, the gate of the N-channel MOS transistor, and the negative end of the voltage regulator diode; the second pin of the feedback capacitor is electrically connected to the second pin of the first sampling resistor, the first pin of the second sampling resistor, and the sampling end of the voltage regulator diode;

[0039] The sampling end of the voltage stabilizing diode is electrically connected to the second pin of the feedback capacitor, the second pin of the first sampling resistor, and the first pin of the second sampling resistor, and the positive end of the voltage stabilizing diode is grounded;

[0040] The first pin of the first sampling resistor is electrically connected to the source of the N-channel MOS transistor, the first pin of the output filter capacitor, and the first pin of the load resistor; the second pin of the first sampling resistor is electrically connected to the first pin of the second sampling resistor; and the second pin of the second sampling resistor is grounded.

[0041] Furthermore, the adjustment circuit is further configured to control the output voltage of the output circuit to decrease when the voltage value input by the first input circuit increases;

[0042] The adjustment circuit is further configured to control the output voltage of the output circuit to increase when the voltage value input by the first input circuit decreases.

[0043] The present invention also provides a voltage adjustment method, comprising: a first input circuit, a second input circuit, an adjustment circuit, an output circuit, a sampling circuit and a feedback circuit; the adjustment circuit, the output circuit, the sampling circuit and the feedback circuit are connected to form a sampling feedback loop; the method comprises the following steps:

[0044] Get the input voltage value;

[0045] collecting a voltage value of the sampling output circuit;

[0046] Comparing the voltage difference between the voltage value and a reference voltage to obtain a feedback result;

[0047] The output voltage is adjusted according to the input voltage value and the feedback result.

[0048] Furthermore, the adjusting the output voltage according to the input voltage value and the feedback result includes the steps of:

[0049] When the input voltage value increases, controlling the output voltage to decrease; or,

[0050] When the input voltage value decreases, the output voltage is controlled to increase.

[0051] The linear voltage stabilization circuit and voltage adjustment method provided by the present invention can achieve the purpose of low output voltage stabilization cost, low voltage drop, high conversion efficiency, and reduced heat generation, thereby occupying a small PCB area and reducing the packaging volume. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of a linear voltage stabilization circuit and a voltage adjustment method.

[0053] Figure 1 It is a structural diagram of the first prior art;

[0054] Figure 2 It is a structural diagram of the third prior art;

[0055] Figure 3 1 is a schematic structural diagram of an embodiment of a linear voltage stabilizing circuit of the present invention;

[0056] Figure 4 1 is a schematic structural diagram of another embodiment of the linear voltage stabilizing circuit of the present invention;

[0057] Figure 5 1 is a schematic structural diagram of another embodiment of the linear voltage stabilizing circuit of the present invention;

[0058] Figure 6is a flow chart of an embodiment of a voltage adjustment method of the present invention. DETAILED DESCRIPTION

[0059] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, specific embodiments of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. Those skilled in the art can, without inventive effort, derive other drawings and other embodiments based on these drawings.

[0060] To simplify the drawings, only the parts relevant to the present invention are schematically shown in each figure. They do not represent the actual structure of the product. Furthermore, to simplify the drawings and facilitate understanding, in some figures, only one of the components with the same structure or function is schematically depicted or labeled. As used herein, "one" not only means "only one" but also "more than one."

[0061] One embodiment of the present invention is a linear voltage stabilizing circuit, such as Figure 3 and 4 Shown, including:

[0062] A first input circuit 10, a second input circuit 60, an adjustment circuit 20, an output circuit 30, a sampling circuit 40 and a feedback circuit 50;

[0063] The first input circuit 10 is electrically connected to the voltage input terminal of the adjustment circuit 20 and is used to supply power to the adjustment circuit 20;

[0064] The second input circuit 60 is electrically connected to the voltage input terminal of the feedback circuit 50 and is used to supply power to the feedback circuit 50;

[0065] The adjustment circuit 20 is electrically connected to the output circuit 30, the output circuit 30 is electrically connected to the sampling circuit 40, the sampling circuit 40 is electrically connected to the feedback circuit 50, and the feedback circuit 50 is electrically connected to the adjustment circuit 20, forming a sampling feedback adjustment loop; wherein,

[0066] The sampling circuit is used to collect the voltage value of the output circuit;

[0067] The feedback circuit is used to compare the voltage difference between the voltage value and the reference voltage to obtain a feedback result;

[0068] The adjustment circuit is used to adjust the output voltage of the output circuit according to the voltage value input by the first input circuit and the feedback result.

[0069] The feedback circuit includes an error amplifier (U1);

[0070] The first input circuit 10 includes an input power supply (E1) and an input filter capacitor (C1);

[0071] The second input circuit 60 includes the feedback circuit power supply (E2);

[0072] The output circuit 30 includes an output filter capacitor (C3) and a load resistor (R4);

[0073] The adjustment circuit 20 includes an N-channel MOS transistor (Q1);

[0074] The sampling circuit 40 includes a first sampling resistor (R1) and a second sampling resistor (R2):

[0075] The feedback circuit 50 includes a bias resistor (R3) and a feedback capacitor (C2);

[0076] The positive end of the input power supply (E1) is electrically connected to the first pin of the input filter capacitor (C1) and the drain (D) of the N-channel MOS transistor (Q1), and the negative end of the input power supply (E1) is grounded; the first pin of the input filter capacitor (C1) is electrically connected to the drain (D) of the N-channel MOS transistor (Q1), and the second pin of the input filter capacitor (C1) is grounded; the source of the N-channel MOS transistor (Q1) is electrically connected to the first pin of the output filter capacitor (C3), the first pin of the first sampling resistor (R1), and the first pin of the load resistor (R4); the gate (G) of the N-channel MOS transistor (Q1) is electrically connected to the second pin of the bias resistor (R3), the output end (out) of the error amplifier (U1), and the first pin of the feedback capacitor (C2); the first pin of the output filter capacitor (C3) is electrically connected to the first pin of the load resistor (R4), the second pin of the output filter capacitor (C3) is grounded, and the second pin of the load resistor (R4) is grounded;

[0077] The positive end of the feedback circuit power supply (E2) is electrically connected to the first pin of the bias resistor (R3), and the negative end of the feedback circuit power supply (E2) is grounded; the second pin of the bias resistor (R3) is electrically connected to the gate (G) of the N-channel MOS transistor (Q1), the output end (out) of the error amplifier (U1), and the first pin of the feedback capacitor (C2);

[0078] The first pin of the feedback capacitor (C2) is electrically connected to the second pin of the bias resistor (R3), the gate (G) of the N-channel MOS tube (Q1), and the output end (out) of the error amplifier (U1); the second pin of the feedback capacitor (C2) is electrically connected to the second pin of the first sampling resistor (R1), the first pin of the second sampling resistor (R2), and the inverting input end (-) of the error amplifier (U1);

[0079] The inverting input terminal (-) of the error amplifier (U1) is electrically connected to the second pin of the first sampling resistor (R1) and the first pin of the second sampling resistor (R2); the reference voltage is input to the non-inverting input terminal (+) of the error amplifier (U1);

[0080] The first pin of the first sampling resistor (R1) is electrically connected to the source of the N-channel MOS transistor (Q1), the first pin of the output filter capacitor (C3), and the first pin of the load resistor (R4); the second pin of the first sampling resistor (R1) is electrically connected to the first pin of the second sampling resistor (R2); and the second pin of the second sampling resistor (R2) is grounded.

[0081] Specifically, after the input power supply (E1) is powered on, the input power supply (E1) voltage is filtered by the input filter capacitor (C1). The filtered input voltage is adjusted by the N-channel MOS transistor (Q1) and then output. It is then filtered by the output filter capacitor (C3) and then output. According to the operating principle of the N-channel MOS transistor (Q1), by controlling the gate-source voltage (VGS), the three states of the N-channel MOS transistor (Q1) can be controlled: cutoff, amplification, and saturation conduction. The amplification and saturation conduction states are used to achieve output voltage regulation. In this application, the gate-source voltage (VGS) of the N-channel MOS transistor (Q1) is the difference between the gate voltage and the output voltage. Therefore, a feedback circuit power supply (E2) with a higher voltage than the input power supply (E1) is required to provide a DC power supply to meet the required gate-source voltage (VGS) amplitude of the N-channel MOS transistor (Q1), thereby turning on the N-channel MOS transistor (Q1). The bias resistor (R3) is used by the feedback circuit power supply (E2) to provide a bias voltage for the gate (G) of the N-channel MOS tube (Q1).

[0082] The output voltage of the output terminal (out) of the error amplifier (U1) is adjusted to indirectly control the voltage amplitude of the gate-source voltage (VGS) of the N-channel MOS transistor (Q1). A first sampling resistor (R1) and a second sampling resistor (R2) in the sampling circuit 40 sample the output voltage, and the sampling result is input to the inverting input terminal (-) of the error amplifier (U1), compared with the reference voltage VREF, and amplified. The output result of the output terminal (out) of the error amplifier (U1) is used to control the amplitude of the gate drive voltage of the N-channel MOS transistor (Q1).

[0083] When the input power supply (E1) voltage rises, the output voltage rises, the sampling voltage rises, the error amplifier (U1) compares the voltage of the input inverting input terminal (-) with the reference voltage, the error amplifier (U1) output voltage drops, the gate voltage of the N-channel MOS transistor (Q1) drops, and the gate-source voltage (VGS) of the N-channel MOS transistor (Q1) drops, thereby reducing the amplification factor of the N-channel MOS transistor (Q1) and causing the output voltage to drop.

[0084] When the input power supply (E1) voltage drops, the opposite of the above occurs.

[0085] When the input power supply (E1) voltage approaches the output voltage, the sampled voltage drops. The error amplifier (U1) compares the sampled voltage at its inverting input (-) with the reference voltage, causing the error amplifier (U1) output voltage to rise. This increases the gate voltage of the N-channel MOS transistor (Q1), and the gate-source voltage (VGS) of the N-channel MOS transistor (Q1). When the input power supply (E1) voltage drops, causing the gate-source voltage (VGS) of the N-channel MOS transistor (Q1) to rise to the point where the N-channel MOS transistor (Q1) is saturated and conducting, the output voltage is the difference between the input power supply (E1) voltage and the saturation conduction voltage drop of the N-channel MOS transistor (Q1). The saturation conduction voltage drop is determined by the product of the output current and the saturation on-resistance RDS(ON) of the N-channel MOS transistor (Q1).

[0086] Another embodiment of the present invention is a linear voltage stabilizing circuit, such as Figure 3 and 5 Shown, including:

[0087] A first input circuit 10, a second input circuit 60, an adjustment circuit 20, an output circuit 30, a sampling circuit 40 and a feedback circuit 50;

[0088] The first input circuit 10 is electrically connected to the voltage input terminal of the adjustment circuit 20 and is used to supply power to the adjustment circuit 20;

[0089] The second input circuit 60 is electrically connected to the voltage input terminal of the feedback circuit 50 and is used to supply power to the feedback circuit 50;

[0090] The adjustment circuit 20 is electrically connected to the output circuit 30, the output circuit 30 is electrically connected to the sampling circuit 40, the sampling circuit 40 is electrically connected to the feedback circuit 50, and the feedback circuit 50 is electrically connected to the adjustment circuit 20, forming a sampling feedback adjustment loop; wherein,

[0091] The sampling circuit is used to collect the voltage value of the output circuit;

[0092] The feedback circuit is used to compare the voltage difference between the voltage value and the reference voltage to obtain a feedback result;

[0093] The adjustment circuit is used to adjust the output voltage of the output circuit according to the voltage value input by the first input circuit and the feedback result.

[0094] The feedback circuit includes a voltage stabilizing diode (U2);

[0095] The first input circuit 10 includes an input power supply (E1) and an input filter capacitor (C1);

[0096] The second input circuit 60 includes the feedback circuit power supply (E2);

[0097] The output circuit 30 includes an output filter capacitor (C3) and a load resistor (R4);

[0098] The adjustment circuit 20 includes an N-channel MOS transistor (Q1);

[0099] The sampling circuit 40 includes a first sampling resistor (R1) and a second sampling resistor (R2):

[0100] The feedback circuit 50 includes a bias resistor (R3) and a feedback capacitor (C2);

[0101] The positive end of the input power supply (E1) is electrically connected to the first pin of the input filter capacitor (C1) and the drain (D) of the N-channel MOS transistor (Q1), and the negative end of the input power supply (E1) is grounded; the first pin of the input filter capacitor (C1) is electrically connected to the drain (D) of the N-channel MOS transistor (Q1), and the second pin of the input filter capacitor (C1) is grounded; the source of the N-channel MOS transistor (Q1) is electrically connected to the first pin of the output filter capacitor (C3), the first pin of the first sampling resistor (R1), and the first pin of the load resistor (R4); the gate (G) of the N-channel MOS transistor (Q1) is electrically connected to the second pin of the bias resistor (R3), the negative end (K) of the voltage regulator diode (U2), and the first pin of the feedback capacitor (C2); the first pin of the output filter capacitor (C3) is electrically connected to the first pin of the load resistor (R4), the second pin of the output filter capacitor (C3), and the second pin of the load resistor (R4) are grounded;

[0102] The positive end of the feedback circuit power supply (E2) is electrically connected to the first pin of the bias resistor (R3), and the negative end of the feedback circuit power supply (E2) is grounded; the second pin of the bias resistor (R3) is electrically connected to the gate (G) of the N-channel MOS transistor (Q1), the negative end (K) of the voltage regulator diode (U2), and the first pin of the feedback capacitor (C2);

[0103] The first pin of the feedback capacitor (C2) is electrically connected to the second pin of the bias resistor (R3), the gate (G) of the N-channel MOS transistor (Q1), and the negative end (K) of the voltage stabilizing diode (U2); the second pin of the feedback capacitor (C2) is electrically connected to the second pin of the first sampling resistor (R1), the first pin of the second sampling resistor (R2), and the sampling end (R) of the voltage stabilizing diode (U2);

[0104] The sampling terminal (R) of the voltage stabilizing diode (U2) is electrically connected to the second pin of the feedback capacitor (C2), the second pin of the first sampling resistor (R1), and the first pin of the second sampling resistor (R2), and the positive terminal (A) of the voltage stabilizing diode (U2) is grounded;

[0105] The first pin of the first sampling resistor (R1) is electrically connected to the source of the N-channel MOS transistor (Q1), the first pin of the output filter capacitor (C3), and the first pin of the load resistor (R4); the second pin of the first sampling resistor (R1) is electrically connected to the first pin of the second sampling resistor (R2); and the second pin of the second sampling resistor (R2) is grounded.

[0106] Specifically, after the input power supply (E1) is powered on, the input power supply (E1) voltage is filtered by the input filter capacitor (C1). The filtered input voltage is adjusted by the N-channel MOS transistor (Q1) and then output. It is then filtered by the output filter capacitor (C3) and then output. According to the operating principle of the N-channel MOS transistor (Q1), by controlling the gate-source voltage (VGS), the three states of the N-channel MOS transistor (Q1) can be controlled: cutoff, amplification, and saturation conduction. The amplification and saturation conduction states are used to achieve output voltage regulation. In this application, the gate-source voltage (VGS) of the N-channel MOS transistor (Q1) is the difference between the gate voltage and the output voltage. Therefore, a feedback circuit power supply (E2) with a higher voltage than the input power supply (E1) is required to provide a DC power supply to meet the required gate-source voltage (VGS) amplitude of the N-channel MOS transistor (Q1), thereby turning on the N-channel MOS transistor (Q1). The bias resistor (R3) is used by the feedback circuit power supply (E2) to provide a bias voltage for the gate (G) of the N-channel MOS tube (Q1).

[0107] The gate voltage is adjusted by the negative terminal (K) of the voltage stabilizing diode (U2), indirectly controlling the voltage amplitude of the gate-source voltage (VGS) of the N-channel MOS transistor (Q1). The first sampling resistor (R1) and the second sampling resistor (R2) of the sampling circuit 40 sample the output voltage, input the sampling result to the sampling terminal (R) of the voltage stabilizing diode (U2), and compare and amplify it with the reference voltage within the voltage stabilizing diode (U2) chip. The output result at the negative terminal of the voltage stabilizing diode (U2) is used to control the amplitude of the gate drive voltage of the N-channel MOS transistor (Q1).

[0108] When the input voltage rises, the output voltage rises, the sampling voltage rises, and the Zener diode (U2) compares the sampling voltage value of the input sampling terminal (R) with the reference voltage inside the Zener diode (U2) chip. The output voltage of the negative terminal of the Zener diode (U2) drops, the gate voltage of the N-channel MOS transistor (Q1) drops, and the gate-source voltage (VGS) of the N-channel MOS transistor (Q1) drops, thereby reducing the amplification factor of the N-channel MOS transistor (Q1) and causing the output voltage to drop.

[0109] When the input voltage drops, the opposite happens.

[0110] When the input voltage approaches the output voltage, the sampling voltage drops. The Zener diode (U2) compares the input sampling terminal with the reference voltage within the Zener diode (U2) chip, causing the Zener diode (U2) output voltage to rise. This increases the gate voltage of the N-channel MOS transistor (Q1), and the gate-source voltage (VGS) of the N-channel MOS transistor (Q1). When the input power supply (E1) voltage drops, causing the gate-source voltage (VGS) of the N-channel MOS transistor (Q1) to rise until the N-channel MOS transistor (Q1) is saturated and conducting, the output voltage is the difference between the input power supply (E1) voltage and the saturation conduction voltage drop of the N-channel MOS transistor (Q1). The saturation conduction voltage drop is determined by the product of the output current and the saturation on-resistance (RDS(ON)) of the N-channel MOS transistor (Q1).

[0111] The present invention is applicable to existing DC power supply systems with two or more circuits and employs an N-channel MOS transistor (Q1) as a series voltage divider adjustment device. According to the operating principle of the N-channel MOS transistor (Q1), the N-channel MOS transistor (Q1) can only switch from a cutoff state to an amplifying state when the control voltage is higher than the gate (G) turn-on voltage VGS(th) of the N-channel MOS transistor (Q1). Typically, the gate (G) turn-on voltage VGS(th) of the N-channel MOS transistor (Q1) is above 2V. A higher-voltage DC power supply is introduced to power the feedback circuit 50, thereby enabling a higher and wider adjustment range for the gate voltage controlled by the feedback circuit 50. When the input voltage drops close to the output voltage, the gate drive voltage controlled by the feedback circuit 50 reaches its maximum value, causing the N-channel MOS transistor (Q1) to switch from an amplifying state to a saturated conduction state. At this point, its minimum voltage drop is determined by the product of the N-channel MOS transistor (Q1) on-resistance RDS(ON) and the current flowing through the load resistor (R4). Based on the actual operating current requirements of the circuit, the on-resistance RDS(ON) of the N-channel MOS transistor (Q1) that meets the voltage drop can be flexibly selected based on the on-resistance RDS(ON) in the N-channel MOS transistor (Q1) data sheet to achieve ultra-low voltage drop linear voltage regulation.

[0112] like Figure 3 and Figure 4 As shown, or as Figure 3 and Figure 5 As shown, the workflow

[0113] When the input voltage of the first input circuit 10 increases, the output voltage of the output circuit 30 increases, thereby increasing the sampling voltage of the sampling circuit 40 of the sampling feedback adjustment loop, causing the feedback voltage of the feedback circuit 50 to decrease, resulting in an increase in the voltage difference of the adjustment circuit 20, and finally causing the output voltage of the output circuit 30 to decrease.

[0114] When the input voltage of the first input circuit 10 drops, the output voltage of the output circuit 30 drops, thereby causing the sampling voltage of the sampling circuit 40 of the sampling feedback adjustment loop to drop, causing the feedback voltage of the feedback circuit 50 to rise, resulting in a drop in the voltage difference of the adjustment circuit 20, and finally causing the output voltage of the output circuit 30 to rise.

[0115] Compared with the prior art, the present invention eliminates the need for ultra-low voltage drop linear step-down chips, thereby reducing voltage stabilization costs. Flexible selection of an N-channel MOS transistor (Q1) facilitates low voltage drop adjustment. Furthermore, the voltage drop in the adjustment circuit 20 eliminates the need to require the input voltage to be 2V higher than the output voltage to achieve output power stability, resulting in high conversion efficiency. Furthermore, the voltage drop in the adjustment circuit 20 reduces heat generation, eliminating the need for external heat sinks for cooling under high current conditions. This reduces PCB footprint and packaging size.

[0116] Another embodiment of the present invention provides a voltage adjustment method, comprising a first input circuit, a second input circuit, an adjustment circuit, an output circuit, a sampling circuit, and a feedback circuit; wherein the adjustment circuit, the output circuit, the sampling circuit, and the feedback circuit are connected to form a sampling feedback loop; and the method comprises the following steps: Figure 3-6 As shown, the steps include:

[0117] S100 obtains the input voltage value;

[0118] S200 collects the voltage value of the output circuit;

[0119] S300 compares the voltage difference between the voltage value and the reference voltage to obtain a feedback result;

[0120] S400 adjusts the output voltage according to the input voltage value and the feedback result.

[0121] The present invention is a method embodiment corresponding to the above-mentioned circuit embodiment, and the common parts are not repeated here. To achieve the effect of maintaining a stable output voltage, a feedback circuit power supply (E2) provides a supplementary bias voltage to the feedback circuit through the gate-source voltage difference between the gate (G) and source (S) of the N-channel MOS transistor (Q1), thereby placing the N-channel MOS transistor in an amplified state.

[0122] Preferably, the adjusting the output voltage according to the input voltage value and the feedback result comprises the steps of:

[0123] When the input voltage value increases, controlling the output voltage to decrease; or,

[0124] When the input voltage value decreases, the output voltage is controlled to increase.

[0125] like Figure 3 and Figure 4 As shown, if the voltage value of the input power supply (E1) increases, the input voltage (Vin) increases, and the output voltage (Vout) increases. Due to the output voltage (Vout) in the sampling feedback adjustment loop, the sampled voltage value obtained by sampling the sampling resistor in the sampling feedback loop also increases. The sampled voltage value is compared with the reference voltage input to the positive input terminal (+) of the error amplifier (U1) through the inverting error amplifier (U1). If the sampled voltage value is greater than the reference voltage, the voltage value output by the output terminal (out) of the error amplifier (U1) decreases, causing the gate voltage of the N-channel MOS transistor (Q1) to decrease. Since the source-drain voltage (VDS) of the N-channel MOS transistor (Q1) = gate voltage - source (S) voltage, and since the source (S) voltage of the N-channel MOS transistor (Q1) is the output voltage, the source-drain voltage (VDS) of the N-channel MOS transistor (Q1) decreases, thereby increasing the source-drain voltage (VDS) of the N-channel MOS transistor (Q1). Furthermore, since Vin = Vds + Vout, when the source-drain voltage (VDS) of the N-channel MOS transistor (Q1) increases, the output voltage (Vout) decreases. Similarly, when the voltage of the input power supply (E1) decreases, the input voltage (Vin) decreases, which is the opposite of the voltage regulation process described above.

[0126] like Figure 3 and Figure 5 As shown, if the voltage value of the input power supply (E1) increases, the input voltage (Vin) increases, and the output voltage (Vout) increases. Due to the output voltage (Vout) in the sampling feedback adjustment loop, the sampled voltage value obtained by the sampling resistor in the sampling feedback loop also increases. The sampling voltage value of the input sampling terminal (R) is compared with the reference voltage inside the Zener diode (U2) chip through the Zener diode (U2). If the sampling voltage value is greater than the reference voltage, the voltage value output by the negative terminal (K) of the Zener diode (U2) decreases, causing the gate voltage of the N-channel MOS transistor (Q1) to decrease. Since the source-drain voltage (VDS) of the N-channel MOS transistor (Q1) = gate voltage - source (S) voltage, and since the source (S) voltage of the N-channel MOS transistor (Q1) is the output voltage, the source-drain voltage (VDS) of the N-channel MOS transistor (Q1) decreases, thereby increasing the source-drain voltage (VDS) of the N-channel MOS transistor (Q1). Furthermore, since Vin = Vds + Vout, when the source-drain voltage (VDS) of the N-channel MOS transistor (Q1) increases, the output voltage (Vout) decreases. Similarly, when the voltage of the input power supply (E1) decreases, the input voltage (Vin) decreases, which is the opposite of the voltage regulation process described above.

[0127] Based on the above embodiment, the voltage of the input power supply (E1), the voltage of the feedback circuit power supply (E2), and the output voltage in the present invention can refer to any DC voltage. The voltage regulator diode (U2) in the present invention is a 431 series integrated chip, such as TL431, KA431, AZ431, and all other 431 models. The bias resistor (R3), the first sampling resistor (R1), the second sampling resistor (R2), and the load resistor (R4) in the present invention include resistors of any specifications, parameters, models, packaging, power, material, and precision. The input filter capacitor (C1), the output filter capacitor (C3), and the feedback capacitor (C2) in the present invention include capacitors of any specifications, parameters, models, packaging, power, material, and precision. The N-channel MOS transistor (Q1) in the present invention includes an N-channel MOS transistor (Q1) of any specifications, parameters, models, packaging, and power. The error amplifier (U1) in the present invention includes an operational amplifier of any specifications and models.

[0128] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that those skilled in the art can make several improvements and modifications without departing from the principles of the present invention, and such improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A linear voltage stabilizing circuit, characterized in that: include: A first input circuit, a second input circuit, an adjustment circuit, an output circuit, a sampling circuit and a feedback circuit; The first input circuit is electrically connected to the voltage input terminal of the adjustment circuit and is used to supply power to the adjustment circuit; The second input circuit is electrically connected to the voltage input terminal of the feedback circuit and is used to supply power to the feedback circuit; The adjustment circuit is electrically connected to the output circuit, the output circuit is electrically connected to the sampling circuit, the sampling circuit is electrically connected to the feedback circuit, and the feedback circuit is electrically connected to the adjustment circuit to form a sampling feedback adjustment loop; wherein, The sampling circuit is used to collect the voltage value of the output circuit; The feedback circuit is used to compare the voltage difference between the voltage value and the reference voltage to obtain a feedback result; The adjustment circuit is used to adjust the output voltage of the output circuit according to the voltage value of the first input circuit input and the feedback result; The feedback circuit includes an error amplifier; The first input circuit includes an input power supply and an input filter capacitor; The second input circuit includes a power supply for the feedback circuit; The output circuit includes an output filter capacitor and a load resistor; The adjustment circuit includes an N-channel MOS tube; The sampling circuit includes a first sampling resistor and a second sampling resistor: The feedback circuit includes a bias resistor and a feedback capacitor; The positive end of the input power supply is electrically connected to the first pin of the input filter capacitor and the drain of the N-channel MOS tube, and the negative end of the input power supply is grounded; the first pin of the input filter capacitor is electrically connected to the drain of the N-channel MOS tube, and the second pin of the input filter capacitor is grounded; the source of the N-channel MOS tube is electrically connected to the first pin of the output filter capacitor, the first pin of the first sampling resistor and the first pin of the load resistor, and the gate of the N-channel MOS tube is electrically connected to the second pin of the bias resistor, the output end of the error amplifier and the first pin of the feedback capacitor; the first pin of the output filter capacitor is electrically connected to the first pin of the load resistor, the second pin of the output filter capacitor is grounded, and the second pin of the load resistor is grounded; The positive end of the feedback circuit power supply is electrically connected to the first pin of the bias resistor, and the negative end of the feedback circuit power supply is grounded; the second pin of the bias resistor is electrically connected to the gate of the N-channel MOS tube, the output end of the error amplifier, and the first pin of the feedback capacitor; The first pin of the feedback capacitor is electrically connected to the second pin of the bias resistor, the gate of the N-channel MOS tube, and the output end of the error amplifier; the second pin of the feedback capacitor is electrically connected to the second pin of the first sampling resistor, the first pin of the second sampling resistor, and the inverting input end of the error amplifier; The inverting input terminal of the error amplifier is electrically connected to the second pin of the first sampling resistor and the first pin of the second sampling resistor; the non-inverting input terminal of the error amplifier inputs a reference voltage; The first pin of the first sampling resistor is electrically connected to the source of the N-channel MOS tube, the first pin of the output filter capacitor, and the first pin of the load resistor; the second pin of the first sampling resistor is electrically connected to the first pin of the second sampling resistor; and the second pin of the second sampling resistor is grounded.

2. The linear voltage stabilizing circuit according to claim 1, characterized in that: The adjustment circuit is further configured to control the output voltage of the output circuit to decrease when the voltage value input by the first input circuit increases; The adjustment circuit is further used to control the output voltage of the output circuit to increase when the voltage value input by the first input circuit decreases.

3. The linear voltage stabilizing circuit according to claim 1, characterized in that: The step of adjusting the output voltage according to the input voltage value and the feedback result comprises the following steps: When the input voltage value increases, the output voltage is controlled to decrease; or, When the input voltage value decreases, the output voltage is controlled to increase.

4. A voltage adjustment method, characterized in that: The linear voltage regulator circuit applied to any one of claims 1 to 3 comprises: a first input circuit, a second input circuit, an adjustment circuit, an output circuit, a sampling circuit and a feedback circuit; the adjustment circuit, the output circuit, the sampling circuit and the feedback circuit are connected to form a sampling feedback loop; comprising the steps of: Get the input voltage value; collecting a voltage value of the output circuit; Comparing the voltage difference between the voltage value and a reference voltage to obtain a feedback result; The output voltage is adjusted according to the input voltage value and the feedback result.

5. A linear voltage stabilizing circuit, characterized in that: include: A first input circuit, a second input circuit, an adjustment circuit, an output circuit, a sampling circuit and a feedback circuit; The first input circuit is electrically connected to the voltage input terminal of the adjustment circuit and is used to supply power to the adjustment circuit; The second input circuit is electrically connected to the voltage input terminal of the feedback circuit and is used to supply power to the feedback circuit; The adjustment circuit is electrically connected to the output circuit, the output circuit is electrically connected to the sampling circuit, the sampling circuit is electrically connected to the feedback circuit, and the feedback circuit is electrically connected to the adjustment circuit to form a sampling feedback adjustment loop; wherein, The sampling circuit is used to collect the voltage value of the output circuit; The feedback circuit is used to compare the voltage difference between the voltage value and the reference voltage to obtain a feedback result; The adjustment circuit is used to adjust the output voltage of the output circuit according to the voltage value of the first input circuit input and the feedback result; The feedback circuit includes a voltage stabilizing diode; The first input circuit includes an input power supply and an input filter capacitor; The second input circuit includes a power supply for the feedback circuit; The output circuit includes an output filter capacitor and a load resistor; The adjustment circuit includes an N-channel MOS tube; The sampling circuit includes a first sampling resistor and a second sampling resistor: The feedback circuit includes a bias resistor and a feedback capacitor; The positive end of the input power supply is electrically connected to the first pin of the input filter capacitor and the drain of the N-channel MOS tube, and the negative end of the input power supply is grounded; the first pin of the input filter capacitor is electrically connected to the drain of the N-channel MOS tube, and the second pin of the input filter capacitor is grounded; the source of the N-channel MOS tube is electrically connected to the first pin of the output filter capacitor, the first pin of the first sampling resistor and the first pin of the load resistor, and the gate of the N-channel MOS tube is electrically connected to the second pin of the bias resistor, the negative end of the voltage regulator diode and the first pin of the feedback capacitor; the first pin of the output filter capacitor is electrically connected to the first pin of the load resistor, the second pin of the output filter capacitor is grounded, and the second pin of the load resistor is grounded; The positive end of the feedback circuit power supply is electrically connected to the first pin of the bias resistor, and the negative end of the feedback circuit power supply is grounded; the second pin of the bias resistor is electrically connected to the gate of the N-channel MOS tube, the negative end of the voltage regulator diode, and the first pin of the feedback capacitor; The first pin of the feedback capacitor is electrically connected to the second pin of the bias resistor, the gate of the N-channel MOS tube, and the negative end of the voltage regulator diode; the second pin of the feedback capacitor is electrically connected to the second pin of the first sampling resistor, the first pin of the second sampling resistor, and the sampling end of the voltage regulator diode; The sampling end of the voltage zener diode is electrically connected to the second pin of the feedback capacitor, the second pin of the first sampling resistor and the first pin of the second sampling resistor, and the positive end of the voltage zener diode is grounded; The first pin of the first sampling resistor is electrically connected to the source of the N-channel MOS tube, the first pin of the output filter capacitor, and the first pin of the load resistor; the second pin of the first sampling resistor is electrically connected to the first pin of the second sampling resistor; and the second pin of the second sampling resistor is grounded.

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