Storage device and data writing, reading, backup and recovery method thereof

Abstract

The present invention relates to a storage device, comprising: a host interface; a controller; a data buffer; a clock driver; a first storage area for storing data having an access frequency within a first access frequency range; and a second storage area for storing data having an access frequency within a second access frequency range. The access frequency within the first access frequency range is higher than the access frequency within the second access frequency range. The present invention also relates to a data writing, reading, backing up and restoring method.

Description

Technical Field

[0001] The present invention relates to the field of memory, and more particularly to a storage device and a method for writing, reading, backing up and restoring data thereof. Background Art

[0002] A non-volatile dual in-line memory module (NVDIMM) is a storage module that integrates dynamic random access memory (DRAM) and non-volatile memory (NVM). Usually, when the host / central processing unit (CPU) is abnormal or powered off, the NVDIMM will back up the data in the DRAM to the NVM; then, when the host is powered on again, the backed-up data in the NVM will be restored to the DRAM. Therefore, NVDIMM can avoid data loss when the host is abnormal or powered off, thereby improving the reliability of the host. NVDIMM is powered by a supercapacitor during data backup, but the power supply capacity of the supercapacitor is limited and has a large attenuation with the service time and the increase of operating temperature. For NVDIMM, the power consumption of data backup and the time of data backup / recovery are two important product performance indicators, which determine the capacity of the supercapacitor, the reliability of the system and the cost of the product. The increase in data backup power consumption will inevitably require an increase in supercapacitor capacity, but the increase in supercapacitor capacity will increase costs and reduce reliability; the time for data backup / recovery determines the power consumption and user experience during the data backup process. Currently, NVDIMM has different implementation methods, among which P-type NVDIMM (NVDIMM-P) greatly improves the utilization of NVM by configuring the NVM to be accessible by the host during normal operation, thereby enabling ultra-large capacity. However, the data backup and recovery mechanism of NVDIMM-P is not clear.

[0003] Figure 1 The signal flow and interface diagram of a NVDIMM-P in the prior art is shown, in which the data buffer (DB) connects the data (DQ) signal to the controller (Controller), and the controller then drives the command / address (CA) signal and the DQ signal to access the memory. However, Figure 1 The structure shown in the figure has the following problems: the driving capability of the data signal can be enhanced after passing through the data buffer, but after entering the controller, it is difficult to maintain and transmit the enhanced driving signal to the memory, and the accessible number and access rate of the storage module will be limited by the driving capability of the controller.

[0004] In addition, although the non-volatile memory in the NVDIMM-P can be read and written during normal operation, the non-volatile memory in the NVDIMM is generally read and written more slowly than DRAM. Summary of the invention

[0005] Embodiments of the present invention relate to a storage device, a writing method for writing data into the storage device, a reading method for reading data from the storage device, and a data backup method and a data recovery method for the storage device.

[0006] According to a first aspect of the present invention, there is provided a storage device, wherein the storage device comprises:

[0007] Host interface;

[0008] Controller;

[0009] Data buffer;

[0010] Clock driver;

[0011] a first storage area for storing data having an access frequency within a first access frequency range; and

[0012] a second storage area for storing data having an access frequency within a second access frequency range;

[0013] The access frequency within the first access frequency range is higher than the access frequency within the second access frequency range.

[0014] According to a second aspect of the present invention, there is provided a method for writing data into a storage device, wherein the storage device comprises a first storage area and a second storage area;

[0015] Wherein, the writing method includes:

[0016] storing data having an access frequency within a first access frequency range in the first storage area; and

[0017] storing data having an access frequency within a second access frequency range in the second storage area;

[0018] The access frequency within the first access frequency range is higher than the access frequency within the second access frequency range.

[0019] According to a third aspect of the present invention, there is provided a method for writing data into a storage device, wherein the storage device comprises a controller, a data buffer, a first storage area and a second storage area, and the writing method comprises:

[0020] In response to receiving a first command and address signal including a write command and a write address associated with the write command being at the second storage area, writing data into the first storage area;

[0021] reading the data written into the first storage area into the controller; and

[0022] Data is written into different sub-storage areas of the second storage area according to the access frequency of the data read from the controller.

[0023] According to a fourth aspect of the present invention, a method for reading data from a storage device is provided, wherein the storage device comprises a first storage area and a second storage area, and the reading method comprises reading data in the second storage area via the first storage area.

[0024] According to a fifth aspect of the present invention, there is provided a data backup method for a storage device, wherein the storage device comprises a controller, a first storage area and a second storage area, the second storage area comprises a first sub-storage area, a second sub-storage area and a third sub-storage area;

[0025] Wherein, the data backup method comprises:

[0026] Receiving data to be backed up and storing the data to be backed up in the first storage area and the first sub-storage area and the second sub-storage area;

[0027] In response to receiving a data backup signal, reading the data in the first storage area to the controller, and storing the data in the first sub-storage area and the second sub-storage area to the third sub-storage area; and

[0028] The data read from the first storage area to the controller is stored in the third sub-storage area.

[0029] According to a sixth aspect of the present invention, there is provided a data recovery method for a storage device, wherein the storage device comprises a first storage area and a second storage area, the second storage area comprises a first sub-storage area, a second sub-storage area and a third sub-storage area;

[0030] The data recovery method includes, in response to receiving a restore data command, restoring the data in the first storage area stored during data backup from the third sub-storage area to the first storage area.

[0031] Those skilled in the art should understand that the second to sixth aspects of the present invention can achieve the technical effects described in relation to the first aspect of the present invention. The storage device of the present invention and the data writing, reading, backing up and restoring method thereof can improve the rate performance and reliability of the system and reduce the data backup time and the requirements for the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Further details, aspects and embodiments of the invention will be described by way of example only with reference to the accompanying drawings. The elements in the drawings are illustrated for the sake of simplicity and clarity and are not necessarily drawn to scale.

[0033] Figure 1 It is a signal flow and interface diagram of an NVDIMM-P of the prior art;

[0034] Figure 2 is a memory space distribution diagram in an NVDIMM-P according to an embodiment of the present invention.

[0035] Figure 3 is an exemplary block diagram of an NVDIMM-P according to one embodiment of the present invention. DETAILED DESCRIPTION

[0036] Although the present invention may be implemented in many different forms, one or more specific embodiments are shown in the drawings and will be described in detail herein; it should be understood that the present disclosure should be considered as an illustration of the principles of the present invention and is not intended to limit the present invention to the specific embodiments shown and described. Therefore, processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the present invention may not be described.

[0037] It will be understood that although the terms "first", "second", "third" etc. may be used in the present disclosure to describe various elements, components, signals and / or frequencies, these elements, components, signals and / or frequency ranges should not be limited by these terms. These terms are used to distinguish an element, component, signal or frequency range from another element, component, signal or frequency range. Therefore, without departing from the spirit and scope of the present invention, the first element, component, signal or frequency range described below may be referred to as a second element, component, signal or frequency range.

[0038] The terms used in this disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in this disclosure, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It will also be understood that when the terms "comprise" and "comprising" are used in this specification, the features, wholes, steps, operations, elements and / or combinations thereof described are indicated, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof are not excluded.

[0039] Embodiments of the present invention relate to storage devices for storing data and methods for writing, reading, backing up, and restoring data thereof. For example, the storage device in embodiments of the present invention may be a non-volatile dual in-line memory module (NVDIMM) device, such as a P-type NVDIMM (NVDIMM-P) device.

[0040] According to a first aspect of the present invention, a storage device is provided, wherein the storage device includes: a host interface; a controller; a data buffer; a clock driver; a first storage area for storing data having an access frequency within a first access frequency range; and a second storage area for storing data having an access frequency within a second access frequency range; wherein the access frequency within the first access frequency range is higher than the access frequency within the second access frequency range.

[0041] According to a preferred embodiment of the first aspect of the present invention, the first storage area includes a plurality of volatile memories.

[0042] According to a preferred embodiment of the first aspect of the present invention, there are multiple data buffers, which are connected to the multiple volatile memories and the data channels of the host interface in a one-to-one correspondence. Since the data buffer is directly connected to the volatile memory (such as random access memory (RAM), for example, dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), static random access memory (SRAM), etc.), the host can access the volatile memory through the data channel and the data buffer, making full use of the driving capability of the data buffer. Therefore, compared with the solution of driving the volatile memory through the controller, the storage device of the embodiment of the present invention can drive more volatile memory modules, increase the storage space of the storage device, and increase the access rate to the volatile memory.

[0043] According to a preferred embodiment of the first aspect of the present invention, the data buffer is connected to the controller via a local data bus.

[0044] According to a preferred embodiment of the first aspect of the present invention, the controller is connected to the command and address channels of the host interface.

[0045] According to a preferred embodiment of the first aspect of the present invention, the controller is connected to the clock driver via a command and data bus and a local command bus respectively.

[0046] According to a preferred embodiment of the first aspect of the present invention, the clock driver is connected to the first storage area and the data buffer respectively.

[0047] According to a preferred embodiment of the first aspect of the present invention, the clock driver is connected to the data buffer via a data buffer command bus to configure the data buffer.

[0048] According to a preferred embodiment of the first aspect of the present invention, the second storage area includes multiple sub-storage areas, the second access frequency range contains multiple sub-access frequency ranges, and the multiple sub-storage areas are respectively used to store data with access frequencies within different sub-access frequency ranges.

[0049] According to a preferred embodiment of the first aspect of the present invention, the second storage area comprises a first sub-storage area, a second sub-storage area and a third sub-storage area;

[0050] The second access frequency range includes a first sub-access frequency range, a second sub-access frequency range and a third sub-access frequency range from high to low access frequencies;

[0051] Among them, the first sub-storage area is used to store data with an access frequency within the first sub-access frequency range, the second sub-storage area is used to store data with an access frequency within the second sub-access frequency range, and the third sub-storage area is used to store data with an access frequency within the third sub-access frequency range.

[0052] According to a preferred embodiment of the first aspect of the present invention, the first sub-storage area is located in the controller.

[0053] According to a preferred embodiment of the first aspect of the present invention, the first sub-storage area is a cache memory, preferably a static random access memory.

[0054] According to a preferred embodiment of the first aspect of the present invention, the second sub-storage area is a local dynamic random access memory.

[0055] According to a preferred embodiment of the first aspect of the present invention, the third sub-storage area is a non-volatile memory. Preferably, the non-volatile memory is Flash, phase change memory or resistive memory.

[0056] According to a preferred embodiment of the first aspect of the present invention, the controller is connected to the second sub-storage area and the third sub-storage area respectively.

[0057] When writing data, the host will divide the data into frequently accessed data (hot data) and infrequently accessed data (cold data) through the drive thereon, and write the "hot data" to the address space of the volatile memory and write the "cold data" to the address space of the cold data storage area. As described above, non-volatile memory has some disadvantages relative to volatile memory. In order to reduce these disadvantages, the storage device of the embodiment of the present invention writes the data with a relatively high access frequency in the "cold data" into the buffer memory (such as SRAM, local DRAM, etc.) of the storage device, and writes the data with a relatively low access frequency in the "cold data" into the non-volatile memory. In this way, the rate performance of the storage device is further improved, and frequent access to the non-volatile memory is avoided. According to the embodiment of the present invention, according to the accessible speed of each buffer memory in the storage device, the data with a higher access frequency is stored in the buffer memory with a higher accessible speed, so that the rate performance of the storage device is optimized.

[0058] According to a preferred embodiment of the first aspect of the present invention, data having an access frequency within the second access frequency range is stored in the second storage area via the first storage area.

[0059] According to a preferred embodiment of the first aspect of the present invention, the controller is configured to: write data on the data channel of the host interface to the first storage area in response to receiving a first command and address signal containing a write command and the write address associated with the write command is on the second storage area; read the data written to the first storage area to the controller; and write the data to different sub-storage areas of the second storage area according to the access frequency of the data read to the controller.

[0060] Therefore, during normal operation, the host can write data to a non-volatile memory such as Flash (e.g., NAND Flash), phase-change memory (PCM, such as X-Point) or resistive random access memory (RRAM) through the host interface, thereby increasing the storage space of the storage device.

[0061] According to a preferred embodiment of the first aspect of the present invention, the controller receives the first command and address signals from a command and address channel of the host interface.

[0062] According to a preferred embodiment of the first aspect of the present invention, the first storage area includes a plurality of volatile memories; the controller is configured to:

[0063] encoding the write address so that the encoded write address is on the first storage area, and obtaining an encoded first command and address signal;

[0064] sending the encoded first command and address signal to the clock driver via a command and data bus between the controller and the clock driver; and

[0065] The clock driver is configured to forward the encoded first command and address signals to the plurality of volatile memories to write data on the data channel to the encoded write addresses of the plurality of volatile memories.

[0066] According to a preferred embodiment of the first aspect of the present invention, the data buffer is connected to the controller via a local data bus;

[0067] The controller is configured to send a second command and address signal including a read command and the encoded write address to the clock driver via a local command bus after writing the data on the data channel to the encoded write address; and

[0068] The clock driver is configured to, in response to receiving the second command and address signal, configure the data buffer and forward the second command and address signal to the plurality of volatile memories to read the data in the encoded write address to the controller via the data buffer and the local data bus.

[0069] In an embodiment of the present invention, since the clock driver is arranged at the back end of the controller (such as a non-volatile controller (NVC)), the controller directly receives the command and address signals sent by the host, and can encode the addresses in the command and address signals so that the address for accessing the non-volatile memory is on the volatile memory, so that the volatile memory can act as a buffer for the non-volatile memory. In addition, by means of controller caching, the rate difference between the volatile memory and the non-volatile memory is balanced, so that the host can stably access the non-volatile memory with a lower overhead.

[0070] According to a preferred embodiment of the first aspect of the present invention, the data in the second storage area is read out via the first storage area.

[0071] According to a preferred embodiment of the first aspect of the present invention, the controller is configured to:

[0072] In response to receiving a third command and address signal including an internal write command, and an access address associated with the internal write command being on the second storage area, reading data from an actual storage address corresponding to the access address in a data write phase;

[0073] writing the read data from the controller into the first storage area; and

[0074] In response to receiving a fourth command and address signal including a read command and a read address associated with the read command being the same as the access address, the data is read out from the first storage area.

[0075] Therefore, during normal operation, the host can read the data in the non-volatile memory through the host interface.

[0076] According to a preferred embodiment of the first aspect of the present invention, the controller receives the third command and address signal and the fourth command and address signal from a command and address channel of the host interface.

[0077] According to a preferred embodiment of the first aspect of the present invention, the first storage area includes a plurality of volatile memories, and the data buffer is connected to the controller via a local data bus;

[0078] The controller is configured to send a fifth command and address signal to the clock driver via a local command bus, the fifth command and address signal including a write command and a write address on the plurality of volatile memories;

[0079] the clock driver being configured to, in response to receiving the fifth command and address signal, configure the data buffer and forward the fifth command and address signal to the plurality of volatile memories; and

[0080] The controller is further configured to write the data read from the actual storage address to the write address via the local data bus and the data buffer.

[0081] According to a preferred embodiment of the first aspect of the present invention, the controller is configured to: encode the read address so that the encoded read address is the same as the write address, and obtain an encoded fourth command and address signal; and send the encoded fourth command and address signal to the clock driver via a command and address bus between the controller and the clock driver; and

[0082] The clock driver is configured to, in response to receiving the encoded fourth command and address signal, configure the data buffer and forward the encoded fourth command and address signal to the plurality of volatile memories to read out the data in the write address via the data channel.

[0083] In the embodiment of the present invention, since the clock driver is arranged at the back end of the controller, the controller directly receives the command and address signal sent by the host, and first writes the data in the non-volatile memory to the volatile memory, and uses the volatile memory as the buffer of the non-volatile memory. In addition, the rate difference between the volatile memory and the non-volatile memory is balanced by the controller cache, so that the host can stably access the non-volatile memory with a lower overhead.

[0084] According to a preferred embodiment of the first aspect of the present invention, the storage device is configured to receive data to be backed up and store the data to be backed up in the first storage area and the first sub-storage area and the second sub-storage area;

[0085] The controller is configured to:

[0086] In response to receiving a data backup signal, reading the data in the first storage area to the controller, and storing the data in the first sub-storage area and the second sub-storage area to the third sub-storage area; and

[0087] The data read from the first storage area to the controller is stored in the nonvolatile memory.

[0088] When the host is abnormal or powered off, the host will refresh the data in its cache to the storage device. The storage device according to the embodiment of the present invention can back up the data to the non-volatile memory when the host is abnormal or powered off.

[0089] According to a preferred embodiment of the first aspect of the present invention, the first storage area includes a plurality of volatile memories, and the data buffer is connected to the controller via a local data bus;

[0090] The controller is configured to, in response to receiving the data backup signal, send a sixth command and address signal including a backup command and a backup address to the clock driver via a local command bus;

[0091] The clock driver is configured to, in response to receiving the sixth command and address signal, configure the data buffer and forward the sixth command and address signal to the plurality of volatile memories to read data in the plurality of volatile memories to the controller via the data buffer and the local data bus.

[0092] The storage device of the present invention reads data in the volatile memory while backing up data in the cache memory of the storage device to the non-volatile memory at the same time, thereby improving the data backup speed and further reducing the requirements for the supercapacitor.

[0093] According to a preferred embodiment of the first aspect of the present invention, the controller comprises a processing unit and is configured to, in response to receiving the data backup signal, sequentially perform the following steps during reading the data in the plurality of volatile memories into the controller:

[0094] -storing the data in the space of the first sub-storage area occupied by the processing unit into the second sub-storage area;

[0095] -storing data in the space of the first sub-storage area not occupied by the processing unit into the third sub-storage area; and

[0096] -Storing the data in the second sub-storage area into the third sub-storage area.

[0097] According to a preferred embodiment of the first aspect of the present invention, which also includes an emergency power supply interface for connecting a backup power supply, the controller is configured to switch the storage device to power supply through the emergency power supply interface in response to receiving the data backup signal. Optionally or alternatively, a backup power supply may be provided in the storage device to supply power when the host is abnormal or loses power. In addition, those skilled in the art should understand that the backup power supply may be a battery, a capacitor (preferably a supercapacitor) and / or any other suitable mechanism and / or device for power storage.

[0098] According to a preferred embodiment of the first aspect of the present invention, the controller is configured to perform power-off of the storage device after storing the data read from the first storage area into the third sub-storage area.

[0099] According to a preferred embodiment of the first aspect of the present invention, the storage device is configured to, in response to receiving a restore data command, restore the data in the first storage area stored during data backup from the third sub-storage area to the first storage area.

[0100] According to a preferred embodiment of the first aspect of the present invention, the controller is configured to, in response to receiving the restore data command, send the restore data command to the clock driver, while reading data in the first storage area stored during data backup from the third sub-storage area;

[0101] The clock driver is configured to, in response to receiving the resume data command, configure the data buffer and forward the resume data command to the first storage area; and

[0102] The controller is further configured to write back the data read from the third sub-storage area to the first storage area after the clock driver configures the data buffer and forwards the restore data command to the first storage area.

[0103] Therefore, the storage device of the present invention can read the data backed up in the non-volatile memory into the volatile memory when the host is abnormal or powered off, so that the data can be read and used by the host.

[0104] According to a preferred embodiment of the first aspect of the present invention, the controller is configured to receive the restore data command via the system management bus of the host interface, send the restore data command to the clock driver via the local command bus, and write back the data read from the third sub-storage area to the first storage area via the local data bus and the data buffer.

[0105] According to a second aspect of the present invention, there is provided a method for writing data into a storage device, wherein the storage device comprises a first storage area and a second storage area; wherein the writing method comprises:

[0106] storing data having an access frequency within a first access frequency range in the first storage area; and

[0107] storing data having an access frequency within a second access frequency range in the second storage area;

[0108] The access frequency within the first access frequency range is higher than the access frequency within the second access frequency range.

[0109] According to a preferred embodiment of the second aspect of the present invention, the writing method comprises: storing data having an access frequency within the second access frequency range into the second storage area via the first storage area.

[0110] According to a preferred embodiment of the second aspect of the present invention, the first storage area includes a plurality of volatile memories.

[0111] According to a preferred embodiment of the second aspect of the present invention, the second storage area includes a plurality of sub-storage areas; wherein the writing method includes:

[0112] dividing the second access frequency range into a plurality of sub-access frequency ranges; and

[0113] Data having access frequencies within different sub-access frequencies are respectively stored in corresponding sub-storage areas among the plurality of sub-storage areas.

[0114] According to a preferred embodiment of the second aspect of the present invention, the second storage area includes a first sub-storage area, a second sub-storage area and a third sub-storage area; wherein the writing method includes:

[0115] Dividing the second access frequency range into a first sub-access frequency range, a second sub-access frequency range and a third sub-access frequency range from high to low access frequencies;

[0116] storing data having an access frequency within the first sub-access frequency range in the first sub-storage area;

[0117] storing data having an access frequency within the second sub-access frequency range in the second sub-storage area; and

[0118] Data having an access frequency within the third sub-access frequency range is stored in the third sub-storage area.

[0119] According to a preferred embodiment of the second aspect of the present invention, the storage device comprises a controller, and the first sub-storage area is located in the controller.

[0120] According to a preferred embodiment of the second aspect of the present invention, the first sub-storage area is a cache memory, preferably a static random access memory.

[0121] According to a preferred embodiment of the second aspect of the present invention, the second sub-storage area is a local dynamic random access memory.

[0122] According to a preferred embodiment of the second aspect of the present invention, the third sub-storage area is a non-volatile memory. Preferably, the non-volatile memory is Flash, phase change memory or resistive memory.

[0123] According to a third aspect of the present invention, there is provided a method for writing data into a storage device, wherein the storage device comprises a controller, a data buffer, a first storage area and a second storage area, and the writing method comprises:

[0124] In response to receiving a first command and address signal including a write command and a write address associated with the write command being at the second storage area, writing data into the first storage area;

[0125] reading the data written into the first storage area into the controller; and

[0126] Data is written into different sub-storage areas of the second storage area according to the access frequency of the data read from the controller.

[0127] According to a preferred embodiment of the third aspect of the present invention, wherein the first storage area includes a plurality of volatile memories, the storage device further includes a clock driver, and the writing method includes:

[0128] encoding the write address so that the encoded write address is on the plurality of volatile memories and obtaining an encoded first command and address signal;

[0129] sending the encoded first command and address signals to the clock driver; and

[0130] The encoded first command and address signals are forwarded to the plurality of volatile memories to write the data to the encoded write addresses of the plurality of volatile memories.

[0131] According to a preferred embodiment of the third aspect of the present invention, wherein the data buffer is connected to the plurality of volatile memories and connected to the controller via a local data bus, the writing method comprises:

[0132] After writing the data to the encoded write address, sending a second command and address signal including a read command and the encoded write address to the clock driver;

[0133] configuring the data buffer and forwarding the second command and address signals to the plurality of volatile memories; and

[0134] The data in the encoded write address is read to the controller via the data buffer and the local data bus.

[0135] According to a preferred embodiment of the third aspect of the present invention, the writing method comprises:

[0136] storing data having an access frequency within a first access frequency range in the first storage area; and

[0137] storing data having an access frequency within a second access frequency range in the second storage area;

[0138] The access frequency within the first access frequency range is higher than the access frequency within the second access frequency range.

[0139] According to a preferred embodiment of the third aspect of the present invention, the second storage area includes a first sub-storage area, a second sub-storage area and a third sub-storage area; wherein the writing method includes:

[0140] Dividing the second access frequency range into a first sub-access frequency range, a second sub-access frequency range and a third sub-access frequency range from high to low access frequencies;

[0141] storing data having an access frequency within the first sub-access frequency range in the first sub-storage area;

[0142] storing data having an access frequency within the second sub-access frequency range in the second sub-storage area; and

[0143] Data having an access frequency within the third sub-access frequency range is stored in the third sub-storage area.

[0144] According to a fourth aspect of the present invention, a method for reading data from a storage device is provided, wherein the storage device comprises a first storage area and a second storage area, and the reading method comprises reading data in the second storage area via the first storage area.

[0145] According to a preferred embodiment of the fourth aspect of the present invention, wherein the storage device comprises a controller, the reading method comprises:

[0146] In response to receiving a third command and address signal including an internal write command, and an access address associated with the internal write command being on the second storage area, reading data from an actual storage address corresponding to the access address in a data write phase;

[0147] writing the data from the controller into the first storage area; and

[0148] In response to receiving a fourth command and address signal including a read command and a read address associated with the read command being the same as the access address, the data is read out from the first storage area.

[0149] According to a preferred embodiment of the fourth aspect of the present invention, the storage device includes a data buffer, the first storage area includes a plurality of volatile memories, and the reading method includes:

[0150] sending a fifth command and address signal to the clock driver, the fifth command and address signal including a write command and a write address on the plurality of volatile memories;

[0151] configuring the data buffer and forwarding the fifth command and address signals to the plurality of volatile memories; and

[0152] The data is written to write addresses on the plurality of volatile memories.

[0153] According to a preferred embodiment of the fourth aspect of the present invention, the reading method comprises:

[0154] encoding the read address so that the encoded read address is the same as the write address, and obtaining an encoded fourth command and address signal;

[0155] sending the encoded fourth command and address signal to the clock driver;

[0156] configuring the data buffer and forwarding the encoded fourth command and address signals to the plurality of volatile memories; and

[0157] The data is read out from the write addresses of the plurality of volatile memories.

[0158] According to a fifth aspect of the present invention, a data backup method of a storage device is provided, wherein the storage device comprises a controller, a first storage area and a second storage area, the second storage area comprises a first sub-storage area, a second sub-storage area and a third sub-storage area; wherein the data backup method comprises:

[0159] Receiving data to be backed up and storing the data to be backed up in the first storage area and the first sub-storage area and the second sub-storage area;

[0160] In response to receiving a data backup signal, reading the data in the first storage area to the controller, and storing the data in the first sub-storage area and the second sub-storage area to the third sub-storage area; and

[0161] The data read from the first storage area to the controller is stored in the third sub-storage area.

[0162] According to a preferred embodiment of the fifth aspect of the present invention, the storage device includes a clock driver and a data buffer, and the first storage area includes a plurality of volatile memories; wherein the data backup method includes:

[0163] In response to receiving the data backup signal, sending a sixth command and address signal including a backup command and a backup address to the clock driver;

[0164] configuring the data buffer and forwarding the sixth command and address signals to the plurality of volatile memories; and

[0165] The data in the plurality of volatile memories are read to the controller.

[0166] According to a preferred embodiment of the fifth aspect of the present invention, wherein the controller includes a processing unit, the data backup method includes:

[0167] The following steps are performed sequentially during the process of reading the data in the plurality of volatile memories into the controller:

[0168] -storing the data in the space of the first sub-storage area occupied by the processing unit into the second sub-storage area;

[0169] -storing data in the space of the first sub-storage area not occupied by the processing unit into the third sub-storage area; and

[0170] -Storing the data in the second sub-storage area into the third sub-storage area.

[0171] According to a preferred embodiment of the fifth aspect of the present invention, the storage device includes an emergency power supply interface for connecting a backup power supply, and the backup power supply is preferably a supercapacitor; wherein the data backup method includes: in response to receiving the data backup signal, switching the storage device to be powered by the emergency power supply interface.

[0172] According to a preferred embodiment of the fifth aspect of the present invention, the data backup method comprises: after storing the data read from the first storage area into the third sub-storage area, powering off the storage device.

[0173] According to a sixth aspect of the present invention, there is provided a data recovery method for a storage device, wherein the storage device comprises a first storage area and a second storage area, the second storage area comprises a first sub-storage area, a second sub-storage area and a third sub-storage area;

[0174] The data recovery method includes, in response to receiving a restore data command, restoring the data in the first storage area stored during data backup from the third sub-storage area to the first storage area.

[0175] According to a preferred embodiment of the sixth aspect of the present invention, wherein the storage device comprises a clock driver and a data buffer, the data recovery method comprises:

[0176] sending the restore data command to the clock driver, and simultaneously reading the data in the first storage area stored during the data backup period from the third sub-storage area;

[0177] configuring the data buffer and forwarding the restore data command to the first storage area; and

[0178] The data read from the third sub-storage area is written back to the first storage area.

[0179] According to a preferred embodiment of the sixth aspect of the present invention, wherein the storage device comprises a host interface, the data recovery method comprises:

[0180] receiving the restore data command via a system management bus of the host interface;

[0181] sending the recover data command to the clock driver via a local command bus; and

[0182] The data read from the third sub-storage area is written back to the first storage area via a local data bus and the data buffer.

[0183] The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0184] Figure 2 is a memory space distribution diagram in NVDIMM-P according to an embodiment of the present invention. Figure 2 As shown in FIG. 1 , the memory space of the non-volatile dual in-line memory module NVDIMM 20 generally includes a first storage area (“hot area”) 21 and a second storage area (“cold area”) 22 .

[0185] In the embodiments of the present invention, "hot area" refers to an area where the host or central processing unit frequently reads and writes (i.e., storing data frequently accessed by the host or central processing unit), and "cold area" refers to an area where the host or central processing unit does not frequently read and write (i.e., storing data not frequently accessed by the host or central processing unit). Here, whether to read and write frequently is defined according to specific circumstances.

[0186] According to the access frequency of the host or the central processing unit, the second storage area ("cold area") 22 is divided into a first sub-storage area 221, a second sub-storage area 222...the nth sub-storage area 22n. The host or the central processing unit has different read and write frequencies for these sub-storage areas 221, 222...22n, that is, these sub-storage areas store data with host access frequencies in different access frequency ranges.

[0187] Figure 3 FIG. 1 is an exemplary block diagram of an NVDIMM-P according to one embodiment of the present invention. Figure 3 As shown, the non-volatile dual in-line memory module NVDIMM300 of this embodiment includes multiple dynamic random access memories DRAM 301, NAND Flash 302, local DRAM 303, controller 304, clock driver RCD 305 and multiple data buffers DB306. The controller 304 is connected to the NAND Flash 302 and the local DRAM 303, connected to the clock driver 305 through the local command bus LCOM and the command and address bus CA2, and connected to the multiple data buffers 306 through the local data bus LDQ. The clock driver 305 is connected to the multiple dynamic random access memories 301, and configures the data buffers 306 through the data buffer command bus BCOM. The NVDIMM 300 also includes a host interface, through which the NVDIMM 300 is connected to the host or the central processing unit, and the host interface includes a command and address pin CA1, a SAVE_n pin, a system management bus pin SMBus, and a data pin DQ.

[0188] In addition, the plurality of data buffers 306 are connected to the plurality of dynamic random access memories 301 and the DQ pins in a one-to-one correspondence. Figure 1 Compared with the technical solution in the embodiment of the present invention, the host can directly access the dynamic random access memory 301 through the data buffer 306, rather than accessing the dynamic random access memory through the controller. In this way, the driving capability of the data buffer 306 is fully utilized, the access speed of the storage module is increased, and the storage module can be configured with more dynamic random access memories 301.

[0189] In an embodiment of the present invention, the dynamic random access memory is ultimately used to store "hot data", and the non-volatile memory is ultimately used to store "cold data". In the present invention, "hot data" refers to data frequently accessed by the host or the central processing unit, and "cold data" refers to data infrequently accessed by the host or the central processing unit. As described above, the dynamic random access memory belongs to the "hot zone" and the non-volatile memory belongs to the "cold zone". When writing data, the driver on the host will distinguish between "hot data" (having an access frequency within the first access frequency range) and "cold data" (having an access frequency within the second access frequency range), and the driver also knows the address space of the dynamic random access memory and the non-volatile memory on the storage module. It should be understood that in the present invention, the non-volatile memory can be Flash (e.g., NAND Flash), phase-change memory (PCM, such as X-Point) or resistive random access memory (RRAM), etc.

[0190] exist Figure 3 In the NVDIMM 300, the host can access the dynamic random access memory 301 and the NAND Flash 302 in the "cold area" during normal operation, thereby increasing the memory space of the system. Therefore, in the embodiment of the present invention, the NVDIMM 300 implements the function of the P-type NVDIMM (NVDIMM-P).

[0191] The following further describes the process of the host writing "cold data" to the "cold area" of the storage device of the present invention and reading "cold data" from the "cold area" of the storage device of the present invention (i.e., the host writes "cold data" and reads "cold data"). Figure 3 The structure of NVDIMM 300.

[0192] The host writes "cold data" in two steps:

[0193] The first step is to write cold data from the "host" to the "dynamic random access memory":

[0194] When the drive on the host determines that the data to be stored on the NVDIMM 300 is "cold data", the host sends the "cold data" and the write command and the write address of the cold data to the NVDIMM 300 through the host interface of the NVDIMM 300 (that is, the host sends the cold data and its command and address signals). The controller 304 receives the command and address signal through the command and address pin CA1, and re-encodes the command and address signal to obtain an encoded command and address signal, wherein the write address in the encoded command and address signal (that is, the encoded write address) falls on the dynamic random access memory 301. Then, the controller 304 sends the encoded command and address signal to the clock driver 305 through the command and address bus CA2 between the controller 304 and the clock driver 305. The clock driver 305 configures the data buffer 306 in response to the encoded command and address signals and sends the encoded command and address signals to the dynamic random access memory 301 so that the host has operational control over the dynamic random access memory 301, thereby the host can write the "cold data" from the host to one or more of the multiple dynamic random access memories 301.

[0195] The second step is to write the cold data from the "dynamic random access memory" into the "cold data storage area" (i.e., the "cold area" 22):

[0196] The controller 304 sends a command and address signal to the clock driver 305 via the local command bus LCOM, and the command and address signal include a read command and address (the address of the “cold data” in the dynamic random access memory 301). The clock driver 305 configures the data buffer 306 via the data buffer command bus BCOM and sends the command and address signal to the dynamic random access memory 301, so that the operation control of the dynamic random access memory 301 is switched to the controller 304. Thus, the controller 304 can read the “cold data” in the dynamic random access memory 301 into the cache space in the controller 304 via the data buffer 306 and the local data bus LDQ.

[0197] It can be seen that the dynamic random access memory 301 plays the role of caching data.

[0198] In the embodiment of the present invention, each of the plurality of dynamic random access memories 301 reserves a buffer area with a fixed space size for caching cold data. Preferably, the space size of each of these buffer areas is greater than 64KB. When opening up the space size of these buffer areas, factors to be considered include the rate at which the host accesses the dynamic random access memory, the rate at which the controller accesses the dynamic random access memory, and the rate at which the controller accesses the non-volatile memory.

[0199] In the embodiment of the present invention, the controller 304 has a high-speed cache memory (such as SRAM) and a processing unit. Here, the high-speed cache memory of the controller 304 is the cache space in the controller 304 mentioned above.

[0200] It should be noted that in the embodiments of the present invention, if an abnormality such as power failure occurs, the "cold data" is ultimately stored in the non-volatile memory of the storage device (i.e. Figure 3 On the contrary, if there is no abnormality such as power failure, the "cold data" does not need to be stored in the non-volatile memory of the storage device.

[0201] In order to further improve the speed performance of the storage module and avoid frequent access to the non-volatile memory, thereby avoiding damage to the non-volatile memory, in an embodiment of the present invention, the controller 304 will write these "cold data" into the cache memory of the controller 304, the local DRAM 303 or the NAND Flash 302 in sequence according to the cache algorithm.

[0202] The overall idea of ​​the cache algorithm is: divide the cold data storage area of ​​the storage device into different sub-storage areas; store the "cold data" in different sub-storage areas according to the access frequency belonging to different sub-access frequency ranges.

[0203] More specifically, the second access frequency range includes a first sub-range, a second sub-range, and a third sub-range with access frequencies from high to low; "cold data" with an access frequency within the first sub-range is cached in a cache memory (such as SRAM) of the controller 304, "cold data" with an access frequency within the second sub-range is cached in the local DRAM 303, and "cold data" with an access frequency within the third range (i.e., the relatively lowest access frequency) is stored in the NAND Flash 302.

[0204] When writing "cold data", a mapping table is allocated in the controller 304 to match the write address of the "cold data" input by the host with the actual storage address of the "cold data" one by one.

[0205] The host reads "cold data" from the "cold zone" in two steps:

[0206] The first step is to read the cold data from the "cold area" into the "dynamic random access memory":

[0207] When the host needs to read "cold data" from the "cold area", the host first sends an internal write command and the theoretical storage address of the "cold data" to the NVDIMM 300 (that is, the host sends a command and address signal to write the "cold data" to the DRAM). The theoretical storage address is the address that the host wants to write and read. Specifically, the controller 304 receives the command and address signal via the command and address pin CA1, and obtains the actual storage address in the NAND Flash 302, local DRAM 303 or SRAM of the controller 304 corresponding to the theoretical storage address of the "cold data" according to the mapping table stored in the write phase, thereby reading the "cold data" in the actual storage address to the controller 304. After reading out these "cold data", the controller 304 sends a command and address signal to the clock driver 305 via the local command bus LCOM. The command and address signals internally write the command and the address on the dynamic random access memory 301. The clock driver 305 configures the data buffer 306 via the data buffer command bus BCOM and sends the command and address signal to the dynamic random access memory 301, so that the controller 304 has the operation control right of the dynamic random access memory 301. Thus, the controller 304 can store the "cold data" in the dynamic random access memory 301 via the local data bus LDQ and the data buffer 306.

[0208] The second step is to read the cold data from the "dynamic random access memory" to the "host":

[0209] After storing these "cold data" in the dynamic random access memory 301, the host will send a read command and the theoretical storage address of the "cold data" (i.e., a command and address signal for reading the "cold data"). The controller 304 receives the command and address signal via the command and address pin CA1, and re-encodes the theoretical storage address of the "cold data" to obtain an encoded command and address signal, wherein the encoded read address falls on the address where the dynamic random access memory 301 stores the "cold data". Then, the controller 304 sends the encoded command and address signal to the clock driver 305 via the command and address bus CA2 between the controller 304 and the clock driver 305. In response to the encoded command and address signal, the clock driver 305 configures the data buffer 306 and sends the encoded command and address signal to the dynamic random access memory 301, so that the host has the operation control right of the dynamic random access memory 301, thereby, the host can read the above-mentioned "cold data".

[0210] The non-volatile dual in-line memory module can back up the data stored in the host to the non-volatile memory in the memory module when the host is abnormal or powered off, thereby achieving non-volatility. In a system equipped with a non-volatile dual in-line memory module, after the system is powered on, the host can obtain information about whether the power was off abnormally last time: if the last time was a normal shutdown, the host starts normally; otherwise, the host enters a data recovery state. The following further describes the process of backing up data to NVDIMM 300 and restoring data from NVDIMM 300 when the host is powered off abnormally. Figure 3 The structure of NVDIMM 300.

[0211] When the host's baseboard management controller (BMC) or a module with similar functions detects an AC power drop, the host ADR refreshes the cached data to the dynamic random access memory DRAM 301 or the buffer memory of the non-volatile dual in-line memory module (such as the SRAM of the controller 304, the local DRAM 303, etc.). Then, the host pulls the SAVE_n pin low and then high to notify the non-volatile dual in-line memory module to perform data backup. After receiving the data backup signal, the controller 304 switches the NVDIMM 300 to be powered by the supercapacitor 400 connected to it. Then, the controller 304 sends a command and address signal to back up the data in the DRAM 301 to the clock driver 305 via the local command bus LCOM, and the command and address signal include the address of the data in the DRAM 301 to be stored in the NAND Flash 302. In response to the command and address signal, the clock driver 305 configures the data buffer 306 via the data buffer command bus BCOM and sends the command and address signal to the DRAM 301, so that the controller 304 obtains the control right of the DRAM 301, thereby, the controller 304 can read the data in the DRAM 301 into the controller 304 via the data buffer 306 and the local data bus LDQ. While reading the data in the DRAM 301, the controller 304 first refreshes the data in the cache memory occupied by its processing unit to the local DRAM 303, then stores the data in the SRAM of the controller 304 to the NAND Flash 302, and finally stores the data in the local DRAM 303 to the NAND Flash 302. Since it takes a certain time period to read the data in the DRAM 301, the data in the cache memory occupied by the processing unit, the SRAM of the controller 304, and the local DRAM 303 are backed up in parallel to shorten the overall backup time, thereby reducing the requirements for the super capacitor 400.

[0212] After the controller 304 reads the data in the DRAM 301, the controller 304 stores the data in the above-mentioned address in the NAND Flash 302. Subsequently, the controller 304 performs power-off of the NVDIMM 300, that is, the super capacitor 400 no longer supplies power.

[0213] If the host detects that the last power failure was abnormal after the system is powered on and there is a correct data backup in the NVDIMM 300, the host will send a data recovery command through the system management bus pin SMBus. After receiving the recovery data command, the controller 304 sends a recovery data command to the clock driver 305 via the local command bus LCOM, and reads the data in the DRAM 301 stored during the data backup from the NAND Flash 302. In response to the recovery data command, the clock driver 305 configures the data buffer 306 via the data buffer command bus BCOM and sends the recovery data command to the DRAM 301, so that the controller 304 has the operation control right of the DRAM 301. Thus, after reading the data from the NAND Flash 302, the controller 304 can write the data back to the DRAM 301 via the local data bus LDQ and the data buffer 306. Subsequently, the host can read the data written back to the DRAM 301.

[0214] As will be apparent to those skilled in the art, many different ways of performing the method are possible. For example, the order of the steps may be changed or some steps may be performed in parallel. In addition, other method steps may be inserted between steps. The inserted steps may represent improvements to the method such as described herein, or may be unrelated to the method. In addition, a given step may not be fully completed before starting the next step.

[0215] In one or more embodiments, the system and / or module and / or unit and / or circuit and / or box can be provided in whole or in part in hardware and / or firmware, including but not limited to: one or more application-specific integrated circuits (ASICs), digital signal processors, discrete circuits, logic gates, standard integrated circuits, state machines, lookup tables, controllers (e.g., by executing appropriate instructions, and including microcontrollers and / or embedded controllers), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), etc. and various combinations thereof. In particular, in one or more embodiments, the controller, processing unit, clock driver, volatile memory, non-volatile memory, data buffer, cache memory, etc. can be implemented in whole or in part as a so-called application-specific integrated circuit (ASIC), that is, an integrated circuit (IC) customized for their specific use. In addition, in one or more embodiments, the method according to the present invention can be performed using software, which may have been downloaded and / or stored in a corresponding memory, for example, a volatile memory (such as RAM, DRAM, SRAM, etc.) or a non-volatile memory (such as CD-ROM, flash memory device, etc.). Alternatively, the device may be implemented in whole or in part in programmable logic, for example as a field programmable gate array (FPGA).For example, the circuit may be implemented in CMOS, for example using a hardware description language (such as Verilog, VHDL, etc.).

[0216] While various preferred embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A storage device, characterized in that: include: Host interface; Controller; Data buffer; Clock driver; a first storage area for storing data having an access frequency within a first access frequency range; as well as a second storage area for storing data having an access frequency within a second access frequency range; wherein the access frequency within the first access frequency range is higher than the access frequency within the second access frequency range; The second storage area includes a plurality of sub-storage areas, the second access frequency range includes a plurality of sub-access frequency ranges, and the plurality of sub-storage areas are respectively used to store data having access frequencies within different sub-access frequency ranges; wherein data having an access frequency within the second access frequency range is stored in the second storage area via the first storage area, wherein the controller is configured to: in response to receiving a first command and an address signal including a write command and a write address associated with the write command being on the second storage area, write the data on the data channel of the host interface into the first storage area; read the data written into the first storage area into the controller; and write the data into different sub-storage areas of the second storage area according to the access frequency of the data read into the controller; Wherein, the first storage area includes multiple volatile memories, and the controller is further configured to: encode the write address so that the encoded write address is on the first storage area, and obtain an encoded first command and address signal; send the encoded first command and address signal to the clock driver via a command and data bus between the controller and the clock driver; and the clock driver is configured to forward the encoded first command and address signal to the multiple volatile memories to write the data on the data channel to the encoded write addresses of the multiple volatile memories.

2. The storage device according to claim 1, characterized in that The first storage area includes a plurality of volatile memories.

3. The storage device according to claim 2, characterized in that: There are multiple data buffers, which are connected to the multiple volatile memories and the data channels of the host interface in a one-to-one correspondence.

4. The storage device according to any one of claims 1 to 3, characterized in that: The data buffer is connected to the controller via a local data bus.

5. The storage device according to any one of claims 1 to 3, characterized in that: The controller is connected to the command and address channels of the host interface.

6. The storage device according to any one of claims 1 to 3, characterized in that: The controller is connected to the clock driver via a command and data bus and a local command bus respectively.

7. The storage device according to any one of claims 1 to 3, characterized in that: The clock drivers are connected to the first storage area and the data buffer respectively.

8. The storage device according to claim 7, characterized in that: The clock driver is connected to the data buffer via a data buffer command bus to configure the data buffer.

9. The storage device according to claim 1, characterized in that: The second storage area includes a first sub-storage area, a second sub-storage area and a third sub-storage area; The second access frequency range includes a first sub-access frequency range, a second sub-access frequency range and a third sub-access frequency range from high to low access frequencies; Among them, the first sub-storage area is used to store data with an access frequency within the first sub-access frequency range, the second sub-storage area is used to store data with an access frequency within the second sub-access frequency range, and the third sub-storage area is used to store data with an access frequency within the third sub-access frequency range.

10. The storage device according to claim 9, characterized in that: The first sub-storage area is located in the controller.

11. The storage device according to claim 10, characterized in that: The first sub-storage area is a cache memory.

12. The storage device according to claim 11, characterized in that: The cache memory is a static random access memory.

13. The storage device according to any one of claims 9 to 12, characterized in that: The second sub-storage area is a local dynamic random access memory.

14. The storage device according to any one of claims 9 to 12, characterized in that: The third sub-storage area is a non-volatile memory.

15. The storage device according to claim 14, characterized in that: The non-volatile memory is Flash, phase change memory or resistive memory.

16. The storage device according to any one of claims 9 to 12, characterized in that: The controller is connected to the second sub-storage area and the third sub-storage area respectively.

17. The storage device according to claim 1, characterized in that: The controller receives the first command and address signals from a command and address channel of the host interface.

18. The storage device according to claim 1, wherein: The data buffer is connected to the controller via a local data bus; The controller is configured to send a second command and address signal including a read command and the encoded write address to the clock driver via a local command bus after writing the data on the data channel to the encoded write address; and The clock driver is configured to, in response to receiving the second command and address signal, configure the data buffer and forward the second command and address signal to the plurality of volatile memories to read the data in the encoded write address to the controller via the data buffer and the local data bus.

19. The storage device according to any one of claims 1 to 3, characterized in that: The data in the second storage area is read out via the first storage area.

20. The storage device according to claim 19, characterized in that The controller is configured to: In response to receiving a third command and address signal including an internal write command, and an access address associated with the internal write command being on the second storage area, reading data from an actual storage address corresponding to the access address in a data write phase; Writing the read data from the controller into the first storage area; and In response to receiving a fourth command and address signal including a read command and a read address associated with the read command being the same as the access address, the data is read out from the first storage area.

21. The storage device according to claim 20, characterized in that The controller receives the third command and address signal and the fourth command and address signal from a command and address channel of the host interface.

22. The storage device according to claim 20, characterized in that The first storage area includes a plurality of volatile memories, and the data buffer is connected to the controller via a local data bus; The controller is configured to send a fifth command and address signal to the clock driver via a local command bus, the fifth command and address signal including a write command and a write address on the plurality of volatile memories; the clock driver being configured to, in response to receiving the fifth command and address signal, configure the data buffer and forward the fifth command and address signal to the plurality of volatile memories; and The controller is further configured to write the data read from the actual storage address to the write address via the local data bus and the data buffer.

23. The storage device according to claim 22, characterized in that The controller is configured to: encoding the read address so that the encoded read address is the same as the write address, and obtaining an encoded fourth command and address signal; sending the encoded fourth command and address signal to the clock driver via a command and address bus between the controller and the clock driver; and The clock driver is configured to, in response to receiving the encoded fourth command and address signal, configure the data buffer and forward the encoded fourth command and address signal to the plurality of volatile memories to read out the data in the write address via a data channel of the host interface.

24. The storage device according to claim 14, characterized in that The storage device is configured to receive data to be backed up and store the data to be backed up in the first storage area and the first sub-storage area and the second sub-storage area; The controller is configured to: In response to receiving a data backup signal, reading the data in the first storage area to the controller, and storing the data in the first sub-storage area and the second sub-storage area to the third sub-storage area; and The data read from the first storage area to the controller is stored in the nonvolatile memory.

25. The storage device according to claim 24, characterized in that The first storage area includes a plurality of volatile memories, and the data buffer is connected to the controller via a local data bus; The controller is configured to, in response to receiving the data backup signal, send a sixth command and address signal including a backup command and a backup address to the clock driver via a local command bus; The clock driver is configured to, in response to receiving the sixth command and address signal, configure the data buffer and forward the sixth command and address signal to the plurality of volatile memories to read data in the plurality of volatile memories to the controller via the data buffer and the local data bus.

26. The storage device according to claim 25, characterized in that The controller includes a processing unit and is configured to, in response to receiving the data backup signal, sequentially perform the following steps during reading the data in the plurality of volatile memories into the controller: - storing the data in the space of the first sub-storage area occupied by the processing unit into the second sub-storage area; - storing data in the space of the first sub-storage area not occupied by the processing unit into the third sub-storage area; and - storing the data in the second sub-storage area into the third sub-storage area.

27. The storage device according to claim 24, characterized in that It also includes an emergency power supply interface for connecting to a backup power supply. The controller is configured to switch the storage device to power supply through the emergency power supply interface in response to receiving the data backup signal.

28. The storage device according to claim 24, characterized in that The controller is configured to perform power-down of the storage device after storing the data read from the first storage area in the third sub-storage area.

29. The storage device according to any one of claims 9 to 12, characterized in that: The storage device is configured to, in response to receiving a restore data command, restore data in the first storage area stored during data backup to the first storage area from the third sub-storage area.

30. The storage device according to claim 29, characterized in that The controller is configured to, in response to receiving the restore data command, send the restore data command to the clock driver, while reading data in the first storage area stored during data backup from the third sub-storage area; The clock driver is configured to, in response to receiving the resume data command, configure the data buffer and forward the resume data command to the first storage area; The controller is further configured to write back the data read from the third sub-storage area to the first storage area after the clock driver configures the data buffer and forwards the restore data command to the first storage area.

31. The storage device according to claim 30, characterized in that The controller is configured to receive the resume data command via a system management bus of the host interface, send the resume data command to the clock driver via a local command bus, and write back the data read from the third sub-storage area to the first storage area via a local data bus and the data buffer.

32. The storage device according to claim 27, characterized in that The backup power source is a supercapacitor.

33. A method for writing data into a storage device, characterized in that: The storage device comprises a first storage area and a second storage area; Wherein, the writing method includes: storing data having an access frequency within a first access frequency range in the first storage area; and storing data having an access frequency within a second access frequency range in the second storage area; wherein the access frequency within the first access frequency range is higher than the access frequency within the second access frequency range; Wherein, the writing method further includes: Data having an access frequency within the second access frequency range is stored in the second storage area via the first storage area.

34. The writing method according to claim 33, characterized in that: The first storage area includes a plurality of volatile memories.

35. The writing method according to claim 33 or 34, characterized in that: The second storage area includes a plurality of sub-storage areas; Wherein, the writing method includes: dividing the second access frequency range into a plurality of sub-access frequency ranges; and Data having access frequencies within different sub-access frequencies are respectively stored in corresponding sub-storage areas among the plurality of sub-storage areas.

36. The writing method according to claim 35, characterized in that: The second storage area includes a first sub-storage area, a second sub-storage area and a third sub-storage area; Wherein, the writing method includes: Dividing the second access frequency range into a first sub-access frequency range, a second sub-access frequency range and a third sub-access frequency range from high to low access frequencies; storing data having an access frequency within the first sub-access frequency range in the first sub-storage area; storing data having an access frequency within the second sub-access frequency range in the second sub-storage area; and Data having an access frequency within the third sub-access frequency range is stored in the third sub-storage area.

37. The writing method according to claim 36, characterized in that: The storage device includes a controller, and the first sub-storage area is located in the controller.

38. The writing method according to claim 37, characterized in that: The first sub-storage area is a cache memory.

39. The writing method according to claim 38, characterized in that: The cache memory is a static random access memory.

40. The writing method according to claim 36, characterized in that: The second sub-storage area is a local dynamic random access memory.

41. The writing method according to claim 36, characterized in that: The third sub-storage area is a non-volatile memory.

42. The writing method according to claim 41, characterized in that: The non-volatile memory is Flash, phase change memory or resistive memory.

43. A method for writing data into a storage device, characterized in that: The storage device includes a controller, a data buffer, a first storage area and a second storage area, and the writing method includes: In response to receiving a first command and address signal including a write command and a write address associated with the write command being at the second storage area, writing data into the first storage area; reading the data written into the first storage area into the controller; and Data is written into different sub-storage areas of the second storage area according to the access frequency of the data read from the controller.

44. The writing method according to claim 43, characterized in that: The first storage area includes a plurality of volatile memories, the storage device also includes a clock driver, and the writing method includes: encoding the write address so that the encoded write address is on the plurality of volatile memories and obtaining an encoded first command and address signal; sending the encoded first command and address signals to the clock driver; and The encoded first command and address signals are forwarded to the plurality of volatile memories to write the data to the encoded write addresses of the plurality of volatile memories.

45. The writing method according to claim 44, characterized in that: The data buffer is connected to the plurality of volatile memories and is connected to the controller via a local data bus, and the writing method comprises: After writing the data to the encoded write address, sending a second command and address signal including a read command and the encoded write address to the clock driver; configuring the data buffer and forwarding the second command and address signals to the plurality of volatile memories; and The data in the encoded write address is read to the controller via the data buffer and the local data bus.

46. ​​The writing method according to any one of claims 43 to 45, characterized in that: The writing method comprises: storing data having an access frequency within a first access frequency range in the first storage area; and storing data having an access frequency within a second access frequency range in the second storage area; The access frequency within the first access frequency range is higher than the access frequency within the second access frequency range.

47. The writing method according to claim 46, characterized in that: The second storage area includes a first sub-storage area, a second sub-storage area and a third sub-storage area; Wherein, the writing method includes: Dividing the second access frequency range into a first sub-access frequency range, a second sub-access frequency range and a third sub-access frequency range from high to low access frequencies; storing data having an access frequency within the first sub-access frequency range in the first sub-storage area; storing data having an access frequency within the second sub-access frequency range in the second sub-storage area; and Data having an access frequency within the third sub-access frequency range is stored in the third sub-storage area.

48. A method for reading data from a storage device, characterized in that: The storage device comprises a first storage area and a second storage area, and the reading method comprises reading data in the second storage area via the first storage area; Wherein, the storage device includes a controller, and the reading method includes: In response to receiving a third command and address signal including an internal write command, and an access address associated with the internal write command being on the second storage area, reading data from an actual storage address corresponding to the access address in a data write phase; writing the data from the controller into the first storage area; and In response to receiving a fourth command and address signal including a read command and a read address associated with the read command being the same as the access address, the data is read out from the first storage area.

49. The reading method according to claim 48, characterized in that: The storage device includes a data buffer, the first storage area includes a plurality of volatile memories, and the reading method includes: sending a fifth command and address signal to the clock driver, the fifth command and address signal including a write command and a write address on the plurality of volatile memories; configuring the data buffer and forwarding the fifth command and address signals to the plurality of volatile memories; and The data is written to write addresses on the plurality of volatile memories.

50. The reading method according to claim 49, characterized in that: The reading method comprises: encoding the read address so that the encoded read address is the same as the write address, and obtaining an encoded fourth command and address signal; sending the encoded fourth command and address signal to the clock driver; configuring the data buffer and forwarding the encoded fourth command and address signals to the plurality of volatile memories; and The data is read out from the write addresses of the plurality of volatile memories.

51. A data backup method for a storage device, characterized in that: The storage device includes a controller, a first storage area and a second storage area, wherein the second storage area includes a first sub-storage area, a second sub-storage area and a third sub-storage area; Wherein, the data backup method comprises: Receiving data to be backed up and storing the data to be backed up in the first storage area and the first sub-storage area and the second sub-storage area; In response to receiving a data backup signal, reading the data in the first storage area to the controller, and storing the data in the first sub-storage area and the second sub-storage area to the third sub-storage area; and The data read from the first storage area to the controller is stored in the third sub-storage area.

52. The data backup method according to claim 51, characterized in that: The storage device includes a clock driver and a data buffer, and the first storage area includes a plurality of volatile memories; Wherein, the data backup method comprises: In response to receiving the data backup signal, sending a sixth command and address signal including a backup command and a backup address to the clock driver; configuring the data buffer and forwarding the sixth command and address signals to the plurality of volatile memories; and The data in the plurality of volatile memories are read to the controller.

53. The data backup method according to claim 52, characterized in that: The controller includes a processing unit, and the data backup method includes: The following steps are performed sequentially during the process of reading the data in the plurality of volatile memories into the controller: - storing the data in the space of the first sub-storage area occupied by the processing unit into the second sub-storage area; - storing data in the space of the first sub-storage area not occupied by the processing unit into the third sub-storage area; and - storing the data in the second sub-storage area into the third sub-storage area.

54. The data backup method according to any one of claims 51 to 53, characterized in that: The storage device includes an emergency power supply interface for connecting to a backup power supply; Wherein, the data backup method comprises: In response to receiving the data backup signal, the storage device is switched to be powered by the emergency power supply interface.

55. The data backup method according to any one of claims 51 to 53, characterized in that: The data backup method comprises: After the data read from the first storage area is stored in the third sub-storage area, power-down of the storage device is performed.

56. The data backup method according to claim 54, characterized in that: The backup power source is a supercapacitor.

57. A data recovery method for a storage device, characterized in that: The storage device comprises a first storage area and a second storage area, wherein the second storage area comprises a first sub-storage area, a second sub-storage area and a third sub-storage area; The data recovery method includes, in response to receiving a restore data command, restoring the data in the first storage area stored during data backup from the third sub-storage area to the first storage area.

58. The data recovery method according to claim 57, characterized in that: The storage device includes a clock driver and a data buffer, and the data recovery method includes: sending the restore data command to the clock driver, and simultaneously reading the data in the first storage area stored during the data backup period from the third sub-storage area; configuring the data buffer and forwarding the restore data command to the first storage area; and The data read from the third sub-storage area is written back to the first storage area.

59. The data recovery method according to claim 58, characterized in that: The storage device includes a host interface, and the data recovery method includes: receiving the restore data command via a system management bus of the host interface; sending the recover data command to the clock driver via a local command bus; and The data read from the third sub-storage area is written back to the first storage area via a local data bus and the data buffer.

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