Semiconductor Package with Sidewall Connection

Abstract

Embodiments of the present disclosure relate to a semiconductor package with sidewall connections. A fan-out wafer-level package is provided that includes a semiconductor die having redistribution layers on its sidewalls. The redistribution layer located above the die includes an extension portion that extends along the sidewalls. The semiconductor die is encapsulated in a molding compound layer. The molding compound layer is located between the extension portion of the redistribution layer and the sidewalls of the semiconductor die. Solder contacts for electrically connecting the semiconductor device to an electronic circuit board are located on the redistribution layer. The sidewalls of the solder contacts and the redistribution layer can provide electrical contact at two different locations. Thus, the package can be used to improve interconnectivity by providing vertical and horizontal connections.

Description

Technical Field

[0001] This disclosure relates to a wafer-level package having an extended redistribution layer formed on the sidewall of a semiconductor die for providing additional input / output terminals within the package. Background Technology

[0002] A typical semiconductor package includes input / output connections for connecting the semiconductor package to various other external circuitry on its top surface. These various external circuitry may include other semiconductor packages or printed circuit boards or any other type of external circuitry.

[0003] In traditional wafer-level chip-scale packaging (WLCSP), a technique for packaging integrated circuits (ICs) at the wafer level, I / O connections are typically provided only on the top side of the package via solder balls mounted on a semiconductor die. This WLCSP packaging limits the number of I / O connections in the package and, because I / O connections are provided only on the top side of the package, it limits the ways in which packages can be stacked.

[0004] Due to this limited application in traditional WLCSP structures, the package size cannot meet the industry's growing demand for the smallest possible package size. Summary of the Invention

[0005] This disclosure relates to a semiconductor package that utilizes the sidewall region of a WLCSP package to provide additional I / O connections and reduce package size. Therefore, a semiconductor package and a method of manufacturing such a semiconductor package are provided, which have additional I / O connections and minimize the overall size of the semiconductor package. That is, by increasing the number of I / O connections in the package, the semiconductor package can be horizontally and vertically stacked with other semiconductor packages or circuits using the proposed sidewall I / O connections.

[0006] Another aspect of this disclosure is to provide a semiconductor package that can provide improved interconnectivity between semiconductor packages.

[0007] Another aspect of this disclosure is to provide a semiconductor package that can be stacked vertically and horizontally to increase connectivity in all directions.

[0008] Another aspect of this disclosure is to provide a semiconductor package that can be stacked in a 3D structure that occupies minimal space and thus reduces the overall size of the semiconductor device.

[0009] Another aspect of this disclosure is to provide a method for manufacturing a semiconductor package with additional I / O connections using a conventional wafer-level chip-scale packaging bumping process without adding additional manufacturing stages. This helps to maintain the cost of the entire manufacturing process. Attached Figure Description

[0010] To better understand the embodiments, reference will now be made to the accompanying drawings by way of example only. In the drawings, the same reference numerals identify similar elements or actions. The dimensions and relative positions of the elements in the drawings need not be drawn to scale. For example, the shapes and angles of various elements need not be drawn to scale, and some of these elements may be enlarged and positioned to improve the readability of the drawings. Furthermore, the specific shapes of the drawn elements are not necessarily intended to convey any information about the actual shape of the particular element and may be chosen simply for ease of identification in the drawings.

[0011] Figure 1 This is a cross-sectional view of an exemplary embodiment of a semiconductor structure according to the present disclosure, the semiconductor structure having an extended redistribution layer on the sidewall of a semiconductor die;

[0012] Figure 2 This is based on exemplary embodiments of the present disclosure. Figure 1 A top view of the semiconductor structure;

[0013] Figure 3A and Figure 3B An example of providing a mold protective layer according to an embodiment of the present disclosure is shown;

[0014] Figure 4 A cross-sectional view of two semiconductor structures having connections using solder balls is shown according to an embodiment of the present disclosure;

[0015] Figure 5 A cross-sectional view of two semiconductor structures having a connection using wire bonding is shown according to another embodiment of the present disclosure;

[0016] Figures 6A to 6I This is a cross-sectional view illustrating an exemplary method for creating an extended redistribution layer according to an exemplary embodiment of the present disclosure;

[0017] Figure 7 A cross-sectional view of a scribed adjacent semiconductor structure according to an embodiment of the present disclosure is shown. Detailed Implementation

[0018] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the art will recognize that the embodiments can be practiced without one or more of these specific details or using other methods, components, materials, etc. In other instances, well-known structures associated with chip packaging or wafer-level chip-scale packaging (WLCSP) have not been shown or described in detail so as not to unnecessarily obscure the description of the embodiments.

[0019] Unless the context otherwise requires, throughout the following specification and claims, the word “comprising” and its variations (such as “including” and “having”) shall be interpreted in an open-ended sense, that is, as “including but not limited to”. Furthermore, unless the context otherwise expressly indicates otherwise, the terms “first,” “second,” and similar sequence indicators shall be interpreted as interchangeable.

[0020] Throughout this specification, the reference to "an embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases "in an embodiment" or "in one embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner.

[0021] Unless otherwise expressly provided, the singular forms “a,” “an,” and “the” used in this specification and the appended claims include the plural objects. It should also be noted that, unless otherwise expressly provided, the term “or” is generally used in its broadest sense, that is, “and / or.”

[0022] The dashed lines in the attached diagram are intended to indicate the presence of additional elements, but have been omitted for simplicity.

[0023] Figure 1 This is a cross-sectional view of a portion of a semiconductor structure 100 according to an exemplary embodiment of the present disclosure. In this embodiment, the semiconductor structure 100 includes a semiconductor die 110 having a semiconductor substrate, the semiconductor substrate including various active and passive circuits, such as transistors, resistors, capacitors, logic, etc. The semiconductor structure 100 also includes contact pads 120, a passivation layer 130, a first dielectric layer 140, a redistribution layer 150, a second dielectric layer 160, and a conductive structure 171 including a metallization layer 170. The conductive structure 171 can be any suitable structure capable of conducting electrical signals, and can be, but is not limited to, an under-bump metallization structure (UBM) as the metallization layer 170, and solder bumps or solder balls 180. These conductive structures form the basis for providing electrical contacts, which will be described in detail below. However, other embodiments may include fewer or more elements of the semiconductor structure depending on specific design requirements.

[0024] A semiconductor die 110 is disposed on a carrier substrate of a wafer (not shown). The semiconductor die 110 may have a first surface 111, a second surface 113, and a third surface 115. In one embodiment, the first surface 111 may refer to, for example, a first surface 111. Figure 1The semiconductor die 110 is disposed on its top surface. The first surface may be, for example, a planar surface. Contact pads 120 may be disposed on the top surface of the semiconductor die 110. The semiconductor die 110 includes a second surface 113, which may refer to a side surface of the semiconductor die 110. In one embodiment, the first surface 111 and the second surface 113 are laterally opposite to each other. In another embodiment, the first surface 111 and the second surface 113 are perpendicular to each other. The semiconductor die 110 also includes a third surface 115, which may refer to a bottom surface of the semiconductor die 110. The third surface 115 of the semiconductor die 110 may contact a carrier substrate of the wafer. The first surface 111 and the third surface 115 are opposite to each other and may be parallel to each other. The semiconductor die 110 may be made of materials including, but not limited to, silicon (Si) or gallium arsenide (GaAs).

[0025] Contact pads 120 are located on the first surface 111 of the semiconductor die 110. In one embodiment, contact pads 120 are disposed on the top surface of the semiconductor die 110. In this embodiment, contact pads 120 may overlap a region of the semiconductor die 110 and do not necessarily have a surface coplanar with the first surface 111 of the semiconductor die 110. However, in some embodiments, to minimize the overall height and thickness of the semiconductor structure 100, contact pads 120 may be embedded or recessed in the semiconductor die 110 and may have a top surface 111 coplanar with the semiconductor die 110. Embedding contact pads 120 in the semiconductor die 110 may include etching the semiconductor die 110 and depositing contact pads 120 on the etched portion of the die 110. This contact may be part of a processing step for forming active and passive circuitry in the die. Thus, contact pads 120 may be deposited on the semiconductor die 110 to a position below the first surface 111 of the semiconductor die 110. In one embodiment, the contact pad 120 is a metal pad and may be made of a conductive material, including but not limited to metals such as copper (Cu) and aluminum (Al).

[0026] A passivation layer 130 is located on the semiconductor die 110. In one embodiment, the passivation layer 130 is disposed on the semiconductor die 110 and on a first portion 117 of the contact pad 120. For example, the passivation layer 130 overlaps and contacts the two edge portions of the contact pad 120. The passivation layer 130 can be made of an inorganic dielectric material. For example, the passivation layer 130 can be made using silicon nitride (SiN), silicon dioxide (SiO2), other dielectrics, or any compound utilizing a combination of Si and N or Si and O. The passivation layer 130 serves to protect the semiconductor die 110. Depending on the design, the passivation layer 130 may be omitted.

[0027] A first dielectric layer 140 is located on the passivation layer 130. In one embodiment, the first dielectric layer 140 is disposed on the passivation layer 130 and on a second portion 119 of the contact pad 120. For example, the first dielectric layer 140 overlaps with and contacts the second portion 119 of the contact pad 120. In one embodiment, the first dielectric layer 140 is made of an insulating material including but not limited to polybenzoxazole (PBO) or polyimide (PI).

[0028] A redistribution layer 150 is located on the first dielectric layer 140. In one embodiment, the redistribution layer 150 is disposed on the first dielectric layer 140 and the contact pad 120. For example, the redistribution layer 150 contacts a third portion 121 of the contact pad 120 and overlaps with the passivation layer 130 and the first dielectric layer 140. In one embodiment, the redistribution layer 150 includes an extension 152. For example, the extension 152 extends to the side of the semiconductor die 110 to cover the side of the passivation layer 130 and the first dielectric layer 140. The semiconductor die 110 may include a plurality of redistribution layers 150 formed around the periphery of the die and associated with other solder balls 180 located around the semiconductor die 110. In various applications, the redistribution layer 150 extends along each side of the semiconductor die 110 to provide electrical contact on some of the sidewalls.

[0029] To illustrate in more detail, the extension 152 of the redistribution layer 150 extends along the second surface 113 of the semiconductor die 110. In one embodiment, the redistribution layer 150 extends to the second surface 113 of the semiconductor die 110 (e.g., the sidewall of the semiconductor die 110) and covers the sidewalls of the passivation layer 130 and the first dielectric layer 140, thereby preventing the passivation layer 130 and the first dielectric layer 140 from being directly exposed.

[0030] In one embodiment, the extension 152 of the redistribution layer 150 extends along the second surface 113 of the semiconductor die 110 to expose the lip portion 112 of the semiconductor die 110. For example, the redistribution layer 150 does not extend all the way down along the second surface 113 (e.g., a sidewall) and may cover the sides of the passivation layer 130 and the first dielectric layer 140 while exposing the top and side surfaces of the lip portion 112 of the semiconductor die 110. In another embodiment, such as Figure 1 As shown, the outer surface of the extended redistribution layer 150 can be coplanar with the outer surface of the lip portion 112 of the semiconductor die 110.

[0031] In another embodiment, the extension 152 of the redistribution layer 150 extends downward along the second surface 113 of the semiconductor die 110. For example, the redistribution layer 150 extends downward along the sidewall and may cover the sidewalls of the passivation layer 130, the first dielectric layer 140, and the semiconductor die 110. In this embodiment, the extended redistribution layer 150 may cover the lip portion 112 of the semiconductor die 110 to provide the entire surface as an electrical contact. Although not shown, if the extended redistribution layer 150 covers the lip portion 112 of the semiconductor die 110, the extended redistribution layer 150 will form a stepped shape in the sidewall of the semiconductor die 110 due to the lip portion 112.

[0032] In another embodiment, the semiconductor die 110 may lack the lip portion 112, and the extension portion 152 of the redistribution layer 150 may extend downward along the second surface 113 of the semiconductor die 110 to reach the third surface 115 of the semiconductor die 110, see also Figure 3B For example, the sides of the semiconductor die 110, the passivation layer 130, and the first dielectric layer 140 may be coplanar, and the redistribution layer 150 may extend along the sidewalls to completely cover the sides of the passivation layer 130, the first dielectric layer 140, and the semiconductor die 110. In this embodiment, the extended redistribution layer 150 may extend until it reaches the third surface 115 (e.g., the bottom surface of the semiconductor die 110) to provide electrical contacts covering the entire second surface 113.

[0033] The second dielectric layer 160 is located on the redistribution layer 150. In one embodiment, the second dielectric layer 160 overlaps with the contact pad 120, passivation layer 130, first dielectric layer 140, and redistribution layer 150. In one embodiment, the second dielectric layer 160 may only contact a certain area of ​​the redistribution layer 150. The second dielectric layer 160 may be made of the same material as the first dielectric layer 140, including but not limited to PBO or PI.

[0034] A bump under-metal structure (UBM) 170 is located on the second dielectric layer 160. UBM 170 is included as a conductive structure within a conductive structure 171 for conducting electrical signals. In one embodiment, UBM 170 is in direct contact with the redistribution layer 150 at a location spaced apart from the contact pad 120. The redistribution layer 150 may be electrically and physically connected to the contact pad 120. This connection allows the conductive structure 171 to provide electrical signals to other input / output terminals, such as printed circuit boards (PCBs) or other circuitry (not shown). In this embodiment, UBM 170 is located on the second dielectric layer 160 without overlapping the contact pad 120. However, in another embodiment, the location of UBM 170 may overlap with the contact pad 120, or it may be located at a different location depending on any design requirements. UBM 170 may be made of a metal, including but not limited to nickel (Ni), Al, Cu, chromium (Cr), titanium (Ti), or any combination thereof.

[0035] Solder ball 180 is located on UBM 170. Solder ball 180 is also included in conductive structure 171 for conducting electrical signals. Solder ball 180 may be collectively referred to as solder ball, solder bump, solder joint, etc. Any structure capable of conducting electrical signals will be satisfied, and is not limited to solder ball.

[0036] In integrated circuit packaging, solder balls provide electrical contacts between the chip package and the PCB, which provides an electrical contact via the solder balls. However, according to this disclosure, a redistribution layer 150 on the first dielectric layer 140 extends along the sidewall of the semiconductor die 110 to provide a second electrical contact on the sidewall of the semiconductor die 110. With this configuration, the chip packages can be stacked both vertically and horizontally. This design improves interconnectivity between chip modules and saves area consumption.

[0037] Furthermore, this configuration provides an additional electrical contact on the side of the semiconductor die 110, avoiding the use of through-silicon vias (TSVs) or chip vias as vertical electrical connections through the silicon die. While TSVs also provide interconnectivity in 3D packaging and 3D integrated circuits, the manufacturing process involved in forming TSVs in a silicon die is complex, difficult, and expensive. Therefore, the extended redistribution layer 150 provides a configuration that consumes less area, involves less cost, consumes less power, and maintains a high interconnect speed due to the reduced connection length. Figure 4 and Figure 5 The text provides a more detailed explanation of vertical connections.

[0038] In another embodiment, the electrical signal output to solder ball 180 and the electrical signal output to extension 152 of redistribution layer 150 may be different. The semiconductor structure may be configured to provide two significantly different electrical signals. For example, semiconductor structure 100 provides at least two output terminals, and each of the signals output through solder ball 180 and extension of redistribution layer 150 may be different, depending on design requirements.

[0039] Alternatively, in some embodiments, the electrical signals output from solder ball 180 and extension 152 will be the same.

[0040] Figure 2 This is based on exemplary embodiments of the present disclosure. Figure 1 A top view of the semiconductor structure 100.

[0041] Reference Figure 2 The semiconductor structure 100 according to embodiments of the present disclosure may have an extension of the redistribution layer 150. (Refer to...) Figure 1 The cross-sectional view of the semiconductor structure 100 along the dotted line has been explained. The top view of the semiconductor structure 100 shows only one sphere; however, the package will include multiple spheres, some or all of which may have extensions of the redistribution layer 150.

[0042] exist Figure 2 In this process, solder balls 180 and a redistribution layer 150 are formed on a semiconductor die 110. The redistribution layer 150 extends to the sidewalls of the semiconductor die 110 to cover a portion of the sidewalls of the die 110. Although the sidewall regions overlapping with the extended redistribution layer 150 are completely covered on the sidewalls, the extended redistribution layer 150 may not cover the remaining sidewall regions of the semiconductor die 110.

[0043] In one embodiment, the sidewall region covered by the extended redistribution layer 150 may be narrow, thus providing a small contact area. However, in another embodiment, the sidewall region covered by the extended redistribution layer 150 may be wide, thus providing a large contact area. Therefore, different contact area sizes can be provided based on design requirements.

[0044] In other embodiments not shown, the extended redistribution layer 150 can be rewired to provide contacts at different portions of the semiconductor die 110. By stretching the extended redistribution layer 150 to different locations within the semiconductor die 110, the second contact provided by the extended redistribution layer 150 does not necessarily have to be located as shown regarding Figure 1 and Figure 2 On the side shown.

[0045] Figure 3A and Figure 3BAn example is shown of a mold protection layer provided by an extension 152 of a semiconductor die 110 and a redistribution layer 150, according to an embodiment of the present disclosure.

[0046] exist Figure 3A In this process, a mold protection layer 190 is provided to cover the sides of the semiconductor die 110, the side of the passivation layer 130, and the side of the first dielectric layer 140. The mold protection layer 190 is located between the extension 152 of the redistribution layer 150 and the semiconductor die 110, the passivation layer 130, and the first dielectric layer 140.

[0047] refer to Figure 3A The semiconductor die 110 has a lip portion 112 on a carrier substrate of a wafer (not shown). The semiconductor die 110 may have a first surface 111 and a second surface 113. The lip may extend through the second surface 113.

[0048] In one embodiment, the first surface 111 may refer to the top surface of the semiconductor die 110, and the contact pad 120 may be deposited on the first surface 111 of the semiconductor die 110. The semiconductor die 110 includes a second surface 113, which may refer to the side surface of the semiconductor die 110. In one embodiment, the first surface 111 and the second surface 113 may be transverse to each other. For example, the first surface 111 and the second surface 113 do not need to be perpendicular to each other. Thus, the first surface 111 and the second surface 113 may form an angle with each other. However, in another embodiment, the first surface 111 and the second surface 113 may be perpendicular to each other. The semiconductor die 110 may be made of materials including, but not limited to, Si or GaAs.

[0049] Contact pads 120 are deposited on a first surface 111 of the semiconductor die 110. In one embodiment, the contact pads 120 are located on the top surface of the semiconductor die 110. In this embodiment, the contact pads 120 may be positioned such that the surface of the contact pads 120 is coplanar with the first surface 111 of the semiconductor die 110. However, in different embodiments, the surface of the contact pads 120 does not necessarily have to be coplanar with the semiconductor die 110. In some embodiments, to minimize the overall height and thickness of the semiconductor structure 300, the contact pads 120 may be embedded in the semiconductor die 110 and may have a top surface coplanar with the semiconductor die 110. For example, the contact pads 120 may be metal pads and may be made of conductive materials including, but not limited to, Cu, Al, etc.

[0050] A passivation layer 130 is deposited on the semiconductor die 110. In one embodiment, the passivation layer 130 is located on the semiconductor die 110 and overlaps with a first portion 117 of the contact pad 120. For example, the passivation layer 130 overlaps two edge portions of the contact pad 120 and contacts the contact pad 120. In this embodiment, the passivation layer 130 is deposited on the semiconductor die 110 but does not extend to the lip portion 112 of the semiconductor die 110. The passivation layer 130 can be made of an inorganic or organic dielectric material. For example, the passivation layer 130 can be made using SiN, SiO2, other dielectrics, or any compound utilizing a combination of Si and N or Si and O. The passivation layer 130 serves to protect the semiconductor die 110. Depending on the design, the passivation layer 130 may be omitted.

[0051] A first dielectric layer 140 is deposited on the passivation layer 130. In one embodiment, the first dielectric layer 140 is located on the passivation layer 130 and overlaps with a second portion 119 of the contact pad 120. For example, the first dielectric layer 140 overlaps the second portion 119 of the contact pad 120 and contacts both the contact pad 120 and the passivation layer 130. In this embodiment, the first dielectric layer 140 is deposited on the passivation layer 130 but does not extend to the lip portion 112 of the semiconductor die 110. The first dielectric layer 140 may be made of, for example, but not limited to, PBO or PI.

[0052] A redistribution layer 150 is deposited on the first dielectric layer 140. In one embodiment, the redistribution layer 150 is located on the contact pad 120, the first dielectric layer 140, and the mold protection layer 190. For example, the redistribution layer 150 contacts a third portion 121 of the contact pad 120 and overlaps with the passivation layer 130, the first dielectric layer 140, and the mold protection layer 190. In one embodiment, the redistribution layer 150 includes an extension 152 that extends along a sidewall or a second surface 113 of the semiconductor die 110. In another embodiment, the other end of the redistribution layer 150 need not extend to the other side surface of the semiconductor die 110. That is, depending on circuit design requirements, the redistribution layer 150 may be formed on only one side of the semiconductor die 110. However, in different applications, the redistribution layer 150 may extend along both sides of the semiconductor die 110 to provide electrical contacts on both sidewalls of the semiconductor die 110.

[0053] An extension 152 of the redistribution layer 150 extends along a second surface 113 of the semiconductor die 110, including a lip portion 112. In one embodiment, the redistribution layer 150 extends to the second surface 113 of the semiconductor die 110 (e.g., a sidewall of the semiconductor die 110) and covers the top surface of the first dielectric layer 140 and the top and side surfaces of the mold protection layer 190, thereby preventing the passivation layer 130, the first dielectric layer 140, and the mold protection layer 190 from being directly exposed.

[0054] In one embodiment, the extension 152 of the redistribution layer 150 extends along the second surface 113 of the semiconductor die 110, but does not cover the lip portion 112 of the semiconductor die 110. For example, the redistribution layer 150 may not extend all the way down along the second surface 113 (e.g., the sidewall of the semiconductor die 110), and may cover the mold protection layer 190 until it reaches the top surface of the lip portion 112 of the semiconductor die 110.

[0055] In another embodiment, an extension 152 of the redistribution layer 150 extends along the second surface 113 of the semiconductor die 110 to expose the lip portion 112 of the semiconductor die 110. For example, the extension 152 of the redistribution layer 150 may be coplanar with the lip portion 112 of the semiconductor die 110. That is, the side surface of the lip portion 112 of the semiconductor die 110 may be coplanar with the extension 152 of the redistribution layer 150 extending along the second surface 113 (e.g., sidewall) of the semiconductor die 110.

[0056] A mold protection layer 190 is provided to cover the sides of the semiconductor die 110, the sides of the passivation layer 130, and the sides of the first dielectric layer 140. The mold protection layer 190 may provide additional protection on top of the extended redistribution layer 150. The mold protection layer 190 is located between the extension 152 of the redistribution layer 150 and the semiconductor die 110, the passivation layer 130, and the first dielectric layer 140. The mold protection layer 190 is disposed adjacent to the outer periphery of the semiconductor die. In one embodiment, the mold protection layer 190 surrounds the semiconductor die 110 to provide protection on the sidewalls of the semiconductor structure 300.

[0057] A compression molding process can be used to form the mold protection layer 190 to encapsulate the die with molding compound. However, other methods can be used and are not limited to this molding process. The mold protection layer 190 can provide additional protection on top of the extended redistribution layer 150. The mold protection layer 190 is located between the sides of the semiconductor die 110, the sides of the passivation layer 130, the sides of the first dielectric layer 140, and the extension of the redistribution layer 150, such that the electrical contact area on the sidewalls of the semiconductor die 110 is not reduced.

[0058] In another embodiment, the mold protection layer 190 may be positioned to cover a portion of the extension 152 of the redistribution layer 150. With this configuration, the electrical contact area provided on the sidewall of the semiconductor die 110 using the extension 152 of the redistribution layer 150 can be reduced. For example, the mold protection layer 190 may be formed between the lip portion 112 of the semiconductor die 110 and the extension 152 of the redistribution layer 150 to partially cover the lower extension of the redistribution layer 150. However, in different embodiments, depending on design requirements, the mold protection layer 190 may be provided to cover the upper extension or the middle extension of the redistribution layer 150.

[0059] A second dielectric layer 160 is deposited on the redistribution layer 150. In one embodiment, the second dielectric layer 160 overlaps with contact pads 120, passivation layer 130, first dielectric layer 140, and redistribution layer 150. For example, the second dielectric layer 160 is positioned such that it contacts a portion of the first dielectric layer 140 and a portion of the redistribution layer 150. The second dielectric layer 160 may be made of the same material as the first dielectric layer 140, including but not limited to PBO or PI.

[0060] UBM 170 is deposited on the second dielectric layer 160. The conductive structure 171 according to this disclosure also includes, in particular, UBM 170, solder balls 180, etc., which are capable of conducting electrical signals. In one embodiment, UBM 170 is in direct contact with the redistribution layer 150 in a location that does not overlap with the contact pad 120. The redistribution layer 150 may be electrically or physically connected to the contact pad 120, and this connection allows the conductive structure 171 to provide electrical signals to other input / output terminals, such as a PCB or other external circuitry (not shown). In this embodiment, UBM 170 is located on the second dielectric layer 160 that does not overlap with the contact pad 120. However, in another embodiment, the location of UBM 170 may overlap with the contact pad 120 or be located at a different location according to any design requirements. UBM 170 may be made of metals including, but not limited to, Ni, Al, Cu, Cr, Ti, or any combination thereof.

[0061] Solder ball 180 is mounted on UBM 170. Solder ball 180 is also included in conductive structure 171 for conducting electrical signals. Solder ball 180 may be collectively referred to as solder ball, solder bump, solder joint, etc. Any structure capable of conducting electrical signals will satisfy, and is not limited to, solder ball.

[0062] Based on current circuit packaging, solder balls can provide the first electrical contact to the chip package or PCB, but the extended redistribution layer 150 can also provide a second electrical contact on the sidewall of the semiconductor die 110. This configuration allows the chip packages to be stacked both vertically and horizontally. This design improves interconnectivity between chip modules and saves area footprint.

[0063] Furthermore, this configuration enhances interconnectivity in 3D packaging and 3D integrated circuits and reduces complexity involved in the manufacturing process because forming the extended redistribution layer 150 can be done using conventional bumping processes without adding additional manufacturing stages. For example, the extended redistribution layer 150 can be easily formed using a conventional WLCSP bumping process. Therefore, the complexity involved in forming the extended redistribution layer 150 is reduced, and the cost is lower. Further, due to the reduced connection length between chip packages or to the PCB, the extended redistribution layer 150 can provide a configuration that occupies less area, consumes less power, and still maintains high interconnect speeds. Figure 4 and Figure 5 The lieutenant general will provide a more detailed explanation of vertical connections.

[0064] In another embodiment, the electrical signal output to solder ball 180 and the electrical signal output to extension 152 of redistribution layer 150 may be different. The semiconductor structure may be configured to provide two significantly different electrical signals. For example, semiconductor structure 100 provides at least two output terminals, and each of the signals output through solder ball 180 and extension of redistribution layer 150 may be different, depending on design requirements.

[0065] exist Figure 3B In this process, a mold protection layer 190 is provided to cover the sides of the semiconductor die 110, the side of the passivation layer 130, and the side of the first dielectric layer 140. The mold protection layer 190 is located between the extension of the redistribution layer 150 and the semiconductor die 110, the passivation layer 130, and the first dielectric layer 140.

[0066] Reference Figure 3B The semiconductor die 110 has no lip portion. The semiconductor die 110 without a lip portion is disposed on a carrier substrate of a wafer (not shown). For clarity and to avoid obscuring the subject matter of this disclosure, regarding bonding... Figure 1 and Figure 3A The descriptions that can be easily found have been omitted, and repetitive explanations have been omitted.

[0067] A mold protection layer 190 is provided to cover the sides of the semiconductor die 110, the sides of the passivation layer 130, and the sides of the first dielectric layer 140. The mold protection layer 190 may provide additional protection on top of an extended redistribution layer 150 for the semiconductor die 110. The mold protection layer 190 is located between the extension of the redistribution layer 150 and the semiconductor die 110, the passivation layer 130, and the first dielectric layer 140. The mold protection layer 190 is disposed adjacent to the outer periphery of the semiconductor die. In one embodiment, the mold protection layer 190 surrounds the semiconductor die 110 to provide protection on the sidewalls of the semiconductor structure 320.

[0068] Only the features related to the mold protection layer 190 are described in detail. The mold protection layer 190 can be formed by using a compression molding process to encapsulate the die with molding compound. However, as mentioned, another suitable molding process can be used. The mold protection layer 190 is located between the sidewall 113 of the semiconductor die 110, the sidewall of the passivation layer 130, the sidewall of the first dielectric layer 140, and the extension 152 of the redistribution layer 150, such that the electrical contact area on the sidewalls of the semiconductor die 110 is not reduced. Because... Figure 3B The semiconductor die 110 in the mold has no lip portion, and the mold protective layer 190 can be formed to cover downwards until it reaches the third surface 115 of the semiconductor die 110. For example, the mold protective layer 190 can be formed to cover the entire second surface 113 of the semiconductor die 110.

[0069] An extension 152 of the redistribution layer 150 extends along the second surface 113 of the semiconductor die 110 and covers the mold protection layer 190. In one embodiment, the redistribution layer 150 extends over the mold protection layer 190 to the sidewall of the semiconductor die 110, such that the mold protection layer 190 is not directly exposed. This configuration allows the mold protection layer 190 to protect the semiconductor die 110 and the outer boundary of the extended redistribution layer 150 to have a wide contact surface on the sidewall of the semiconductor die 110.

[0070] In another embodiment, the extension 152 of the redistribution layer 150 extends downward along the second surface 113 of the semiconductor die 110 to reach the third surface 115 of the semiconductor die 110. For example, the redistribution layer 150 may extend downward along the sidewalls of the mold protection layer 190 and the bottom surface of the mold protection layer 190. If the extended redistribution layer 150 covers the mold protection layer 190 and reaches the third surface 115 of the semiconductor die 110, it will provide connectivity in all directions (e.g., the top direction through the solder ball 180, and the side direction using the extended redistribution layer 150) and increase the surface area capable of providing electrical contacts. This will improve vertical and horizontal interconnections between chip packages or with other external circuitry.

[0071] Figure 4 Cross-sectional views of two semiconductor structures according to embodiments of the present disclosure are shown, the two semiconductor structures being stacked and connected together and having solder balls on the lateral surfaces.

[0072] exist Figure 4 In this package 400, a portion includes a first semiconductor die 110 and a second semiconductor die 410 attached together via an adhesive layer 498. The adhesive layer 498 can be any suitable material for attaching the silicon dies together. For example, adhesives including, but not limited to, polyimide or epoxy resins can be used to bond the two silicon dies. The first semiconductor die 110 includes a first contact pad 120, a first passivation layer 130, a first dielectric layer 140, a first redistribution layer 150, a second dielectric layer 160, a first conductive structure 171 including a first UBM 170, and a first solder ball 180. The second semiconductor die 410 includes a second contact pad 420, a second passivation layer 430, a third dielectric layer 440, a second redistribution layer 450, a fourth dielectric layer 460, a second conductive structure 471 including a second UBM 470, and a second solder ball 480. However, other embodiments may include fewer or more elements of the semiconductor structure depending on specific design requirements.

[0073] The first semiconductor die 110 and other components of the first semiconductor die 110 are related to... Figure 1 or Figure 3A The methods described are similar. Therefore, repeated descriptions of the same elements are omitted.

[0074] A first semiconductor die 110 having a first solder ball 180 can be connected to a printed circuit board (PCB) 494 using a conductive layer 492. The conductive layer 492 can provide an electrical connection between the first solder ball 180 and the PCB 494. The conductive layer 492 can be made of any metal capable of conducting signals, including but not limited to Cu, Al, etc.

[0075] The second semiconductor die 410 may have a fourth surface 411, a fifth surface 413, and a sixth surface 415. In one embodiment, the fourth surface 411 may refer to the bottom surface, the fifth surface 413 may refer to the side surface, and the sixth surface 415 may refer to the top surface of the second semiconductor die 410, which faces downward in the figure.

[0076] The second contact pad 420 may be disposed on the top surface of the second semiconductor die 410. In one embodiment, the fifth surface 413 and the sixth surface 415 may be transverse to each other. In another embodiment, the fifth surface 413 and the sixth surface 415 may be perpendicular to each other.

[0077] The second semiconductor die 410 also includes a sixth surface 415, which may correspond to the top surface of the second semiconductor die 410. In one embodiment, the fourth surface 411 and the sixth surface 415 may be opposite each other. For example, the fourth surface 411 and the sixth surface 415 may be located on opposite sides facing each other. In another embodiment, the fourth surface 411 and the sixth surface 415 may be parallel to each other. The second semiconductor die 410 may be made of materials including, but not limited to, Si or GaAs.

[0078] In this embodiment, the third surface 115 of the first semiconductor die 110 (e.g., the bottom surface of the first semiconductor die 110) and the fourth surface 411 of the second semiconductor die 410 (e.g., the bottom surface of the second semiconductor die 410) may face each other. For example, the third surface 115 of the first semiconductor die 110 and the fourth surface 411 of the second semiconductor die 410 may be located on opposite sides and may be glued together using an adhesive layer 498. In other embodiments, the adhesive layer 498 may be omitted.

[0079] The second contact pad 420 is located on the sixth surface 415 of the second semiconductor die 410. In one embodiment, the second contact pad 420 is disposed on the top surface of the second semiconductor die 410. In this embodiment, the second contact pad 420 may overlap a region of the second semiconductor die 410 and does not necessarily have to have a surface coplanar with the sixth surface 415 of the second semiconductor die 410. However, in some embodiments, to minimize the overall height and thickness of the semiconductor structure 400, the second contact pad 420 may be embedded in the second semiconductor die 410 and may have a top surface coplanar with the second semiconductor die 410. Embedding the second contact pad 420 in the second semiconductor die 410 may include etching the second semiconductor die 410 and depositing the second contact pad 420 on the second semiconductor die 410. Thus, the second contact pad 420 may be deposited on the second semiconductor die 410 at a position lower than the top surface of the second semiconductor die 410. In one embodiment, the second contact pad 420 is a metal pad and is made of a conductive material, including but not limited to Cu, Al, etc.

[0080] The second passivation layer 430 is located on the second semiconductor die 410. In one embodiment, the second passivation layer 430 is disposed on the second semiconductor die 410 and on a first portion 417 of the second contact pad 420. For example, the second passivation layer 430 overlaps and contacts the two edge portions of the second contact pad 420. The second passivation layer 430 can be made using SiN, SiO2, other dielectrics, or any compound using a combination of Si and N or Si and O. The second passivation layer 430 serves to protect the second semiconductor die 410. Depending on the design, the second passivation layer 430 may be omitted.

[0081] A third dielectric layer 440 is located on the second passivation layer 430. In one embodiment, the third dielectric layer 440 is disposed on the second passivation layer 430 and on a second portion 419 of the second contact pad 420. For example, the third dielectric layer 440 overlaps with and contacts the second portion 419 of the second contact pad 420. In one embodiment, the third dielectric layer 440 is made of, but is not limited to, PBO or PI.

[0082] The second redistribution layer 450 is located on the third dielectric layer 440. In one embodiment, the second redistribution layer 450 is disposed on the third dielectric layer 440 and the second contact pad 420. For example, the second redistribution layer 450 contacts a third portion 421 of the second contact pad 420 and overlaps with the second passivation layer 430 and the third dielectric layer 440. In one embodiment, the second redistribution layer 450 includes an extension portion 452. In another embodiment, the other end of the second redistribution layer 450 need not extend to the other side surface of the second semiconductor die 410. That is, the second redistribution layer 450 may be formed only on one side of the second semiconductor die 410. However, in different applications, the second redistribution layer 450 may extend along both sides of the second semiconductor die 410 to provide electrical contact on both sidewalls.

[0083] An extension 452 of the second redistribution layer 450 extends along the fifth surface 413 (e.g., a side surface) of the second semiconductor die 410. In one embodiment, the second redistribution layer 450 extends to the fifth surface 413 (e.g., a sidewall of the second semiconductor die 410) and covers the sides of the second passivation layer 430 and the third dielectric layer 440, thereby preventing the second passivation layer 430 and the third dielectric layer 440 from being directly exposed.

[0084] In one embodiment, an extension 452 of the second redistribution layer 450 extends along the fifth surface 413 of the second semiconductor die 410 to expose the lip portion 412 of the semiconductor die 410. For example, the second redistribution layer 450 does not extend all the way down along the fifth surface 413 and may cover the sides of the second passivation layer 430 and the sides of the third dielectric layer 440, but leave the lip portion 412 of the second semiconductor die 410 open.

[0085] In another embodiment, in a semiconductor die without the lip portion 412 (e.g., both the first semiconductor die 110 and the second semiconductor die 410 are...), Figure 3B The die structure 320 seen in the image similarly lacks a lip portion, and the surfaces of the extended second redistribution layer 450 and the extended first redistribution layer 150 can be coplanar. However, due to the adhesive layer 498 between the two semiconductor dies, the extended second redistribution layer 450 and the extended first redistribution layer 150 can be electrically insulated from each other.

[0086] In an additional embodiment, the extension portion 452 of the second redistribution layer 450 extends downward along the fifth surface 413 of the second semiconductor die 410. For example, the second redistribution layer 450 extends downward along the sidewall and may cover the sidewalls of the second passivation layer 430, the third dielectric layer 440, and the second semiconductor die 410. In this embodiment, the extended second redistribution layer 450 may cover the lip portion 412 of the second semiconductor die 410 to provide the entire surface as an electrical contact. Although not shown, if the extended second redistribution layer 450 covers the lip portion 412 of the second semiconductor die 410, it will form a stepped shape in the sidewalls of the second semiconductor die 410 due to the lip portion 412. The extended second redistribution layer 450 and the extended first redistribution layer 150 may still be electrically insulated from each other due to the adhesive layer 498 between the two semiconductor dies.

[0087] A fourth dielectric layer 460 is located on the second redistribution layer 450. In one embodiment, the fourth dielectric layer 460 overlaps with the second contact pad 420, the second passivation layer 430, the third dielectric layer 440, and the second redistribution layer 450. In one embodiment, the fourth dielectric layer 460 may only contact a certain region of the second redistribution layer 450. The fourth dielectric layer 460 may be made of, but is not limited to, the same material as the third dielectric layer 140 (e.g., PBO or PI).

[0088] The second UBM 470 is located on the fourth dielectric layer 460. The second UBM 470 is included as a conductive structure in the conductive structure 471 for conducting electrical signals. In one embodiment, the second UBM 470 is in direct contact with the second redistribution layer 450 at a location spaced apart from the second contact pad 420. The second redistribution layer 450 may be electrically and physically connected to the second contact pad 420. In this embodiment, the second UBM 470 is located on the fourth dielectric layer 460 without overlapping the second contact pad 420. However, in another embodiment, the second UBM 470 may overlap with the second contact pad 420 or be located at a different location according to any design requirements. The second UBM 470 may be made of, but is not limited to, Ni, Al, Cu, Cr, Ti, or any combination thereof.

[0089] The second solder ball 480 is located on the second UBM 470. The second solder ball 480 is also included in the conductive structure 471 for conducting electrical signals. The second solder ball 480 can be collectively referred to as a solder ball, solder bump, solder joint, etc. Any structure capable of conducting electrical signals will satisfy, and is not limited to, a solder ball. Conductive structures such as the second solder ball 480 can provide electrical signals to other input / output terminals such as those on a PCB or other circuits. Although not explicitly stated... Figure 4 As shown, a first solder ball 180 mounted on a first semiconductor die 110 is connected to a PCB 494 to provide input / output terminals. Depending on design requirements, an additional PCB may be attached to a second solder ball 480 mounted on a second semiconductor die 410.

[0090] In wafer-level packaging, solder balls can be used for electrical connections to chip packages or PCBs. However, according to the wafer-level packaging of this disclosure, the first semiconductor die 110 and the second semiconductor die 410 are stacked perpendicularly to each other, and additional electrical contacts are provided on the second surface of the first semiconductor die 110 and the fifth surface 413 of the second semiconductor die 410. The first extended redistribution layer 150 and the second extended redistribution layer 450 can be connected by conductive connections. The conductive connections can be any material capable of conducting electrical signals, such as metals. In one embodiment, the conductive connections include, but are not limited to, solder joints, solder bumps, solder balls 496, or bonding leads 510. Figure 5 (as shown), or any similar structure providing electrical contacts on the sides. With this configuration, the chip packages can be stacked vertically and also connected horizontally due to the electrical contacts on the sidewalls. This design improves interconnectivity between chip modules and saves space.

[0091] exist Figure 4In the first embodiment, conductive connection 496 connects both the first extended redistribution layer 150 and the second extended redistribution layer 450 to form a large single contact. However, in other embodiments, individual conductive connections 496 can be used for each of the extended redistribution layers 150, 450. For example, a solder ball can be individually mounted on the first extended redistribution layer 150 to form one electrical contact, and a second solder ball can be individually mounted on the second extended redistribution layer 450 to form another electrical contact. This configuration not only increases the number of electrical contacts on the sides of the dual-stacked semiconductor structure 400, but also provides a basis for retrieving two different signals from the first extended redistribution layer 150 and the second extended redistribution layer 450. In the previous embodiment where solder ball 496 is stacked on both the first extended redistribution layer 150 and the second extended redistribution layer 450, the electrical contacts provided by solder ball 496 may only have one identical signal because solder ball 496 is connected to both the first extended redistribution layer 150 and the second extended redistribution layer 450. However, if individual solder balls are connected to each of the first and second extended redistribution layers 150 and 450, then two separate electrical signals can be obtained from each of the first and second extended redistribution layers 150 and 450.

[0092] Furthermore, this configuration enhances interconnectivity in 3D packaging and 3D integrated circuits. The fabrication process involved in forming the extended redistribution layer is not complex, difficult, or expensive, as it utilizes conventional WLCSP processes. The additional process involved is stacking two semiconductor dies together and providing solder joints 496 on the sides of the stacked semiconductor dies. Solder joints 496 provide lateral connections for the two vertically stacked semiconductor dies 110, 410. Solder joints 496 can be further used to horizontally connect any semiconductor package or external circuitry in the horizontal direction of the semiconductor structure 400. This allows for the formation of 3D packages that occupy less area and also involve lower cost. In addition, this allows for extended interconnectivity in both the vertical and horizontal directions. Furthermore, it consumes less power and maintains a higher interconnect speed due to the shortened connection length.

[0093] In another embodiment, the electrical signals output to the first solder ball 180 and the second solder ball 480 may be different from the electrical signals output through the solder joint 496. The semiconductor structure 400 may be configured to provide significantly different electrical signals according to different design requirements.

[0094] Figure 5 A cross-sectional view of a semiconductor package having connections using wire bonding, according to an embodiment of the present disclosure, is shown. Figure 5 In China, it has already been done Figure 4The corresponding components will be explained and will not be repeated.

[0095] Reference Figure 5 The first semiconductor die 110 and the second semiconductor die 410 in the vertically stacked semiconductor structure 500 can be connected together using wire bonding 510.

[0096] In a vertically stacked pair of semiconductor dies (e.g., first semiconductor die 110 and second semiconductor die 410), the electrical connection between the top semiconductor die 110 and the bottom semiconductor die 410 can be accomplished using wire bonding 510. For example, the material used for wire bonding 510 can include any metal capable of conducting electrical signals, such as Cu, Al, etc. This allows for a larger electrical contact area. Figure 4 In contrast to the solder joint 496 used, the wire bond 510 can electrically connect the extended first redistribution layer 150 of the top die 110 and the extended second redistribution layer 450 of the bottom die 410. In other embodiments, the wire bond 510 can be used to connect the semiconductor die to other semiconductor packages or other external circuitry (not shown).

[0097] The vertical stacking of semiconductor structure 500 not only improves interconnectivity in 3D packaging and 3D integrated circuits but also saves space, minimizing the overall package size. Semiconductor structure 500 also improves horizontal connectivity by providing additional electrical contacts on the second surface 113 of the first semiconductor die 110 and the fifth surface 413 of the second semiconductor die 410. The first extended redistribution layer 150 and the second extended redistribution layer 450 can be connected by wire bonding 510, which can be used to connect to external circuits or PCBs according to industrial requirements. With this configuration, chip packages can be vertically stacked and horizontally connected. This design improves interconnectivity between chip modules and saves area. It also allows for the formation of 3D packages that consume less power due to shorter connection lengths while maintaining high interconnect speeds.

[0098] In another embodiment, the electrical signals output to the first solder ball 180 and the second solder ball 480 may be different from the electrical signals output via wire bonding 510. The semiconductor structure 500 can be configured to provide significantly different electrical signals according to different design requirements.

[0099] Figures 6A to 6I This is a cross-sectional view illustrating an exemplary method for creating an extended redistribution layer according to an embodiment of the present disclosure.

[0100] In this embodiment, in Figure 6AIn this method, the process begins with a carrier substrate 602. A semiconductor die 604 is placed on the carrier substrate 602. For example, the semiconductor die 604 is attached to the carrier substrate 602 to attach it to the carrier substrate 602. The semiconductor die 604 includes a first surface 605, a second surface 607 transverse to the first surface 605, and a third surface 609 opposite to the first surface 605. The first surface 605 may refer to the top surface of the semiconductor die 604. The second surface 607 may refer to the side surface of the semiconductor die 604. In another embodiment, the first surface 605 and the second surface 607 may be perpendicular to each other. In other embodiments, the angle formed by the first surface 605 and the second surface 607 may be an angle of inclination. Additionally, in some embodiments, the first surface 605 and the third surface 609 may be located on opposite sides. For example, the first surface 605 and the third surface 609 may be parallel to each other, but not necessarily parallel. Additionally, the third surface 609 and the second surface 607 may be transverse to each other. Semiconductor die 604 can be made of, but is not limited to, materials such as Si or GaAs.

[0101] exist Figure 6B In this embodiment, contact pads 606 are provided on a first surface 605 of a semiconductor die 604. In one embodiment, the contact pads 606 are disposed on a top surface of the semiconductor die 604. In this embodiment, the contact pads 606 may overlap a region of the semiconductor die 604 and need not have a surface coplanar with the first surface 605 of the semiconductor die 604. However, in some embodiments, to minimize the overall height and thickness of the semiconductor structure, the contact pads 606 may be embedded in the semiconductor die 604 and may have a top surface coplanar with the semiconductor die 604. Embedding the contact pads 606 in the semiconductor die 604 may include etching the semiconductor die 604 and depositing the contact pads 606 on the die 604. Therefore, in some embodiments, the contact pads 606 may be deposited on the semiconductor die 604 at a position below the top surface of the semiconductor die 604. In one embodiment, the contact pads 606 are metal pads and are made of conductive materials including, but not limited to, Cu, Al, etc.

[0102] exist Figure 6C In this design, a passivation layer 608 is provided on the semiconductor die 604 and the contact pads 606. The passivation layer 608 can be deposited on the semiconductor die 604 and the contact pads 606 using various deposition methods known in the art. For example, the passivation layer 608 is made of materials such as SiN, SiO2, other dielectrics, or any compound using combinations of Si and N or Si and O. The passivation layer 608 serves to protect the semiconductor die 604. Depending on the design, the passivation layer 608 may be omitted.

[0103] exist Figure 6D In this process, a portion of the passivation layer 608 is partially removed to expose a portion of the contact pad 606. This partial removal of the passivation layer 608 creates an opening 610 and partially exposes the contact pad 606. With this removal, the passivation layer 608 overlaps with a first portion 617 of the contact pad 606.

[0104] exist Figure 6E A first dielectric layer 612 is provided on the passivation layer 608 and in the opening 610 created by the partial removal of the passivation layer 608. The first dielectric layer 612 can be deposited based on any deposition method known in the art. For example, the first dielectric layer 612 is disposed along the passivation layer 130 and the shape made by the opening 610. The first dielectric layer 612 is made of, but is not limited to, PBO or PI.

[0105] exist Figure 6F In this embodiment, a redistribution layer 616 is provided on the first dielectric layer 612. Before the redistribution layer 616 is deposited on the first dielectric layer 612, the first dielectric layer 612 is etched and removed to expose a portion of the contact pad 606. As a result of the removal, in one embodiment, the first dielectric layer 612 is disposed on the passivation layer 608 and on a second portion 619 of the contact pad 606. For example, the first dielectric layer 612 overlaps with and contacts the second portion 619 of the contact pad 606.

[0106] Additionally, after providing the first dielectric layer 612 and partially removing it to expose the contact pads 606, a mold protection layer 614 can be provided on the second surface 607 of the semiconductor die 604. The mold protection layer 614 is provided adjacent to the outer periphery of the semiconductor die 604. In one embodiment, the mold protection layer 614 surrounds the semiconductor die 604 to provide protection on the sidewalls of the semiconductor structure. For example, as shown, the mold protection layer 614 is positioned to cover the second surface 607 of the semiconductor die 604, the sidewalls of the passivation layer 608, and the sidewalls of the first dielectric layer 612. The process of forming the mold protection layer 614 can be performed using, for example, a compression molding process. This process is used to encapsulate the semiconductor die 604 with a molding compound while protecting the active surfaces of the die. For example, the molding compound can surround all exposed silicon die surfaces, ignoring certain surfaces of the die. In some embodiments, the process of forming the mold protection layer 614 can be omitted based on industrial design requirements.

[0107] Return to reference Figure 6FA redistribution layer 616 is provided on a portion of the contact pad 606 and the first dielectric layer 612. In one embodiment, the redistribution layer 616 is disposed on the contact pad 606, the first dielectric layer 612, and the mold protection layer 614. For example, the redistribution layer 616 contacts a third portion 621 of the contact pad 606 and overlaps with the passivation layer 608, the first dielectric layer 612, and the mold protection layer 614. A second portion 619 of the contact pad 606 is located between the first portion 617 and the third portion 621 of the pad 606. In one embodiment, the redistribution layer 616 includes an extension 626. In this embodiment, the redistribution layer 616 extends over the mold protection layer 614, completely covering the mold protection layer 614, and contacts the carrier substrate 602. The extension 626 of the redistribution layer 616 extends along the second surface 607 of the semiconductor die 604, thereby preventing the passivation layer 608, the first dielectric layer 612, and the mold protection layer 614 from being directly exposed.

[0108] In one embodiment, the redistribution layer 616 may be formed on one side of the semiconductor die 604. However, in a different embodiment, the other end of the redistribution layer 616 may extend to the other side surface of the semiconductor die 604. That is, the redistribution layer 616 may extend along both sides of the semiconductor die 604 to provide electrical contacts on both sidewalls.

[0109] exist Figure 6F In the previous section, the extension 626 of the redistribution layer 616 was explained relative to a semiconductor die 604 without a lip portion (not shown). However, the same process for forming layers on the semiconductor die 604 can be applied to a die with a lip portion. In some embodiments, where the semiconductor die has a lip portion, the redistribution layer 616 may extend along the second surface of the semiconductor die 604 and, for the sidewalls, just above the lip portion, thus exposing the lip portion of the semiconductor die 604. For example, the redistribution layer 616 may not extend all the way down along the second surface 607 (e.g., the sidewall) and cover the lip portion of the semiconductor die 604. It may extend to cover the sides of the mold protection layer 614, which covers the sides of the passivation layer 608 and the first dielectric layer 612, but leaving the lip portion of the semiconductor die 604 exposed.

[0110] exist Figure 6GIn this embodiment, a second dielectric layer 618 is provided on the redistribution layer 616. In one embodiment, the second dielectric layer 618 overlaps with the contact pad 606, passivation layer 608, first dielectric layer 612, and redistribution layer 616. In one embodiment, the second dielectric layer 618 may only contact a portion of the redistribution layer 616. The second dielectric layer 618 may be made of the same material as the first dielectric layer 612 and may be deposited using the same method. The second dielectric layer 618 may be made of, but is not limited to, materials such as PBO or PI.

[0111] exist Figure 6H In this embodiment, a UBM 620 is provided on the second dielectric layer 618. In one embodiment, the UBM 620 is in direct contact with the redistribution layer 616 at a location spaced apart from the contact pad 606. For example, the redistribution layer 616 may be electrically and physically connected to the contact pad 606. This connection allows conductive structures such as the UBM 620 to provide electrical signals to other input / output terminals, such as those on a PCB or other external circuitry (not shown). In this embodiment, the UBM 620 is located on the second dielectric layer 618 that does not overlap with the contact pad 606. However, in another embodiment, the location of the UBM 620 may overlap with the contact pad 606 or be located at a different location depending on any design requirements. For example, the UBM 620 may be made of a metal, including but not limited to, Ni, Al, Cu, Cr, Ti, or any combination thereof.

[0112] exist Figure 6I In this embodiment, solder balls 622 are provided on the UBM 620. Solder balls 622 may include any conductive material capable of conducting electrical signals, and may include, for example, solder bumps, solder joints, wire bonds, etc. Any structure capable of conducting electrical signals will satisfy, and is not limited to, solder balls.

[0113] Figure 7 A cross-sectional view of scribed adjacent semiconductor structures according to an embodiment of the present disclosure is shown.

[0114] exist Figure 7 The image shows a semiconductor structure 700 with two silicon dies, a first semiconductor die 704 and a second semiconductor die 804 placed adjacent to each other. It will be apparent to those skilled in the art that multiple semiconductor dies are mounted on a carrier substrate 702, 802 of a wafer. In this embodiment, as... Figure 7As shown, two silicon dies are attached to a carrier substrate. A first semiconductor die 704 is attached to a first carrier substrate 702, and a second semiconductor die 804 is attached to a second carrier substrate 802. The first carrier substrate 702 and the second carrier substrate 802 can be identical and can form a large single carrier substrate. The carrier substrate can have multiple semiconductor dies placed on top of the carrier substrate.

[0115] The semiconductor structure built on top of the carrier substrate 802 can be formed based on the same or similar processes used to form the semiconductor structure built on top of the carrier substrate 702. For example, contact pads (not shown), passivation layer 808, first dielectric layer 812, mold protection layer 814, redistribution layer 816, second dielectric layer 818, UBM 820, and solder balls 822 can be formed in the same or similar manner as explained in the previous embodiments.

[0116] In other embodiments, the process of forming contact pads 706, passivation layer 708, first dielectric layer 712, mold protection layer 714, redistribution layer 716, second dielectric layer 718, UBM 720, solder balls 722, etc., on semiconductor die 704 can be performed in a single, unified process for multiple semiconductor dies mounted on a carrier substrate. For example, the aforementioned elements and layers can be formed in a single process for each of the multiple semiconductor dies mounted on the carrier substrate. Thus, the same elements and layers formed on semiconductor die 704 will be formed on adjacent semiconductor dies 804 and on any other multiple semiconductor dies mounted on carrier substrates 702, 802. For example, passivation layer 708 in the first semiconductor die 704 can be formed in the same process as passivation layer 808 in the second semiconductor die 804. Passivation layers for all other semiconductor dies (not shown) on carrier substrates 702, 802 can also be formed in the same single process.

[0117] An exemplary method for forming an extended redistribution layer on a semiconductor die is to form the redistribution layer on each of a plurality of semiconductor dies on a reconstructed wafer. In the reconstructed wafer, a plurality of semiconductor dies are mounted on the reconstructed wafer and spaced apart from each of the plurality of semiconductor dies. The process of forming various layers on top of the plurality of semiconductor dies is as explained in conjunction with previous embodiments. After forming various layers (e.g., contact pads, passivation layers, first dielectric layers, mold protection layers, redistribution layers, second dielectric layers, UBMs, solder balls, etc.), the semiconductor die with the redistribution layer and the adjacent semiconductor die with the redistribution layer are picked up and removed from a carrier substrate (not shown).

[0118] In other embodiments, the semiconductor die may have lip portions 705, 805, and the lip portion 705 of one semiconductor die 704 may be connected to the lip portion 805 of an adjacent semiconductor die 804, such as... Figure 7 As shown. For these semiconductor dies, another exemplary method can be used to form an extended redistribution layer on the semiconductor die. This exemplary method includes forming a redistribution layer on each of a plurality of semiconductor dies on a half-cut wafer, and scribing a lip portion of each of adjacent semiconductor dies.

[0119] For example, in Figure 7 In this process, the first semiconductor die 704 is connected to the second semiconductor die 804 via their respective lip portions 705, 805. The process of forming various layers on the first semiconductor die 704 and the second semiconductor die 804 includes the same or similar process as explained in connection with the relevant prior embodiments. After forming various layers (e.g., contact pads, passivation layers, first dielectric layers, mold protection layers, redistribution layers, second dielectric layers, UBM, solder balls, etc.), the first semiconductor die 704 and the adjacent second semiconductor die 804 are cut along a scribing line 710. The scribing line 710 cuts between the lip portion 705 of the first semiconductor die 704 and the lip portion 805 of the second semiconductor die 804. After cutting along the scribing line 710 on the half-cut wafer, the first semiconductor die 704 and the adjacent second semiconductor die 804 are separated. Other semiconductor dies mounted on the carrier substrate are cut in a similar manner. After each of the multiple semiconductor dies is monolithically converted into an individual semiconductor die, the individual dies are removed from the carrier substrates 702 and 802. Each semiconductor die includes an extended redistribution layer that allows for large contact areas at the chip sidewalls.

[0120] The various embodiments described above can be combined to provide other embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned in this specification and / or listed in the application data sheets are incorporated herein by reference in their entirety. If it is necessary to employ concepts from various patents, applications, and publications to provide other embodiments, aspects of the embodiments may be modified.

[0121] These and other changes can be made to the embodiments based on the specific implementation described above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and equivalents of the claims within their full scope. Therefore, the claims are not limited by the disclosure.

Claims

1. A device comprising: A semiconductor die includes a first surface and a second surface transverse to the first surface; Contact pads are placed on the first surface of the semiconductor die. A redistribution layer is provided on the first surface of the semiconductor die and the contact pads, the redistribution layer having an extension portion extending from the contact pads to the second surface of the semiconductor die, the extension portion including a first electrical contact on the second surface of the semiconductor die. as well as A conductive structure, spaced apart from the contact pads on the redistribution layer, the conductive structure including a second electrical contact on the first surface of the semiconductor die.

2. The device according to claim 1, wherein the second electrical contact comprises an under-bump metal structure, a solder ball, or a solder bump.

3. The device of claim 1, wherein the first electrical contact and the second electrical contact provide different electrical signals to each other.

4. The device of claim 1, wherein the semiconductor die includes a third surface opposite to the first surface, and the extension extends over the first surface to the third surface of the semiconductor die.

5. The device of claim 1, wherein the extension covers the second surface from the first surface to the third surface of the semiconductor die.

6. The device according to claim 1, further comprising: A passivation layer is provided between the redistribution layer and the semiconductor die, and the passivation layer overlaps with a first portion of the contact pad.

7. The device according to claim 6, further comprising: A first dielectric layer is located between the redistribution layer and the passivation layer. The first dielectric layer overlaps with a second portion of the contact pad. The second portion is located between a first portion of the contact pad and a third portion of the contact pad. The third portion of the contact pad is in contact with the redistribution layer.

8. The device according to claim 7, further comprising: A second dielectric layer is placed on the redistribution layer; as well as The conductive structure includes: A metallization layer, which is spaced apart from the contact pads on the redistribution layer.

9. The device according to claim 1, further comprising: A mold protection layer is provided between the second surface of the semiconductor die and the extension of the redistribution layer.

10. A device comprising: The first semiconductor die includes a first surface, a second surface, and a third surface; A first redistribution layer is disposed on the first surface of the first semiconductor die, the first redistribution layer having an extension portion extending from the first surface to the second surface; The second semiconductor die includes a fourth surface, a fifth surface, and a sixth surface, wherein the fourth surface of the second semiconductor die faces the third surface of the first semiconductor die; A second redistribution layer is disposed on the sixth surface of the second semiconductor die, the second redistribution layer having an extension portion extending from the sixth surface to the fifth surface.

11. The device according to claim 10, further comprising: A conductive connection is provided to electrically connect the first redistribution layer and the second redistribution layer.

12. The device of claim 11, wherein the conductive connection comprises a solder bump, a solder joint, a solder ball, or a wire bond.

13. The device of claim 10, wherein the second surface of the first semiconductor die and the fifth surface of the semiconductor die are coplanar.

14. A method comprising: Contact pads are formed on the first surface of the first semiconductor die; A first redistribution layer is formed on the first surface of the first semiconductor die and the contact pad, comprising: An extension portion of the first redistribution layer is formed, the extension portion of the first redistribution layer extending from the contact pad to a second surface of the first semiconductor die, the second surface being transverse to the first surface; as well as A conductive structure spaced apart from the contact pads is formed on the first redistribution layer.

15. The method of claim 14, further comprising: A second redistribution layer is formed on a fourth surface of the second semiconductor die, comprising: forming an extension portion of the second redistribution layer, the extension portion of the second redistribution layer extending from the fourth surface to a fifth surface of the second semiconductor die. An adhesive layer is formed between the first semiconductor die and the second semiconductor die.

16. The method of claim 15, further comprising: An extension portion of the first redistribution layer is formed on the second surface of the first semiconductor die, and an extension portion of the second redistribution layer is formed on the fifth surface of the second semiconductor die, wherein the extension portion of the first redistribution layer is aligned with the extension portion of the second redistribution layer.

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