Method and system for banknote counterfeiting identification

Abstract

The present invention discloses a method and system for counterfeit identification of banknotes, comprising the following steps: determining the currency type and currency value of the banknote to be identified; collecting magnetic information on the banknote and outputting a corresponding analog signal; amplifying the analog signal; converting the amplified analog signal into a digital signal; comparing the digital signal with a template; if the digital signal matches the template, the banknote is identified as authentic; if the digital signal does not match the template, the banknote is identified as fake; there are at least two selectable magnifications for the analog signal and at least two templates; before banknote detection, the magnification of the analog signal is adjusted according to the currency type of the banknote, and the template for comparison with the digital signal is adjusted according to the currency value of the banknote. The present invention adjusts the magnification of the signal gain channel according to different currencies, optimizes and corrects the analog signals corresponding to different currencies collected by the magnetic sensor to the signal range that can be processed by the MCU, so that multiple currencies can be identified by one device, reducing the cost of counterfeit identification and being more convenient to use.

Description

Technical Field

[0001] The present invention relates to the technical field of banknote detection, and more particularly to a method and system for counterfeit identification of banknotes. Background Art

[0002] In order to obtain illegal profits, criminals have produced a large number of highly realistic counterfeit banknotes for circulation in the market. In order to maintain market order and security, many methods of banknote counterfeiting have been developed, including methods and equipment that use magnetic information to detect banknotes.

[0003] At present, the methods and equipment for monitoring banknotes with magnetic information are designed for specific currencies. However, with China's entry into the WTO, exchanges and cooperation between China and other countries in the world have become more frequent, so there is a need for a banknote counterfeit detection system that can detect different currencies. However, due to the different banknote production standards between different currencies in different countries, the magnetic information contained in the banknotes is different. When using the same magnetic information collection system, the characteristics and strength of the output signals vary greatly, which exceeds the collection and processing range of the MCU. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present application provides a method and system for banknote counterfeiting identification.

[0005] A first aspect of the present invention provides a method for counterfeiting banknotes, comprising the following steps:

[0006] Determine the currency and / or denomination of the banknote to be authenticated;

[0007] Collect magnetic information on banknotes and output corresponding analog signals;

[0008] amplifying the analog signal;

[0009] Converting the amplified analog signal into a digital signal;

[0010] comparing the digital signal with a template;

[0011] If the digital signal matches the template, the banknote is authenticated as authentic;

[0012] If the digital signal does not match the template, the banknote is identified as fake;

[0013] There are at least two selectable amplification factors for the analog signal;

[0014] Before banknote detection, adjusting the amplification factor of the analog signal according to the type of banknote;

[0015] Before the banknote is detected, the template for comparison with the digital signal is adjusted according to the banknote value.

[0016] In a preferred embodiment, the method of "determining the currency type and / or currency value of the banknote to be verified" includes:

[0017] One or more characteristic regions are preset for different currencies and / or ratios. When a characteristic region that meets the currency requirements is detected, the currency and / or value of the banknote to be authenticated is determined.

[0018] For example, the characteristic area of ​​each currency type may be a characteristic pattern of a specific area, and whether the specific area has a corresponding characteristic pattern is detected. If so, the currency type of the banknote to be authenticated can be determined.

[0019] Likewise, the characteristic area of ​​the currency value may also be a characteristic pattern of a specific area, or even the size of a banknote.

[0020] Preferably, detecting whether a corresponding characteristic pattern exists in a specific area may be performed by scanning and identifying a pattern.

[0021] Preferably, the analog signal is amplified twice or more.

[0022] Preferably, the analog signal is filtered before each amplification.

[0023] Preferably, the analog signal has at least one amplification whose amplification factor can be adjusted according to the currency type.

[0024] Preferably, there are at least two types of templates.

[0025] Preferably, the magnetic information on the banknote is collected by a magnetic sensor.

[0026] Preferably, the magnetic sensor outputs a corresponding analog signal.

[0027] Preferably, the analog signal output by the magnetic sensor is amplified through a signal gain channel.

[0028] Preferably, the signal gain channel comprises two or more amplifier circuits connected in sequence.

[0029] Preferably, the amplification factors of the last amplification circuit in the signal gain channel from upstream to downstream include two or more.

[0030] Preferably, the analog signal is converted into a digital signal by an ADC module.

[0031] Preferably, the template is stored in the MCU.

[0032] Preferably, the MCU receives a digital signal and determines the authenticity of the banknote by matching a template with the digital signal.

[0033] The second aspect of the present invention provides a system for counterfeit identification of banknotes, comprising: a magnetic sensor, a signal gain channel, an ADC (analog-to-digital conversion) module, and an MCU (microcontroller unit);

[0034] The magnetic sensor, signal gain channel, ADC conversion module and MCU are connected in sequence;

[0035] At least two templates are preset in the MCU, and the templates can be selected;

[0036] The signal gain channel can be amplified by at least two multiples, and the amplification multiples are selectable;

[0037] Wherein, the magnetic sensor is used to collect magnetic information on banknotes and output corresponding analog signals;

[0038] The signal gain channel is used to amplify the analog signal output by the magnetic sensor;

[0039] The ADC module is used to convert analog signals into digital signals;

[0040] The MCU is used to receive digital signals and determine the authenticity of banknotes by matching templates with the digital signals.

[0041] Preferably, in the above content of the present application, the signal gain channel includes a pre-stage amplifier circuit and a post-stage amplifier circuit, and the magnetic sensor, the pre-stage amplifier circuit, the post-stage amplifier circuit, and the ADC module are connected in sequence.

[0042] Preferably, in the above content of the present application, the amplification factor of the front-stage amplifier circuit is fixed, and the amplification factor of the rear-stage amplifier circuit has at least two types.

[0043] Preferably, in the above content of the present application, the post-stage amplifier circuit is connected to the ADC module through an adapter.

[0044] Preferably, in the above content of the present application, the pre-amplifier circuit includes an operational amplifier A1, a capacitor C01, a resistor R01, a capacitor C02, a resistor C02, a capacitor C03, a resistor R03, a capacitor C04, and a resistor R04;

[0045] The capacitor C01 is connected in series with the resistor R01, one end of the capacitor C01 is connected to the magnetic sensor, and the other end is connected to the in-phase input terminal of the operational amplifier A1 through the resistor R01;

[0046] The capacitor C02 is connected in series with the resistor R02, one end of the capacitor C02 is connected to the magnetic sensor, and the other end is connected to the inverting input terminal of the operational amplifier A1 through the resistor R02;

[0047] The capacitor C03 is connected in parallel with the resistor R03, one end of the capacitor C03 is connected to the in-phase input end of the operational amplifier A1, and the other end is externally connected to the reference voltage VrefA;

[0048] The capacitor C04 is connected in parallel with the resistor R04, one end of the capacitor C04 is connected to the inverting input end of the operational amplifier A1, and the other end is connected to the output end of the operational amplifier A1 to provide feedback;

[0049] The analog signal is filtered by capacitors C01 and C02 and then enters the non-inverting input terminal and the inverting input terminal of the operational amplifier A1 respectively.

[0050] Preferably, in the above content of the present application, the post-stage amplifier circuit includes an operational amplifier A2, a capacitor C05, a resistor R05, a capacitor C06, a resistor C06, a capacitor C07, and a variable resistance element;

[0051] The capacitor C05 is connected in series with the resistor R05, one end of the capacitor C05 is connected to the output end of the pre-amplifier circuit, and the other end is connected to the inverting input end of the operational amplifier A2 through the resistor R05;

[0052] The capacitor C06 is connected in parallel with the resistor R06, one end of the capacitor C06 is connected to the in-phase input end of the operational amplifier A2, and the other end is externally connected to the reference voltage VrefB;

[0053] The capacitor C07 is connected in parallel with the variable resistance element, one end of the capacitor C07 is connected to the inverting input end of the operational amplifier A2, and the other end is connected to the output end OUT of the operational amplifier A2 to provide feedback;

[0054] The variable resistance element can be set to have at least two resistance values.

[0055] Preferably, in the above content of the present application, the variable resistance element includes a digital potentiometer, and the digital potentiometer changes the resistance value by receiving MCU parameters.

[0056] Preferably, in the above content of the present application, the digital potentiometer receives the parameters sent by the MCU through an adapter.

[0057] Preferably, in the above content of the present application, there are one or more magnetic sensors.

[0058] Preferably, in the above content of the present application, the number of magnetic sensors is equal to the number of signal gain channels.

[0059] Preferably, in the above content of the present application, the reference voltage VrefA and the reference voltage VrefB are provided by a reference voltage circuit.

[0060] Preferably, in the above content of the present application, the reference voltage circuit includes a resistor Ra, a resistor Rb, a capacitor Cb, an operational amplifier A3, a resistor Rc, a capacitor Cc, an operational amplifier A4, a resistor Rd, and a capacitor Cd;

[0061] The resistor Ra is connected in series with the resistor Rb, one end of the resistor Ra away from the resistor Rb is connected to an external voltage, one end of the resistor Rb away from the resistor Ra is grounded, and the capacitor Cb is connected in parallel with the resistor Rb;

[0062] One end of the resistor Rb close to the resistor Ra is connected to the non-inverting input terminal of the operational amplifier A3 and the non-inverting input terminal of the operational amplifier A4 respectively;

[0063] One end of the resistor Rc is connected to the output end of the operational amplifier A3, and the other end is connected to the inverting input end of the operational amplifier A3 to form a voltage follower;

[0064] One end of the resistor Rd is connected to the output end of the operational amplifier A4, and the other end is connected to the inverting input end of the operational amplifier A4 to form a voltage follower;

[0065] One end of the capacitor Cc is connected to the output end of the operational amplifier A3, and the other end is grounded. The connection point between the capacitor Cc and the output end of the operational amplifier A3 is located after the connection point between the resistor Rc and the output end of the operational amplifier A3;

[0066] One end of the capacitor Cd is connected to the output end of the operational amplifier A4, and the other end is grounded. The connection point between the capacitor Cd and the output end of the operational amplifier A4 is located after the connection point between the resistor Rd and the output end of the operational amplifier A4;

[0067] The output end of the operational amplifier A3 is connected to the resistor R03 after filtering by the capacitor Cc, providing a reference voltage VrefA for the front-stage amplifier circuit. The output end of the operational amplifier A4 is connected to the resistor R06 after filtering by the capacitor Cd, providing a reference voltage VrefB for the back-stage amplifier circuit.

[0068] Preferably, in the above content of the present application, the capacitor Cc and the capacitor Cd are polar capacitors.

[0069] Preferably, in the above content of the present application, the operational amplifier A1 and the operational amplifier A2 are provided by an operational amplifier chip.

[0070] Preferably, in the above content of the present application, the operational amplifier chip model is MCP6004, and four operational amplifiers are encapsulated in the operational amplifier chip, and the four operational amplifiers are independent of each other, wherein pins 1 to 3, pins 5 to 7, pins 8 to 10, and pins 12 to 14 in the operational amplifier chip correspond to an operational amplifier respectively.

[0071] Preferably, in the above content of the present application, pin 7 is the signal output terminal of the operational amplifier chip, and pin 8 is the signal output terminal of the operational amplifier chip.

[0072] Preferably, in the above content of the present application, the two signal gain channels share one operational amplifier chip.

[0073] Preferably, in the above content of the present application, the two operational amplifiers corresponding to pins 1 to 3 and pins 5 to 7 in the operational amplifier chip supply the same signal gain channel, and the two operational amplifiers corresponding to pins 8 to 10 and pins 12 to 14 supply another signal gain channel.

[0074] Preferably, in the above content of the present application, pin 1 is externally connected to capacitor C05, resistor R04, and capacitor C04, pin 2 is externally connected to resistor R02, resistor R04, and capacitor C04, pin 3 is externally connected to resistor R01, resistor R03, and capacitor R03, pin 5 is externally connected to resistor C06 and capacitor C06, and pin 6 is externally connected to resistor R05, capacitor C07, and a variable resistor element.

[0075] Preferably, in the above content of the present application, pin 14 is externally connected to capacitor C05, resistor R04, and capacitor C04, pin 13 is externally connected to resistor R02, resistor R04, and capacitor C04, pin 12 is externally connected to resistor R01, resistor R03, and capacitor R03, pin 10 is externally connected to resistor C06 and capacitor C06, and pin 9 is externally connected to resistor R05, capacitor C07, and a variable resistor element.

[0076] Preferably, in the above content of the present application, the digital potentiometer is a dual-channel digital potentiometer, and preferably, the digital potentiometer model is TPL0102.

[0077] Preferably, in the above content of the present application, the digital potentiometer with model number TPL0102 has an SDA pin, an SCL pin, two groups of HA pins and a WA pin, wherein the SDA pin and the SCL pin are connected to the adapter, the two groups of HA pins and the WA pin are respectively connected to the two signal gain channels, and the two groups of HA pins and the WA pin adjust the two signal gain channels simultaneously.

[0078] Preferably, in the above content of the present application, the HA pin in one group is connected to pin 7 in the MCP6004 operational amplifier chip, and the WA pin is connected to pin 6, and the HA pin in another group is connected to pin 8 in the MCP6004 operational amplifier chip, and the WA pin is connected to pin 9.

[0079] Preferably, in the above content of the present application, the capacitor C01, capacitor C02, and capacitor C05 are polar capacitors.

[0080] Preferably, in the above content of the present application, there are one or more adapters.

[0081] Preferably, in the above content of the present application, the output ends of the plurality of signal gain channels are respectively connected to the ADC module through adapters.

[0082] Preferably, in the above content of the present application, the SCL pins and SDA pins of the plurality of digital potentiometers are first connected in parallel and then connected to the MCU through an adapter.

[0083] Preferably, in the above content of the present application, the MCU pre-stores the operational amplifier gain parameters corresponding to each currency type, and before detection, the corresponding parameters are sent to the digital potentiometer through manual selection.

[0084] Preferably, in the above content of the present application, the MCU pre-stores templates corresponding to different values ​​of various currencies. Before detection, the template is manually selected and the digital signal is waited for to be transmitted for comparison.

[0085] In the above content of this application, each preferred solution can be combined with each other.

[0086] The method and system for banknote counterfeiting provided by the present invention can adjust the amplification factor of the signal gain channel according to different currencies, optimize and correct the analog signals corresponding to different currencies collected by the magnetic sensor to the signal range that can be processed by the MCU, so that multiple currencies can be authenticated by one device, reducing the cost of authentication and making it more convenient to use. BRIEF DESCRIPTION OF THE DRAWINGS

[0087] Figure 1 It is a schematic diagram of the process of the method for counterfeit identification of banknotes of the present invention;

[0088] Figure 2 It is a schematic diagram of the flow of the system for banknote counterfeiting identification of the present invention;

[0089] Figure 3 It is a circuit diagram of a magnetic sensor and a signal gain channel in a system for counterfeit identification of banknotes of the present invention;

[0090] Figure 4 It is a circuit diagram of a reference voltage divider circuit in a system for counterfeit identification of banknotes of the present invention;

[0091] Figure 5 It is a schematic diagram of the structure of an operational amplifier chip in a system for banknote counterfeiting detection according to the present invention;

[0092] Figure 6 The invention is a schematic diagram of the connection of the adapter in the system for banknote counterfeiting identification. DETAILED DESCRIPTION

[0093] The present invention is further described in detail below in conjunction with the accompanying drawings.

[0094] Embodiment 1, a method for detecting counterfeit banknotes, Figure 1 As shown, the following steps are included:

[0095] Collect the magnetic information on the banknotes and output the corresponding analog signal.

[0096] Filters analog signals.

[0097] Amplify the analog signal once.

[0098] Filters analog signals.

[0099] The analog signal is amplified secondary according to the currency type.

[0100] Convert the amplified and filtered analog signal into a digital signal.

[0101] The digital signal is compared with a corresponding template according to the currency value.

[0102] If the digital signal matches the template, the banknote is authenticated as authentic.

[0103] If the digital signal does not match the template, the banknote is authenticated as counterfeit.

[0104] There are at least two selectable amplification factors for the analog signal, and at least two templates for matching with the digital signal.

[0105] Before banknote inspection, the staff needs to determine the currency and value of the banknote to be inspected, and before inspection, adjust the amplification factor of the analog signal according to the currency type of the banknote, and adjust the comparison template of the digital signal according to the value of the banknote.

[0106] Embodiment 2, a system for detecting counterfeit banknotes, such as Figure 2 As shown, it includes a magnetic sensor, a signal gain channel, an ADC (analog-to-digital conversion) module, and an MCU (microcontroller unit), wherein the signal gain channel includes a pre-stage amplifier circuit and a post-stage amplifier circuit, and the magnetic sensor, the pre-stage amplifier circuit, the post-stage amplifier circuit, the ADC module, and the MCU are connected in sequence.

[0107] Among them, the magnetic sensor is used to collect magnetic information on banknotes and output corresponding analog signals.

[0108] The pre-amplifier circuit is used to filter and once amplify the analog signal output by the magnetic sensor, and the amplification factor of the pre-amplifier circuit is fixed.

[0109] The post-stage amplifier circuit is used to filter and perform secondary amplification on the analog signal output by the pre-stage amplifier circuit, and the amplification factor of the post-stage amplifier circuit is adjustable.

[0110] The post-amplifier circuit transfers the analog signal to the ADC module through the adapter.

[0111] The ADC module is used to convert analog signals into digital signals.

[0112] The MCU receives the digital signal and determines the authenticity of the banknote by matching the template with the digital signal, wherein the number of the templates is at least two and they are preset in the MCU.

[0113] The MCU pre-stores the operational amplifier gain parameters corresponding to each currency type. Before verification, the MCU will send the parameters to the post-amplifier circuit to adjust the amplification factor of the post-amplifier circuit according to the currency type of the banknote.

[0114] The MCU has pre-stored templates corresponding to different currency values. Before verification, the MCU will adjust the templates according to the banknote value.

[0115] like Figure 3 As shown, the magnetic sensor is provided with an S+ terminal and an S- terminal, wherein the S+ terminal and the S- terminal are connected to a signal gain channel for outputting an analog signal to the signal gain channel.

[0116] The pre-amplifier circuit includes an operational amplifier A1, a capacitor C01, a resistor R01, a capacitor C02, a resistor C02, a capacitor C03, a resistor R03, a capacitor C04, and a resistor R04.

[0117] The capacitor C01 is connected in series with the resistor R01, one end of the capacitor C01 is connected to the S+ end of the magnetic sensor, and the other end of the capacitor C01 is connected to the in-phase input end of the operational amplifier A1 through the resistor R01.

[0118] The capacitor C02 is connected in series with the resistor R02. One end of the capacitor C02 is connected to the S-terminal of the magnetic sensor, and the other end is connected to the inverting input terminal of the operational amplifier A1 through the resistor R02.

[0119] The analog signal input to the pre-amplifier circuit enters the operational amplifier A1 after being filtered by capacitors C01 and C02.

[0120] The capacitor C03 is connected in parallel with the resistor R03 , one end of the capacitor C03 is connected to the non-inverting input end of the operational amplifier A1 , and the other end of the capacitor C03 is externally connected to a reference voltage VrefA.

[0121] The capacitor C04 is connected in parallel with the resistor R04 , one end of the capacitor C04 is connected to the inverting input end of the operational amplifier A1 , and the other end of the capacitor C04 is connected to the output end of the operational amplifier A1 to provide feedback.

[0122] The reference voltage VrefA ensures that the analog signal level outputted from the output terminal of the operational amplifier A1 is positive. Since the amplification factor of the pre-stage amplifier circuit depends on the ratio between the resistor R04 and the resistor R02, and the resistor R04 and the resistor R02 are fixed resistors, the amplification factor of the pre-stage amplifier circuit remains unchanged.

[0123] The post-amplification circuit includes an operational amplifier A2, a capacitor C05, a resistor R05, a capacitor C06, a resistor C06, a capacitor C07, and a variable resistance element, wherein the resistance value of the variable resistance element is adjustable.

[0124] The capacitor C05 is connected in series with the resistor R05. One end of the capacitor C05 is connected to the output end of the pre-amplifier circuit, and the other end of the resistor C05 is connected to the inverting input end of the operational amplifier A2 through the resistor R05.

[0125] The analog signal output by the pre-amplifier circuit is filtered by capacitor C05 and then enters operational amplifier A2.

[0126] The capacitor C06 is connected in parallel with the resistor R06 , one end of the capacitor C06 is connected to the non-inverting input end of the operational amplifier A2 , and the other end of the capacitor C06 is externally connected to a reference voltage VrefB.

[0127] The capacitor C07 is connected in parallel with the digital potentiometer, one end of the capacitor C07 is connected to the inverting input terminal of the operational amplifier A2, and the other end of the capacitor C07 is connected to the output terminal OUT of the operational amplifier A2 to provide feedback.

[0128] The reference voltage VrefB ensures that the analog signal level output by the output terminal OUT of the operational amplifier A2 is positive. Since the amplification factor of the post-stage amplifier circuit depends on the ratio between the variable resistance element and the resistor R05, and the resistor R05 is a fixed resistor, the resistance value of the variable resistance element can be adjusted, thus achieving adjustable amplification factor of the post-stage amplifier circuit.

[0129] The reference voltage VrefA and the reference voltage VrefB are provided by a reference voltage circuit.

[0130] like Figure 4 As shown, the reference voltage circuit includes a resistor Ra, a resistor Rb, a capacitor Cb, an operational amplifier A3, a resistor Rc, a capacitor Cc, an operational amplifier A4, a resistor Rd, and a capacitor Cd.

[0131] The resistor Ra is connected in series with the resistor Rb. One end of the resistor Ra away from the resistor Rb is connected to an external voltage. One end of the resistor Rb away from the resistor Ra is grounded. The capacitor Cb is connected in parallel with the resistor Rb.

[0132] One end of the resistor Rb close to the resistor Ra is connected to the non-inverting input terminal of the operational amplifier A3 and the non-inverting input terminal of the operational amplifier A4 respectively.

[0133] One end of the resistor Rc is connected to the output end of the operational amplifier A3, and the other end of the resistor Rc is connected to the inverting input end of the operational amplifier A3 to form a voltage follower.

[0134] One end of the resistor Rd is connected to the output end of the operational amplifier A4, and the other end of the resistor Rd is connected to the inverting input end of the operational amplifier A4 to form a voltage follower.

[0135] One end of the capacitor Cc is connected to the output end of the operational amplifier A3, and the other end is grounded. The connection point between the capacitor Cc and the output end of the operational amplifier A3 is located after the connection point between the resistor Rc and the output end of the operational amplifier A3.

[0136] One end of the capacitor Cd is connected to the output end of the operational amplifier A4, and the other end is grounded. The connection point between the capacitor Cd and the output end of the operational amplifier A4 is located after the connection point between the resistor Rd and the output end of the operational amplifier A4.

[0137] The output of operational amplifier A3 is connected to resistor R03 after filtering by capacitor Cc, providing reference voltage VrefA for the front-stage amplifier circuit. The output of operational amplifier A4 is connected to resistor R06 after filtering by capacitor Cd, providing reference voltage VrefB for the back-stage amplifier circuit.

[0138] Capacitor Cc and capacitor Cd are polarized capacitors.

[0139] In this embodiment, the width of a single magnetic track of the magnetic sensor used is 10 mm. Considering that the width of international currency does not exceed 180 mm, in order to verify banknotes of different widths, such as Figure 2 As shown, 18 parallel magnetic sensors are set up to collect magnetic information. The 18 parallel magnetic sensors can cover a coin surface with a maximum width of 180 mm. The number of magnetic sensors corresponds to the number of signal gain channels. The analog signals generated by the 18 semiconductor magnetic sensors are received by 18 parallel signal gain channels. The 18 signal gain channels have the same configuration and the same amplification factor.

[0140] In this embodiment, the Figure 5 The operational amplifier chip model MCP6004 shown provides an operational amplifier for the signal gain channel. Four operational amplifiers are packaged in the operational amplifier chip, and the four operational amplifiers are independent of each other. Pins 1 to 3, pins 5 to 7, pins 8 to 10, and pins 12 to 14 in the operational amplifier chip correspond to one operational amplifier respectively.

[0141] The four operational amplifiers are divided into two groups, each supplying two signal gain channels, where the two operational amplifiers corresponding to pin 1 to pin 3 and pin 5 to pin 7 form a group;

[0142] In this group, the operational amplifier corresponding to pins 1 to 3 is operational amplifier A1, and the operational amplifier corresponding to pins 5 to 7 is operational amplifier A2;

[0143] Pin 1 is externally connected to capacitor C05, resistor R04, and capacitor C04 in the corresponding signal gain channel of this group, pin 2 is externally connected to resistor R02, resistor R04, and capacitor C04 in the signal gain channel of this group, pin 3 is externally connected to resistor R01, resistor R03, and capacitor R03 corresponding to this group, pin 5 is externally connected to resistor C06 and capacitor C06 corresponding to this group, pin 6 is externally connected to resistor R05, capacitor C07, and variable resistance element, and pin 7 is the signal output end.

[0144] The two operational amplifiers corresponding to pin 8 to pin 10 and pin 12 to pin 14 are a group;

[0145] In this group, the operational amplifier corresponding to pin 12 to pin 14 is operational amplifier A1, and the operational amplifier corresponding to pin 8 to pin 10 is operational amplifier A2;

[0146] Pin 14 is externally connected to capacitor C05, resistor R04, and capacitor C04 in the signal gain channel of this group, pin 13 is externally connected to resistor R02, resistor R04, and capacitor C04 corresponding to this group, pin 12 is externally connected to resistor R01, resistor R03, and capacitor R03 in the signal gain channel of this group, pin 10 is externally connected to resistor C06 and capacitor C06 corresponding to this group, pin 9 is externally connected to resistor R05, capacitor C07, and a digital potentiometer, and pin 8 is the signal output terminal.

[0147] Therefore, the 18 signal gain channels correspond to 9 MCP6004 op amp chips.

[0148] In this embodiment, if Figure 3 As shown, a dual-channel digital potentiometer of model TPL0102 is used as a variable resistance element. The TPL0102 digital potentiometer is a dual-channel digital potentiometer, which is provided with an SDA pin, an SCL pin, two groups of HA pins, an LA pin and a WA pin. The digital potentiometer can adjust the resistance between the HA pin and the WA pin by receiving parameters.

[0149] The two groups of HA pins and WA pins are connected to the two gain channels respectively, and the two groups of HA pins and WA pins simultaneously receive parameters to adjust the amplification factors of the two gain channels.

[0150] The HA pin in one group is connected to pin 7 of the MCP6004 operational amplifier chip, and the WA pin is connected to pin 6. The HA pin in the other group is connected to pin 8 of the MCP6004 operational amplifier chip, and the WA pin is connected to pin 9.

[0151] Therefore, 9 MCP6004 op amp chips correspond to 9 TPL0102 digital potentiometers.

[0152] like Figure 3 and Figure 6As shown, the adapter is respectively connected to 18 signal gain channels, 9 digital potentiometers, an ADC module and an MCU.

[0153] The analog signals output by the 18 signal gain channels are transferred to the ADC module through the adapter, and the MCU sends preset parameters to the SDA pin and SCL pin of the digital potentiometer through the adapter to control the resistance value of the digital potentiometer.

[0154] The analog signals output from the output end of the 18-way signal gain channel enter the ADC module through the adapter, are converted into digital signals, and then enter the MCU.

[0155] The MCU pre-stores the operational amplifier gain parameters corresponding to each currency type. Before detection, the corresponding parameters are sent to the digital potentiometer through the adapter through manual selection.

[0156] The MCU has pre-stored templates corresponding to different currency values ​​of various currencies. Before detection, the template is manually selected and the digital signal is waited for to be transmitted for comparison.

[0157] The method and system for banknote counterfeiting provided by the present invention can adjust the amplification factor of the signal gain channel according to different currencies, optimize and correct the analog signals corresponding to different currencies collected by the magnetic sensor to the signal range that can be processed by the MCU, so that multiple currencies can be authenticated by one device, reducing the cost of authentication and making it more convenient to use.

[0158] This specific implementation manner is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to this embodiment as needed, but such modifications are protected by patent law as long as they are within the scope of the claims of the present invention.

Claims

1. A system for banknote counterfeiting, characterized in that: Including magnetic sensor, signal gain channel, ADC module, MCU; The magnetic sensor, signal gain channel, ADC module and MCU are connected in sequence; The signal gain channel can be amplified by at least two multiples, and the amplification multiples are selectable; At least two templates are preset in the MCU, and the templates can be selected; Wherein, the magnetic sensor is used to collect magnetic information on banknotes and output corresponding analog signals; The signal gain channel is used to amplify the analog signal output by the magnetic sensor; The ADC module is used to convert analog signals into digital signals; The MCU is used to receive digital signals and determine the authenticity of banknotes by matching the template with the digital signals; The signal gain channel includes a pre-stage amplifier circuit and a post-stage amplifier circuit, and the magnetic sensor, the pre-stage amplifier circuit, the post-stage amplifier circuit, and the ADC module are connected in sequence; The amplification factor of the front-stage amplifier circuit is fixed, and the amplification factor of the rear-stage amplifier circuit has at least two types; The pre-amplifier circuit includes an operational amplifier A1, a capacitor C01, a resistor R01, a capacitor C02, a resistor C02, a capacitor C03, a resistor R03, a capacitor C04, and a resistor R04; The capacitor C01 is connected in series with the resistor R01, one end of the capacitor C01 is connected to the magnetic sensor, and the other end is connected to the in-phase input terminal of the operational amplifier A1 through the resistor R01; The capacitor C02 is connected in series with the resistor R02, one end of the capacitor C02 is connected to the magnetic sensor, and the other end is connected to the inverting input terminal of the operational amplifier A1 through the resistor R02; The capacitor C03 is connected in parallel with the resistor R03, one end of the capacitor C03 is connected to the in-phase input end of the operational amplifier A1, and the other end is externally connected to the reference voltage VrefA; The capacitor C04 is connected in parallel with the resistor R04, one end of the capacitor C04 is connected to the inverting input end of the operational amplifier A1, and the other end is connected to the output end of the operational amplifier A1 to provide feedback; The analog signal is filtered by capacitors C01 and C02 and enters the in-phase input terminal and the inverting input terminal of the operational amplifier A1 respectively; The post-amplification circuit includes an operational amplifier A2, a capacitor C05, a resistor R05, a capacitor C06, a resistor C06, a capacitor C07, and a variable resistance element; The capacitor C05 is connected in series with the resistor R05, one end of the capacitor C05 is connected to the output end of the pre-amplifier circuit, and the other end is connected to the inverting input end of the operational amplifier A2 through the resistor R05; The capacitor C06 is connected in parallel with the resistor R06, one end of the capacitor C06 is connected to the in-phase input end of the operational amplifier A2, and the other end is externally connected to the reference voltage VrefB; The capacitor C07 is connected in parallel with the variable resistance element, one end of the capacitor C07 is connected to the inverting input end of the operational amplifier A2, and the other end is connected to the output end OUT of the operational amplifier A2 to provide feedback; The variable resistance element can be set to at least two resistance values; The resistance value of the variable resistance element is controlled by the MCU, and the variable resistance element includes a digital potentiometer; The reference voltage VrefA and the reference voltage VrefB are provided by a reference voltage circuit; The reference voltage circuit includes a resistor Ra, a resistor Rb, a capacitor Cb, an operational amplifier A3, a resistor Rc, a capacitor Cc, an operational amplifier A4, a resistor Rd, and a capacitor Cd; The resistor Ra is connected in series with the resistor Rb, one end of the resistor Ra away from the resistor Rb is connected to an external voltage, one end of the resistor Rb away from the resistor Ra is grounded, and the capacitor Cb is connected in parallel with the resistor Rb; One end of the resistor Rb close to the resistor Ra is connected to the non-inverting input terminal of the operational amplifier A3 and the non-inverting input terminal of the operational amplifier A4 respectively; One end of the resistor Rc is connected to the output end of the operational amplifier A3, and the other end is connected to the inverting input end of the operational amplifier A3 to form a voltage follower; One end of the resistor Rd is connected to the output end of the operational amplifier A4, and the other end is connected to the inverting input end of the operational amplifier A4 to form a voltage follower; One end of the capacitor Cc is connected to the output end of the operational amplifier A3, and the other end is grounded. The connection point between the capacitor Cc and the output end of the operational amplifier A3 is located after the connection point between the resistor Rc and the output end of the operational amplifier A3; One end of the capacitor Cd is connected to the output end of the operational amplifier A4, and the other end is grounded. The connection point between the capacitor Cd and the output end of the operational amplifier A4 is located after the connection point between the resistor Rd and the output end of the operational amplifier A4; The output end of the operational amplifier A3 is connected to the resistor R03 after being filtered by the capacitor Cc, so as to provide a reference voltage VrefA for the pre-amplifier circuit; The output end of the operational amplifier A4 is connected to the resistor R06 after being filtered by the capacitor Cd, so as to provide a reference voltage VrefB for the subsequent amplifier circuit; There is one or more magnetic sensors, and the number of the magnetic sensors is equal to the number of signal gain channels.

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