Packaging structure for power converters

Abstract

The present invention provides a packaging structure suitable for a power converter, wherein a first power transistor and a control and drive circuit are integrated into the same chip, which can better realize the high-frequency switching action of the first power transistor, increase the operating frequency of the first power transistor, and reduce the switching loss. The second power transistor is integrated into an independent second chip, and the first chip and the second chip are separated in the packaging structure. The control and drive action of the second power transistor will not interfere with or have other negative effects on the first chip, thereby improving reliability. The first chip and the second chip can be connected through a large-area connection structure, achieving a lower interconnection resistance and improving the large current handling capability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a packaging structure applied to a power converter. Background Art

[0002] A power converter is a conversion circuit that converts an input voltage into a constant output voltage or output current. Depending on the magnitude relationship between the input voltage and the output voltage, the power converter can be set to different power topologies, such as buck, boost, or buck-boost. The same thing is that the power converter includes a main power switch and a rectifier switch, as well as an inductor and an output capacitor. Different power level topologies are obtained by different connection methods between the four basic components. The control and drive circuit controls the main power switch to operate in a high-frequency state, and controls the on-duty cycle of the main power switch according to the feedback information of the output voltage, so as to obtain a constant output voltage at the output end.

[0003] The development of electronic technology has led to higher and higher requirements for miniaturization and integration. Through the existing manufacturing process, the main power switch, rectifier switch and control and drive circuit can be manufactured separately, and then the main power switch, rectifier switch and control and drive circuit can be packaged in one chip through the packaging process. In this way, the chip area will inevitably be larger. Another way is to integrate the main power switch, rectifier switch and control and drive circuit, which can reduce the chip area, but the requirements for the manufacturing process are very high. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a novel packaging structure for a power converter that can take into account both miniaturization and manufacturing process difficulty.

[0005] According to one aspect of the present invention, there is provided a packaging structure applied to a power converter, comprising:

[0006] A first chip including at least a first power transistor and a first control and drive circuit;

[0007] A second chip including at least a second power transistor;

[0008] A connecting device, used to sequentially couple the first power transistor and the second power transistor in series between a high level pin and a low level pin of a lead frame of the packaging structure inside the packaging structure through the connecting device;

[0009] A common connection point of the first power transistor and the second power transistor is coupled to an output pin of the lead frame through a metal connection structure with low interconnect resistance.

[0010] Preferably, the second power transistor is configured as a power device with a vertical current flow direction.

[0011] Preferably, the connection between the first power transistor and the high level pin, and the connection between the second power transistor and the low level pin are realized by a metal connection structure with low interconnection resistance or by a stacked direct connection method.

[0012] Preferably, the metal connection structure with low interconnection resistance is configured as a sheet-like metal clip structure or a redistribution metal structure.

[0013] Preferably, the control electrode, the first power electrode and the second power electrode of the first power transistor are located on the same surface of the first wafer.

[0014] Preferably, the first power electrode and the second power electrode of the second power transistor are located on different surfaces of the second wafer.

[0015] Preferably, the first wafer and the second wafer are arranged in parallel.

[0016] Preferably, the connecting device comprises a metal clip structure to be electrically coupled to the second power electrode of the first power transistor and the first power electrode of the second power transistor through a welding layer, and connected to corresponding pins of a lead frame.

[0017] Preferably, the connecting device includes a metal redistribution structure, and the second electrode of the first power transistor and the first electrode of the second power transistor are connected to the metal redistribution layer through a welding process and connected to corresponding pins of the lead frame via the metal redistribution structure.

[0018] Preferably, the potential regions of the first power electrode and the second power electrode of the first power transistor are located on two opposite sides of the first chip, and the potential region of the second power electrode of the first power transistor is located on a side close to the second chip.

[0019] Preferably, the connecting device comprises a metal connecting structure with low interconnection resistance to connect the first power electrode of the second power transistor and the second power electrode of the first power transistor inside the packaging structure to accommodate large current and reduce interconnection resistance.

[0020] Preferably, the metal connection structure with low interconnection resistance includes a first portion connected to the second power electrode of the first power transistor and a second portion connected to the first power electrode of the second power transistor, and the first portion and the second portion are in contact with each other.

[0021] Preferably, the first portion is configured as a patterned rewiring metal structure to lead out the second power electrode of the first power transistor.

[0022] Preferably, the second portion is configured as a metal clip structure.

[0023] Preferably, the patterned rewiring metal structure includes an electrical lead and a finger structure; the finger structure is connected to the electrode lead-out structure, and the electrical lead is connected to the finger structure to lead out the corresponding potential.

[0024] Preferably, it is characterized in that the patterned rewiring metal structure includes a first metal layer, a welding structure and a second metal layer; the first surface of the first metal layer is connected to an electrode lead of the same potential, the welding structure is connected to the second surface of the first metal layer, and the electrode potential is re-arranged in a corresponding area of ​​the first chip; the first surface of the second metal layer is connected to the welding structure, and is connected to the outside through the second surface.

[0025] Preferably, the first wafer and the second wafer are stacked.

[0026] Preferably, the second chip is mounted upright, and the first chip is flipped over and partially stacked on top of the second chip.

[0027] Preferably, the second power electrode region of the first power transistor and the first power electrode region of the second power transistor overlap along a vertical direction of the packaging structure.

[0028] Preferably, the connecting device includes a metal connecting structure, a first surface of which is electrically connected to the second power electrode of the first power transistor through a weldable structure, a second surface of which is electrically connected to the first power electrode of the second power transistor through a weldable structure, and is connected to the corresponding pin of the lead frame through the metal connecting structure.

[0029] Preferably, the driving electrode in the first control and driving circuit is connected to the control electrode of the second power transistor through a metal connection structure, and the control electrode and the first power electrode are located on the same surface.

[0030] Preferably, the metal connection structure is configured as a metal bump or a metal redistribution structure.

[0031] Preferably, the first power electrode of the first power chip is connected to a corresponding pin of the lead frame through a metal bump or a metal redistribution structure.

[0032] Preferably, the first power electrode and the second power electrode of the second power transistor are located on the same surface of the second wafer.

[0033] Preferably, the connection between the first power transistor and the high level pin, the connection between the second power transistor and the low level pin, and the connection between the first power electrode and the second power electrode of the second power transistor are realized through a metal connection structure with low interconnection resistance or through a stacked direct connection method.

[0034] Preferably, the control electrode of the second power transistor and the first power electrode are located on different surfaces, and the drive electrode in the first control and drive circuit and the first power electrode are connected to the same pin of the lead frame via a metal connection structure.

[0035] Preferably, it further comprises a plastic package to cover the first chip, the second chip, the connecting device and the lead frame, and the pin portion is exposed outside the plastic package.

[0036] By integrating the first power transistor and the control and drive circuit into the same chip according to the packaging structure of the present invention, the high-frequency switching action of the first power transistor can be better realized, the operating frequency of the first power transistor can be increased, and the switching loss can be reduced. The second power transistor is integrated into an independent second chip, and the first chip and the second chip are separated in the packaging structure. The control and drive action of the second power transistor will not interfere with the first chip or have other negative effects, thereby improving reliability. The first chip and the second chip can be connected through a large-area connection structure, achieving a lower interconnection resistance and improving the large current handling capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0038] Figure 1A The schematic diagram of the buck power converter shown;

[0039] Figure 1B The figure shows a packaging structure applied to a power converter according to a first embodiment of the present invention;

[0040] Figure 1C Shown Figure 1B The first exemplary cross-sectional view along A-A' of the packaging structure applied to the power converter according to the present invention is shown;

[0041] Figure 1D Shown Figure 1B A second exemplary cross-sectional view of the packaging structure applied to a power converter according to the present invention along the line A-A' is shown;

[0042] Figure 2AFIG. 1 is a schematic diagram of a packaging structure applied to a power converter according to a second embodiment of the present invention;

[0043] Figure 2B Shown Figure 2A An exemplary cross-sectional view along the line B-B' of the packaging structure applied to a power converter according to the present invention is shown;

[0044] Figure 3A FIG. 1 is a schematic diagram of a power electrode lead-out structure of a first chip according to an embodiment of the present invention;

[0045] Figure 3B Shown Figure 3A A cross-sectional view of the power electrode lead-out structure of the first wafer along line C-C' is shown;

[0046] Figure 4A FIG. 1 is a schematic diagram of a power electrode lead-out structure of a first chip according to another embodiment of the present invention;

[0047] Figure 4B shown Figure 4A The cross-sectional view of the power electrode lead-out structure of the first wafer along the axis D-D' according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0048] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0049] It should be understood that when describing a structure, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the structure is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0050] If it is to describe the situation of being directly above another layer or another area, the expression "A is directly above B" or "A is above B and adjacent to it" will be used in this article. In this application, "A is directly in B" means that A is in B and A is directly adjacent to B.

[0051] Many specific details of the present invention, such as structure, material, size, processing technology and technology, are described below to provide a clearer understanding of the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0052] The present invention provides a packaging structure suitable for a power converter, comprising: a first chip, comprising at least a first power transistor and a first control and drive circuit; a second chip, comprising at least a second power transistor; a connecting device, used to sequentially couple the first power transistor and the second power transistor in series between a high-level pin and a low-level pin of a lead frame of the packaging structure through the connecting device inside the packaging structure; a common connection point of the first power transistor and the second power transistor is coupled to an output pin of the lead frame through a metal connection structure with low interconnection resistance.

[0053] Through this packaging structure, on the one hand, the first power transistor and the control and drive circuit are integrated into the same chip, and the connection between the control electrode and the drive signal can be directly carried out through the connection structure inside the chip, such as the metal layer. Therefore, there is no need for an implementation method similar to the external chip of the prior art center, such as a metal wire bonding method, or even worse, an implementation method of pin connection outside the package. Such an implementation method can better realize the high-frequency switching action of the first power transistor, increase the operating frequency of the first power transistor, and reduce the switching loss. On the second hand, the second power transistor is integrated into an independent second chip, and the first chip and the second chip are separated in the packaging structure. The control and drive action of the second power transistor will not interfere with or have other negative effects on the first chip, thereby improving reliability. At the same time, when the second chip is only used as the second power transistor, the area of ​​the chip can be made larger, thereby reducing the on-resistance and further reducing the conduction loss. On the third hand, the second power transistor is configured as a power device with a vertical current flow direction. The second power transistor is configured so that the current flow direction between the first power electrode and the second power electrode is in a vertical direction. For example, the second chip can be a VDMOS transistor or a source down LDMOS transistor. The type of the first power transistor in the first chip is different, for example, the first power transistor can be an LDMOS transistor. The selection of different types of power transistors can conveniently complete the connection between the first power transistor and the second power transistor inside the packaging structure, and connect them in series between a high potential (for example, an input voltage source) and a low potential (for example, a ground potential) through the pins of the packaging structure, thereby enhancing the anti-interference ability.

[0054] On the other hand, the first power electrode and the second power electrode of the second power transistor may also be located on the same surface of the second wafer.

[0055] The connection between the first power transistor and the high level pin, the connection between the second power transistor and the low level pin, and the connection between the first power electrode and the second power electrode of the second power transistor are realized through a metal connection structure with low interconnection resistance or through a stacked direct connection method.

[0056] The following description of this embodiment is based on the power converter being a buck-type power stage topology structure, and the main power transistor (first power transistor) and the rectifier power transistor (second power transistor) being MOSFET transistors. Correspondingly, the first power electrode is the drain of the MOSFET transistor, the second power electrode is the source of the MOSFET transistor, and the control electrode is the gate of the MOSFET transistor.

[0057] refer to Figure 1A The schematic diagram of the buck power converter shown in FIG. In the buck topology, the drain of the first power transistor Q1 receives the input voltage Vin, the source of the first power transistor Q1 is connected to the drain of the second power transistor Q2 and then connected to one end of the inductor L, and the source of the second power transistor Q2 is connected to the ground potential. The control and drive circuit 5 generates a main driving signal GH to the gate of the first power transistor Q1 based on the received information of the output voltage Vout and the reference voltage information Vref, thereby controlling the switching action of the first power transistor Q1, and the rectifier tube driving signal GL to the gate of the second power transistor Q2, thereby controlling the switching action of the second power transistor Q2. Through this cycle-by-cycle high-frequency control, the output voltage Vout is maintained consistent with the reference voltage Vref.

[0058] refer to Figure 1B , shown is a packaging structure applied to a power converter according to a first embodiment of the present invention.

[0059] The packaging structure according to this embodiment includes:

[0060] The first chip 1 integrates the main power transistor and the control and drive circuit into a single chip; its first power electrode 11 (drain), the second power electrode 12 (source) and the control and drive electrode (13) are all located on the same surface (upper surface) of the first chip.

[0061] The second chip 2 integrates a single rectifier power transistor; its first power electrode 21 (drain) and the second power electrode 22 (source) are located on different surfaces of the second chip, so that the current flowing through the first power electrode 21 (drain) and the second power electrode 22 (source) flows in a vertical direction; here, the first power electrode 21 (drain) is located on the upper surface of the second chip, and the second power electrode 22 (source) is located on the lower surface of the second chip (not shown in the figure); the control and drive electrode (13) can be located on the upper surface or the lower surface of the second chip. In this embodiment, the control and drive electrode (13) and the first power electrode 21 (drain) are both located on the upper surface of the second chip.

[0062] The lead frame includes a base 31 located in the inner area and pins 31 located in the outer edge area. The base 31 is used to provide mechanical support and necessary electrical connection for the first chip 1 and the second chip 2. Here, the first chip 1 and the second chip 2 are arranged in parallel and are both located on the upper surface of the base 31.

[0063] The connection device is used to connect different electrodes that need to be electrically connected inside the packaging structure. Including but not limited to the first connection structure 41 and the second connection structure 42. In the buck topology structure, the drain of the first power transistor receives the input voltage, the source of the first power transistor and the drain of the second power transistor are connected and then connected to one end of the inductor, and the source of the second power transistor is connected to the ground potential.

[0064] In order to achieve the above connection relationship, the drain of the first power transistor is connected to the corresponding pin 32 through the first connection structure 41, and the pin 32 is used to receive the input voltage source, thereby realizing the connection path between the drain of the first power transistor and the input voltage source. The first connection structure 41 is configured as a sheet connection structure, which has a large area and a low on-resistance to accommodate a large current. The first connection structure 41 can be a structure such as a copper clip, which is connected through a welding layer located in the copper clip and the drain area of ​​the first power transistor, and is connected to the pin of the corresponding lead frame through the copper clip.

[0065] The source of the first power transistor and the drain of the second power transistor are connected via a second connection structure 42. The source (not shown) located on the lower surface of the second wafer 2 is connected to the corresponding pin 32 via another conductive connection structure.

[0066] like Figure 1B As shown, the control and drive electrodes 13 of the first chip 1 and the electrodes (source and drain) of the first power transistor are located on the same surface (upper surface). The control and drive electrodes 13 and the electrodes of the first power transistor are arranged so that the electrodes of the first power transistor and the control and drive electrodes 13 are located on opposite sides of the upper surface of the first chip 1. When it is necessary to increase the performance of the first power transistor, such as withstand voltage or current, it can be derived in a direction away from the control and drive electrodes, which is convenient for expansion without being affected by the position of the control and drive electrodes 13, and the position of the original control and drive electrodes 13 can be unchanged.

[0067] In this embodiment, the control electrode 23 (gate) of the second chip 2 and the control and drive electrode 13 of the first chip 1 are both located on a side away from the substrate 31. Therefore, the control and drive electrode corresponding to the drive signal GL generated by the control and drive circuit in the first chip 1 can be connected to the control electrode 23 of the second chip 2 inside the packaging structure through a metal connection structure, such as a bonding wire.

[0068] refer to Figure 1C , shown as Figure 1B The illustrated diagram is a first exemplary cross-sectional view of a packaging structure applied to a power converter according to the present invention along the line A to A'.

[0069] In this example, the source of the first power transistor and the drain of the second power transistor are connected via a second connection structure 42. The second connection structure 42 is configured as a copper clip structure 42. The drain electrode on the upper surface of the second wafer 2 is connected to the copper clip structure 42 via a welding layer 25. The source electrode on the upper surface of the first wafer 1 is also connected to the copper clip structure 42 via a welding layer 15. Therefore, the source of the first power transistor and the drain of the second power transistor are connected together via the copper clip structure 42, and are led out to the corresponding pins 32 via the copper clip structure 42.

[0070] The source electrode located on the lower surface of the second chip 2 can be led out through the conductive layer 24. In one implementation, the conductive layer 24 can be directly connected to the patterned substrate 31, and then led out to the corresponding pin 32. It can be understood that the conductive layer can be configured to include a welding layer and a metal layer, or only include different forms of conductive structures such as a bondable conductive layer. In another implementation, the conductive layer 24 can be configured as a redistribution layer structure to lead the source electrode to the corresponding pin 32. An adhesive layer can be provided between the redistribution layer structure and the substrate 31 to mount and fix the second chip 2 on the substrate 31. The lower surface of the first chip 1 can be mounted and fixed on the substrate 31 by providing an insulating adhesive layer 14.

[0071] The large-area sheet-shaped copper clip structure can withstand large currents and has a small on-resistance, reducing losses.

[0072] refer to Figure 1D , shown as Figure 1B The second exemplary cross-sectional view along the line A to A' of the packaging structure applied to the power converter according to the present invention is shown.

[0073] and Figure 1C In contrast to the first example shown, the second connection structure 42 is configured as a redistribution metal structure 42 .

[0074] The drain electrode on the upper surface of the second wafer 2 is connected to the redistribution metal structure 42 through the metal bump layer 25 .

[0075] The source electrode on the upper surface of the first wafer 1 is also connected to the rewiring metal structure 42 through the metal bump layer 15. Therefore, the source of the first power transistor and the drain of the second power transistor are connected together through the rewiring metal structure 42, and are led out to the corresponding pins 32 through the rewiring metal structure 42.

[0076] Similarly, a large-area sheet-like rewiring metal structure can withstand larger currents and has smaller on-resistance, reducing losses.

[0077] It should be understood that Figure 1C and Figure 1D The packaging structure shown only shows a schematic diagram of the electrical connection relationship between the source electrode and the pin, and the upper and lower surfaces of the welding layer 25 and the upper and lower surfaces of the conductive layer 24 can be arranged with other required layers.

[0078] The packaging structure according to the first embodiment of the present invention further includes a plastic package body for plastic-packaging the lead frame, the first chip, the second chip, and the connecting device, and exposing the pins of the lead frame outside the plastic package body to achieve external connection through the pins.

[0079] refer to Figure 2A , shown is a packaging structure applied to a power converter according to a second embodiment of the present invention.

[0080] and Figure 1A The difference between the illustrated embodiment and the embodiment is that, in this embodiment, the first chip 1 and the second chip 2 are stacked and arranged, which obviously further reduces the packaging area.

[0081] Specifically, the second chip 2 is mounted upright on the substrate 31, and the first chip 1 is flipped on the second chip 2. Moreover, according to the electrode distribution area of ​​the first chip 1, the first chip 1 and the second chip 2 partially overlap along the vertical direction.

[0082] The first power electrode 21 (drain) region of the second power transistor and the second power electrode 12 (source) region of the first power transistor overlap along the vertical direction of the package structure.

[0083] The second power electrode 12 (source) region of the first power transistor is inverted above the first power electrode 21 (drain) region of the second power transistor, so that the second power electrode 12 (source) of the first power transistor and the first power electrode 21 (drain) of the second power transistor are directly connected.

[0084] One implementation method is to set a first connection structure 41 between the second power electrode 12 (source) of the first power transistor and the first power electrode 21 (drain) of the second power transistor, connect the two, and then connect to the corresponding pin 32 of the lead frame.

[0085] The connection between the control electrode 23 of the second chip 2 and the corresponding control and drive electrode 13 of the first chip 1 can be achieved by connecting the two through a metal connection structure inside the packaging structure. For example, the positions of the soldering pads corresponding to the control electrode 23 of the second chip 2 and the soldering pads corresponding to the control and drive electrode 13 of the corresponding first chip 1 are arranged so as to overlap in the vertical direction. In this way, the two are electrically connected through metal bumps, the process is simple to implement, and the reliability of the connection is relatively high. If the soldering pads corresponding to the control electrode 23 of the second chip 2 and the soldering pads corresponding to the control and drive electrode 13 of the corresponding first chip 1 cannot meet the above-mentioned vertical position relationship, the connection between the two can also be achieved through a rewiring layer process.

[0086] The remaining control and driving electrodes 13 of the first wafer 1 are arranged on the patterned pins 32 through a flip-chip packaging process.

[0087] The connection between the first power electrode 11 of the first chip 1 and the corresponding pin 32 can be achieved through a metal bump connected between the first power electrode 11 of the first chip 1 and the patterned pin 32; or can be achieved through a redistribution layer process.

[0088] Figure 2A The package structure shown is compared to Figure 1A The packaging structure shown, on the one hand, can further reduce the packaging area; on the other hand, the connection between the chip and the pins, as well as the connection between the chips, no longer needs to use metal wire bonding, which has higher reliability.

[0089] refer to Figure 2B , shown as Figure 2A The illustrated example is a cross-sectional view of a packaging structure applied to a power converter according to the present invention taken along line B—B′.

[0090] In this example, the source of the first power transistor and the drain of the second power transistor are connected via a second connection structure 42. The second connection structure 42 is configured as a copper clip structure 42. The drain electrode on the upper surface of the second wafer 2 is connected to the copper clip structure 42 via a welding layer 25. The source electrode on the upper surface of the first wafer 1 is also connected to the copper clip structure 42 via a welding layer 15. Therefore, the source of the first power transistor and the drain of the second power transistor are connected together via the copper clip structure 42, and are led out to the corresponding pins 32 via the copper clip structure 42.

[0091] The connection between the first power electrode 11 of the first chip 1 and the pin 32 is realized through the first connection structure 41. The first connection structure 41 can be set as a metal bump, one end of which is connected to the pin 32, and the other end is connected to the pad or metal layer corresponding to the first power electrode 11, so as to lead the first power electrode 11 outward through the pin 32.

[0092] The source electrode located on the lower surface of the second chip 2 can be led out through the conductive layer 24. In one implementation, the conductive layer 24 can be directly connected to the patterned substrate 31, and then led out to the corresponding pin 32. It can be understood that the conductive layer can be configured to include a welding layer and a metal layer, or only include different forms of conductive structures such as a bondable conductive layer. In another implementation, the conductive layer 24 can be configured as a redistribution layer structure to lead the source electrode to the corresponding pin 32. An adhesive layer can be provided between the redistribution layer structure and the substrate 31 to mount and fix the second chip 2 on the substrate 31. The lower surface of the first chip 1 can be mounted and fixed on the substrate 31 by providing an insulating adhesive layer 14.

[0093] It can be inferred that the second connection structure 42 can also be configured as a redistribution metal structure 42 .

[0094] The drain electrode on the upper surface of the second wafer 2 is connected to the redistribution metal structure 42 through the metal bump layer 25 .

[0095] The source electrode on the upper surface of the first wafer 1 is also connected to the rewiring metal structure 42 through the metal bump layer 15. Therefore, the source of the first power transistor and the drain of the second power transistor are connected together through the rewiring metal structure 42, and are led out to the corresponding pins 32 through the rewiring metal structure 42.

[0096] Large-area sheet-shaped copper clip structures or rewiring metal structures can withstand larger currents and have smaller on-resistance, thereby reducing losses.

[0097] It should be understood that Figure 2B The packaging structure shown only shows a schematic diagram of the electrical connection relationship between the source electrode and the pin, and the upper and lower surfaces of the welding layer 15 and the welding layer 25, and the upper and lower surfaces of the conductive layer 24 can be arranged with other required layers.

[0098] The packaging structure according to the second embodiment of the present invention further includes a plastic package body for plastic-packaging the lead frame, the first chip, the second chip, and the connecting device, and exposing the pins of the lead frame outside the plastic package body to achieve external connection through the pins.

[0099] In the above described embodiment, the gate and drain of the second chip are located on the same surface. It is understood that the gate of the second chip can also be located on a different surface from the drain, and on the same surface as the source. In this case, the gate can be led out to the corresponding pin, and the corresponding control and drive electrodes can be led out to the pin, so that the electrical connection between the two can be achieved outside the package.

[0100] The connection between the source electrode of the second chip and the corresponding pin can be made by directly mounting the source electrode on the back side on the large-area patterned pin as a pin connection structure, which will be beneficial to the heat dissipation of the chip. During the plastic packaging process, the back side of the pin connection structure can also be exposed to further improve the heat dissipation capacity.

[0101] In addition, in the above embodiment, the control and drive circuit of the second power stage transistor is integrated in the first chip. It can be understood that the control and drive circuit of the second power stage transistor can be independently a separate chip. The corresponding electrodes of the two are electrically connected inside the packaging structure or through the pins of the packaging structure.

[0102] like Figure 1B and 2A In the above-described embodiment shown, the areas of the first power electrode and the second power electrode of the first chip have been divided and respectively occupy different large area regions above the upper surface of the first chip to facilitate the subsequent interconnection between different electrodes and the connection between the electrodes and the pins of the lead frame.

[0103] The specific implementation method of the regional arrangement of the first power electrode and the second power electrode of the first wafer 1 will be described below according to specific embodiments.

[0104] refer to Figure 3A , which is a schematic diagram of the power electrode lead-out structure of the first chip according to an embodiment of the present invention. Still taking the MOSFET transistor as an example, the first power electrode is the drain, and the second power electrode is the source.

[0105] In this embodiment, the first wafer includes a plurality of unit cells; each unit cell is continuously arranged in a continuous drain-gate-source form and connected in parallel with each other. For convenience of explanation, only the arrangement of the drain and the source is shown in the figure. The drain and the source are arranged in parallel and crossed.

[0106] The patterned first connection structure 33 is configured to connect all drains together. Specifically, the first connection structure 33 includes a plurality of first finger structures 332 and a first electrical lead 331. The first power electrode bonding region 31 is a region where the first finger structures 332 and the drain electrode of the first wafer are bonded, thereby making the first connection structure 33 have the same potential as the drain.

[0107] Similarly, the patterned second connection structure 34 is configured to connect all the sources together. Specifically, the second connection structure 33 includes a plurality of second finger structures 342 and a second electrical lead 341. The second power electrode bonding region 32 is a region where the second finger structure 342 and the source electrode of the first wafer are bonded, thereby making the second connection structure 34 have the same potential as the source.

[0108] The drain and the source are arranged in different regions respectively through the patterned first connection structure 33 and the second connection structure 34 .

[0109] In one implementation, the patterned first connection structure 33 and the second connection structure 34 are configured as a redistribution metal structure.

[0110] refer to Figure 3B , shown as Figure 3A The cross-sectional view of the power electrode lead-out structure of the first wafer is taken along line C—C′.

[0111] The source pad of the first chip 1 is connected to the second finger structure 342 through the metal bump 5, and the bonding area between the two is the second power electrode bonding area 32. It can also be a connection structure other than the metal bump 5, such as a welding layer or a solder ball.

[0112] pass Figure 3A and Figure 3B In the power electrode lead-out structure shown, the source potential and the drain potential are arranged in opposite side areas. The source potential led out by the second electrical lead 341 is located in the area close to the second wafer. The connection between the source of the first wafer and the drain of the second wafer can be achieved by connecting the second electrical lead 341 of the second connection structure 34 to the drain of the second wafer through the large-area sheet-like connection structure described above, such as a copper clip. The connection between the drain of the first wafer and the pin can also be achieved by connecting the first electrical lead 331 to the pin through a large-area sheet-like connection structure, such as a copper clip.

[0113] The power electrode lead-out structure of the first wafer can also be realized by a layered first connection structure and a second connection structure with different heights. For example, the first connection structure connected to the drain pad has a relatively high height. The patterned second connection structure connected to the source pad has a relatively low height, and the source and drain can also be arranged on opposite sides.

[0114] refer to Figure 4A , which is a schematic diagram of a power electrode lead-out structure of a first chip according to another embodiment of the present invention, and Figure 4B shown Figure 4A The cross-sectional view of the power electrode lead-out structure of the first wafer along the axis D-D' according to an embodiment of the present invention is shown.

[0115] Still taking the MOSFET transistor as an example, the first power electrode is the drain, and the second power electrode is the source.

[0116] The patterned rewiring metal structure includes a first metal layer, a welding structure and a second metal layer; the first surface of the first metal layer is connected to an electrode lead of the same potential, the welding structure is connected to the second surface of the first metal layer, and the electrode potential is re-arranged in a corresponding area of ​​the first chip; the first surface of the second metal layer is connected to the welding structure, and is connected to the outside through the second surface.

[0117] Specifically, the patterned redistribution metal structure includes a first metal layer 401 , a welding structure 402 and a second metal layer 403 .

[0118] According to the matrix arrangement of the solder balls on the first chip 1, the patterned redistribution metal structure (drain redistribution unit) is connected to the drain solder ball 401 through the first surface of the first metal layer 402 (drain), and is connected to the second metal layer 404 located in the upper area through the welding structure 403 (such as the solder ball structure) on the second surface, so as to lead the drain electrode polarity to the upper half area of ​​the first chip. Similarly, the redistribution metal structure (source redistribution unit) is connected to the source solder ball 405 through the first surface of the first metal layer 406 (source), and is connected to the second metal layer 408 located in the lower area through the welding structure 407 (such as the solder ball structure) on the second surface, so as to lead the source electrode polarity to the lower half area of ​​the first chip, thereby dividing the drain electrode polarity and the source electrode polarity into two independent and non-overlapping areas.

[0119] The area and thickness of the second metal layer can be set to larger values, which can reduce the resistance of the current conduction path and power loss while achieving electrical connection.

[0120] In addition to the connection structures outside the wafer illustrated above, such as the first connection structure and the second connection structure to achieve the rearrangement of the drain potential and the source potential, the drain potential and the source potential can also be rearranged at the wafer level, for example, through the metal layer of the wafer.

[0121] Therefore, the connection structure between different electrode potentials and the connection structure between electrode potentials and pins according to the present invention refers to a connecting component that can connect different potentials together, and may include one or more different parts, which may be integrated or separate; may be made of the same or different materials; and may include parts outside the wafer and parts inside the wafer.

[0122] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0123] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A packaging structure for a power converter, characterized in that: include: A first chip including at least a first power transistor and a first control and drive circuit; The control electrode, the first power electrode and the second power electrode of the first power transistor are located on the same surface of the first wafer; A second chip including at least a second power transistor; The first power electrode and the second power electrode of the second power transistor are located on different surfaces of the second wafer; The second power transistor is configured as a power device having a current flow direction perpendicular to the second wafer; A connecting device, located inside the packaging structure, for sequentially coupling the first power transistor and the second power transistor in series between a high level pin and a low level pin of a lead frame of the packaging structure; The connecting device includes a metal connecting structure with low interconnection resistance to connect the first power electrode of the second power transistor and the second power electrode of the first power transistor inside the package structure to accommodate large current and reduce interconnection resistance; and is coupled to the pins of the outer edge area of ​​the lead frame; The second power electrode of the second wafer is connected to the base of the inner region of the lead frame through the conductive layer.

2. The packaging structure according to claim 1, characterized in that: The connection between the first power transistor and the high level pin, and the connection between the second power transistor and the low level pin are realized through a metal connection structure with low interconnection resistance or through a stacked direct connection method.

3. The packaging structure according to claim 2, characterized in that: The low interconnect resistance metal connection structure is configured as a sheet-like metal clip structure or a redistribution metal structure.

4. The packaging structure according to claim 1, characterized in that: The first wafer and the second wafer are arranged in parallel.

5. The packaging structure according to claim 4, characterized in that: The low interconnection resistance metal connection structure includes a metal clip structure, which is electrically coupled to the second power electrode of the first power transistor and the first power electrode of the second power transistor through a welding layer and connected to corresponding pins of a lead frame.

6. The packaging structure according to claim 4, characterized in that: The metal connection structure with low interconnection resistance includes a metal rewiring structure. The second electrode of the first power transistor and the first electrode of the second power transistor are connected to the metal rewiring structure through a welding process and connected to corresponding pins of the lead frame via the metal rewiring structure.

7. The packaging structure according to claim 1, characterized in that: The potential regions of the first power electrode and the second power electrode of the first power transistor are located on two opposite sides of the first wafer, and the potential region of the second power electrode of the first power transistor is located on a side close to the second wafer.

8. The packaging structure according to claim 1, characterized in that: The low interconnection resistance metal connection structure includes a first portion connected to the second power electrode of the first power transistor and a second portion connected to the first power electrode of the second power transistor, wherein the first portion and the second portion are in contact with each other.

9. The packaging structure according to claim 8, characterized in that: The first portion is configured as a patterned redistribution metal structure to lead out a second power electrode of the first power transistor.

10. The packaging structure according to claim 9, characterized in that: The second portion is configured as a metal clip structure.

11. The packaging structure according to claim 9, characterized in that: The patterned redistribution metal structure includes an electrical lead and a finger structure; the finger structure is connected to the electrode of the first wafer, and the electrical lead is connected to the finger structure to lead out the corresponding potential.

12. The packaging structure according to claim 9, characterized in that: The patterned rewiring metal structure includes a first metal layer, a first welding structure, a second welding structure and a second metal layer; the first surface of the first metal layer is connected to an electrode of the same potential through the first welding structure, and the second welding structure is connected to the second surface of the first metal layer, and the first welding structure and the second welding structure re-arrange the potential of the electrode to a corresponding area of ​​the first chip; the first surface of the second metal layer is connected to the second welding structure, and the second metal layer is connected to the outside through the second surface.

13. The packaging structure according to claim 1, characterized in that: The first wafer and the second wafer are stacked.

14. The packaging structure according to claim 13, characterized in that: The second chip is mounted face up, the first chip is mounted face down, and a portion of the first chip is stacked on the second chip.

15. The packaging structure according to claim 14, characterized in that: A position of the second power electrode of the first power transistor overlaps a position of the first power electrode of the second power transistor along a vertical direction of the packaging structure.

16. The packaging structure according to claim 15, characterized in that: The first surface of the metal connection structure with low interconnection resistance is electrically connected to the second power electrode of the first power transistor through a weldable structure, and the second surface is electrically connected to the first power electrode of the second power transistor through a weldable structure. The second power electrode of the first power transistor and the first power electrode of the second power transistor are connected to corresponding pins of the lead frame through the metal connection structure with low interconnection resistance.

17. The packaging structure according to claim 15, characterized in that: The driving electrode in the first control and driving circuit is connected to the control electrode of the second power transistor through a metal bump or a metal rewiring structure, and the control electrode of the second power transistor is located on the same surface as the first power electrode of the second power transistor.

18. The packaging structure according to claim 15, characterized in that: The first power electrodes of the first wafer are connected to corresponding pins of the lead frame through metal bumps or metal redistribution structures.

19. The packaging structure according to claim 1, characterized in that: It also includes a plastic package to cover the first chip, the second chip, the connecting device and the lead frame, and the pin part is exposed outside the plastic package.

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