Methods and systems for forming backside metal

Abstract

The invention is entitled "Methods and systems for forming backside metal." Embodiments of a method of forming a metal layer on a semiconductor wafer are disclosed that can include placing a semiconductor wafer into an evaporator dome and adding a material into a crucible at a predetermined distance from the semiconductor wafer. The semiconductor wafer can have an average thickness of less than 39 microns. The method can also include heating the material in the crucible into a vapor and depositing the material on a second side of the semiconductor wafer.

Description

Technical Field

[0001] This document covers, in general, systems and methods for applying metallization to substrates. More specific implementations relate to semiconductor substrates. Background Technology

[0002] Semiconductor substrates are used to form various semiconductor devices. Semiconductor devices are typically distributed on a flat surface of a semiconductor substrate across multiple dies. Metal layers can be formed on the side of the semiconductor substrate opposite to the multiple dies. Summary of the Invention

[0003] A specific implementation of a method for forming a metal layer on a semiconductor wafer may include: placing the semiconductor wafer into an evaporator dome, and adding material to a crucible at a predetermined distance from the semiconductor wafer. The semiconductor wafer may have an average thickness of less than 39 micrometers. The method may further include heating the material in the crucible into vapor and depositing the material onto a second side of the semiconductor wafer.

[0004] Specific implementations of the method for forming a metal layer on a semiconductor wafer may include one, all, or any of the following:

[0005] Heating may include either resistance heating or electron beam heating.

[0006] The semiconductor may include multiple dies located on a first side of the semiconductor wafer.

[0007] The semiconductor wafer may include an edge ring surrounding the periphery of the semiconductor wafer.

[0008] The first side of the semiconductor wafer can be coupled to the back polishing belt.

[0009] The second side of the semiconductor wafer may not be coupled to the back polishing tape.

[0010] The material in the crucible can be a metal, including titanium, gold, copper, tin, tungsten, aluminum, silver, nickel, chromium, or any combination thereof.

[0011] The method may also include etching the wafer, and the etching may include wet etching.

[0012] Semiconductor wafers may not be coupled to a carrier.

[0013] Specific implementations of a method for forming a metal layer on a semiconductor wafer may include: placing the semiconductor wafer into an evaporator dome and adding material to a crucible at a predetermined distance from the semiconductor wafer. The semiconductor wafer may include a first side and a second side. The method may further include coupling the material to the second side of the semiconductor die by heating. Heating may include resistance heating or electron beam heating. The semiconductor wafer may have an average thickness of less than 10 micrometers.

[0014] Specific implementations of the method for forming a metal layer on a semiconductor wafer may include one, all, or any of the following:

[0015] The semiconductor wafer may include an edge ring surrounding the periphery of the semiconductor wafer.

[0016] The first side of the semiconductor wafer can be coupled to the back polishing belt.

[0017] The material in the crucible is a metal, including titanium, gold, copper, tin, tungsten, aluminum, silver, nickel, chromium, or any combination thereof.

[0018] The method may also include etching the wafer, and the etching may include wet chemical etching.

[0019] The semiconductor wafer can be decoupled from the carrier.

[0020] Specific implementations of a method for forming a metal layer on a semiconductor wafer may include: placing the semiconductor wafer into an evaporator dome, and coupling a material to a second side of the semiconductor wafer by heating. The semiconductor wafer may have an average thickness between 5 micrometers and 39 micrometers. Heating may include resistance heating or electron beam heating. The wafer may not be coupled to a carrier.

[0021] Specific implementations of the method for forming a metal layer on a semiconductor wafer may include one, all, or any of the following:

[0022] The average thickness of the semiconductor in this wafer can be 25 micrometers.

[0023] The semiconductor wafer may include an edge ring surrounding the periphery of the semiconductor wafer.

[0024] The first side of the semiconductor wafer can be coupled to the back polishing belt.

[0025] The method may also include etching the wafer, wherein the etching includes wet chemical etching.

[0026] The above and other aspects, features and advantages will become apparent to those skilled in the art from the description and drawings and from the claims. Attached Figure Description

[0027] Specific embodiments will be described below in conjunction with the accompanying drawings, in which similar reference numerals denote similar elements, and:

[0028] Figure 1 This is an internal view of the specific implementation of the evaporator dome;

[0029] Figure 2 This is an internal view of another specific embodiment of the evaporator dome;

[0030] Figure 3 This is a bottom perspective view of the specific implementation of the chip holding assembly; and

[0031] Figure 4 This is an internal view of the specific implementation of the evaporator machine. Detailed Implementation

[0032] This disclosure, its aspects, and specific embodiments are not limited to the specific components, assembly steps, or methodological elements disclosed herein. Numerous additional components, assembly steps, and / or methodological elements known in the art for forming back metals as intended will be readily apparent when used with specific embodiments of this disclosure. Thus, for example, although specific embodiments are disclosed, such embodiments and implementation components may include any shape, size, style, type, model, version, measure, concentration, material, quantity, methodological element, step, etc., known in the art for such back metal formation methods and systems, and implementation components and methods, conforming to the intended operation and methods.

[0033] For semiconductor dies with an average thickness of less than 40 micrometers, specific processing challenges exist. Die handling, die strength, and performing processing operations with the die all present specific challenges because die and wafer breakage can significantly reduce yield and / or affect device reliability. Die strength is negatively impacted by conventional dicing options, such as sawing, which causes die breakage and cracks along the die street. These fragments and cracks formed during the sawing process can ultimately propagate during operation and reliability testing, leading to die failure. Damage can also occur as part of the process of forming a metal layer on the second side of the wafer. The wafer can be damaged when it is removed from the carrier.

[0034] The term "substrate" refers to a semiconductor substrate because semiconductor substrates are a common type of substrate, but "substrate" is not a specific term used to refer to all types of semiconductor substrates. Similarly, the term "substrate" can refer to a wafer because wafers are a common type of substrate, but "wafer" is not a specific term used to refer to all wafers. By way of non-limiting example, the various types of semiconductor substrates disclosed in this document that can be used in various embodiments can be circular, rounded, square, rectangular, or any other closed shape. In various embodiments, by way of non-limiting example, the substrate can include substrate materials such as single-crystal silicon, silicon dioxide, glass, gallium arsenide, sapphire, ruby, silicon-on-insulator, silicon carbide, any of the aforementioned substances in polycrystalline or amorphous form, and any other substrate materials that can be used to construct semiconductor devices. In a particular embodiment, the substrate can be a silicon-on-insulator substrate.

[0035] In various embodiments disclosed in this document, the semiconductor substrate includes a plurality of semiconductor dies that have been processed using semiconductor manufacturing processes to form one or more semiconductor devices (not shown) in or on the semiconductor substrate. The plurality of dies have been processed on a first side or active side of the semiconductor substrate. This may include forming a plurality of layers on the first side of the substrate. The plurality of layers may be patterned, and in various embodiments, may be patterned (or otherwise removed) not over die channels in the substrate. By way of non-limiting example, the plurality of layers may include one or more metal layers, one or more passivation layers, any other layers, and any combination thereof. In various embodiments, by way of non-limiting example, the plurality of dies may include power semiconductor devices, such as MOSFETs, IGBTs, or any other power semiconductor devices. In other embodiments, the plurality of dies may include non-power semiconductor devices.

[0036] After the manufacturing process is completed (or, in some specific implementations, during some portions of the manufacturing process), the semiconductor substrate is thinned to a desired substrate thickness on one side opposite to the side on which one or more semiconductor devices have been formed. This thinning process is performed using back-side grinding, polishing, etching, any combination thereof, or any other technique for substantially uniformly removing material from the semiconductor substrate on its largest flat surface.

[0037] In various embodiments, the substrate can be thinned to an average thickness of less than 50 micrometers (μm). As used herein, "average thickness" refers to the average thickness of the substrate over at least a majority of its surface. In other embodiments, the substrate can be thinned to an average thickness of less than 30 μm. In still other embodiments, the substrate can be thinned to an average thickness of less than 100 μm and greater than 100 μm, and in various other embodiments, the substrate may not be thinned. In a particular embodiment, the substrate can be thinned to an average thickness of 25 μm, and in other particular embodiments, the substrate can be thinned to an average thickness of 75 μm. The substrate can be thinned by back-side grinding, etching, or any other thinning technique.

[0038] In various embodiments, the thinning process can create an edge ring around the wafer (like the edge ring present in the TAIKO back-grinding process sold by Disco Hi-Tec America, Inc., Santa Clara, California). The edge ring serves to structurally support the wafer after thinning, eliminating the need for a wafer carrier during subsequent processing steps. In various embodiments, the thinning process can be performed after the semiconductor substrate has been mounted to the back-grinding tape, regardless of whether an edge ring is formed during back-grinding. In various embodiments, a variety of back-grinding tapes can be used, including those compatible with subsequent plasma etching operations. In other embodiments, the semiconductor substrate may not be coupled to the back-grinding tape.

[0039] In various embodiments, a metal layer is applied to a second side of the semiconductor substrate after a thinning process. In some embodiments, this metal layer may be referred to as a back metal layer or back metal. In various embodiments, the back metal layer may be copper or a copper alloy. In some embodiments, the metal may include tungsten, tin, gold, titanium, aluminum, silver, nickel, chromium, alloys thereof, or any combination thereof. In other embodiments, the back metal layer may include any other type of metal, alloys thereof, or combinations thereof. In various embodiments, the thickness of the back metal layer may be about 10 μm. In other embodiments, the thickness of the back metal layer may be greater than or less than 10 μm.

[0040] For thin wafers in the 5-39 micrometer range, sputtering metal deposition processes apply too much energy to the thinned substrate. As a result, sputtering increases the wafer temperature and can overheat the thin substrate in a very short time. In various processes, the wafer overheats within seconds. The heat energy comes from ion bombardment during the sputtering process. This energy can also come from infrared heating generated by the plasma that forms around the substrate. Slowing down the sputtering process to reduce the energy and heat experienced by the wafer could reduce the process too much for the currently required processing cycle time. In the sputtering chamber, a cooling chuck may not be a feasible tool for use with ultra-thin wafers. An electrostatic chuck may not be suitable for ultra-thin wafers because the capacitance generated by the thinned wafer is insufficient to allow it to couple with the chuck.

[0041] This document discloses various specific implementations of a method for forming a metal layer on a semiconductor wafer using an evaporation process. See also... Figure 1 A schematic diagram of an evaporator dome 2 is shown. The evaporator dome 2 includes a crucible 4. In various embodiments, the crucible may contain one compartment or may exhibit multiple compartments, each with its own crucible. Different materials are present in the different compartments for evaporation onto the second side or back surface of the wafer. The materials in the compartments / crucibles may be metals, including but not limited to tungsten, copper, titanium, gold, alloys, and any other metals used for back surface metallization or seed metallization on the non-active side of the wafer. In this particular embodiment, various wafers / substrates 6 are positioned within a predetermined distance above the crucible 4 in the wafer holder 12. Here, a heating element 8 is positioned below the crucible 4. In various embodiments, the heating element 14 may be an induction heating element and may be positioned around the crucible 16, such as... Figure 2 As shown. In the case of Figure 2 In various specific embodiments shown, the method may include using a radio frequency (RF) generator to operate a heating element 8 to heat a crucible 4, causing one or more materials in the crucible to evaporate and couple to a second side of the wafer 18.

[0042] In various other specific embodiments, the heating of the crucible may include resistance heating or electron beam heating. In resistance heating, the material in the crucible may be in a high vacuum environment and heated to its evaporation point by using a resistance heating element. The evaporated molecules then travel from the source to the substrate / wafer, where they nucleate together on the substrate / wafer to form a thin film coating. This technique can be used to deposit a variety of materials, such as aluminum, silver, nickel, chromium, magnesium, or any other materials mentioned herein.

[0043] In a specific implementation of electron beam heating, an electric current is first passed through a filament, which causes the filament to heat up and subsequently emit electrons. A high voltage is applied between the filament and the furnace bed to accelerate the released electrons toward a crucible containing the material to be deposited. A strong magnetic field focuses the electrons into a uniform electron beam; upon arrival, the energy of this electron beam is transferred to the deposition material, causing the material to evaporate (or sublimate) and ultimately deposit onto a substrate / wafer. Adding a partial pressure of a reactive gas (such as oxygen or nitrogen) to the chamber during evaporation can be used to reactively deposit non-metallic film materials.

[0044] In some embodiments of a method for forming a metal layer on the second side of a semiconductor wafer, various compartments of the crucible may be covered to prevent a particular material from coupling to the second side of the wafer during a deposition step. In other embodiments, two or more compartments may be simultaneously uncovered to form a metal coating comprising a material composition. The sequential covering and uncovering of various compartments can be used to form various material layers, with each compartment forming a material layer on top of the others.

[0045] refer to Figure 2 This illustrates another specific embodiment of a method for forming a metal layer on a semiconductor wafer. The method may include placing a semiconductor wafer / substrate 18 into an evaporator dome 20. In various embodiments, the thickness of the wafer 18 may be less than 39 micrometers. In some embodiments, the average thickness of the wafer 18 may be about 10 micrometers. In other embodiments, the average thickness of the wafer may be about 25 micrometers. Wafers with an average thickness between about 5 micrometers and 39 micrometers can be formed from standard carriers (such as glass plates, carrier wafers, wafer holders, etc.). Figure 3 and Figure 4 (Those shown) or other standard wafer carriers used for semiconductor wafer handling break during removal. Various embodiments of the method may include a wafer having an edge ring disposed around the periphery of the wafer. In such embodiments, tweezers may be used to handle the edge ring of the wafer. In some embodiments, vacuum devices such as wafer bars or non-contact Bernoulli handlers may be used to handle the wafer. In various embodiments, a first side of the semiconductor wafer may be coupled to a strip. By way of non-limiting example, the strip may be a back-grinding strip, a pick-up strip, or various other strips for fixing and stabilizing the semiconductor wafer. In other embodiments, the semiconductor wafer may not be coupled to a strip.

[0046] This method may include heating the material 22 in the crucible 16 into vapor 24 using any heating method disclosed in this document. Figure 2In the system shown, an induction heating system is employed. Material can be coupled to a second side 26 of a semiconductor wafer 18, thereby depositing material onto the second side of the wafer and forming a coating. In various embodiments, the evaporator dome can rotate during material evaporation to facilitate the deposition of a uniform material coating on the second side of the semiconductor wafer. The wafer can be coupled into an opening in the evaporator dome, which resembles an orange peel. For wafers with a diameter of 6 inches, 32 wafers can be processed in a single evaporator in various embodiments. In other embodiments, 12 wafers of the same size, with a diameter of 8 inches, can be processed in a single evaporator.

[0047] In various embodiments of a method for forming a metal layer on a second side of a semiconductor wafer, the layer may include a back metallization layer and / or a seed metal layer. The method may also include etching any of these layers prior to forming the metal layer. In some embodiments, the etching may include wet chemical etching. In various embodiments, the etching of the wafer may be part of an alignment and dicing method for subsequent processing steps. In other embodiments, the etching may be part of a patterning method used finally in a subsequent packaging step. In still other embodiments, the substrate may be chemically etched to remove backside damage following thinning to clean the surface used for applying the backside metal. In still other embodiments, the substrate may be chemically etched to roughen the second side of the semiconductor wafer to increase the adhesion of the backside metal.

[0048] After a metal layer is formed on the second side of a semiconductor wafer, additional processing steps can be performed after the wafer / substrate is removed from the evaporator system. These additional processing steps may include dicing multiple semiconductor dies from the wafer. Dicing may include plasma etching, laser dicing, or sawing. In some embodiments, dicing may be performed from the back side / second side of the wafer. Dicing may include aligning the wafer using alignment features on the front side of the wafer. These alignment features may be located in channels between the multiple dies. In various embodiments, the alignment features may be located on the edges of the dies. When the wafer is aligned, multiple alignment marks may be formed on the second side of the wafer by laser dicing, sawing, or scribing. Scribing may include using a stylus or scribing tool. These multiple alignment marks may resemble perforation marks on the second side of the wafer. These multiple alignment marks can be detected with a visible light camera or an infrared camera. The dicing method may also include forming a groove line in the back side of the wafer using sawing, laser dicing, or scribing. The metal layer may have a remaining thickness of 1 micrometer in the groove line. The multiple dies can then be separated by sawing or laser dicing through the groove line.

[0049] Additional alignment methods may include applying a photoresist before applying the metal layer, and then patterning the photoresist. The photoresist prevents the metal layer from forming in areas covered by the photoresist. After the metal layer is formed, the photoresist can then be removed to reveal two or more alignment marks protected during the metal deposition process. Alignment features in die channels or within the die in areas not covered by the photoresist can be detected using a visible light or infrared camera via the two or more alignment marks.

[0050] In another specific embodiment of the method for aligning and dicing a semiconductor wafer, the method may include forming a metal layer on an edge support ring. The edge support ring may then be ground to remove the metal layer surrounding the periphery of the wafer and form an edge exclusion region. Using an infrared camera, three or more alignment features can be detected through the remaining non-metallized edge exclusion region. After aligning the wafer, multiple dies may be diced from the wafer using a laser, saw, or plasma etching.

[0051] Specific implementations of a method for forming a metal layer on a semiconductor wafer may include: wherein heating includes either resistance heating or electron beam heating.

[0052] The specific implementation of the method for forming a metal layer includes: wherein the semiconductor wafer includes a plurality of dies located on a first side of the semiconductor wafer.

[0053] A specific implementation of the method for forming a metal layer includes: wherein a first side of the semiconductor wafer is coupled to a back polishing tape.

[0054] The specific implementation of the method for forming a metal layer includes: wherein a first side of the semiconductor wafer is not coupled to a back polishing tape.

[0055] A specific implementation of the method for forming a metal layer includes: wherein the material in the crucible is a metal, including titanium, gold, copper, tin, tungsten, aluminum, silver, nickel, chromium, or any combination thereof.

[0056] The method for forming the metal layer also includes etching the wafer, wherein the etching includes wet chemical etching.

[0057] Where the methods for forming a metal layer and the specific implementations of the components, sub-components, methods and sub-methods mentioned above are described, it should be readily apparent that various modifications can be made without departing from the essence, and that these implementations, components, sub-components, methods and sub-methods can be applied to other methods for forming a back metal layer.

Claims

1. A method of forming a metal layer on a semiconductor wafer, the method comprising: placing a semiconductor wafer into an evaporator dome, the semiconductor wafer having an average thickness less than 10 microns; adding a material to a crucible at a predetermined distance from the semiconductor wafer; heating the material in the crucible into a vapor; depositing the material on a second side of the semiconductor wafer; aligning the wafer using alignment features on a first side of the wafer; and cutting the wafer from the second side of the wafer.

2. The method of claim 1, wherein the semiconductor wafer includes an edge support ring around a perimeter of the semiconductor wafer.

3. The method of claim 1, wherein the semiconductor wafer is not coupled to a carrier.

4. A method of forming a metal layer on a semiconductor wafer, the method comprising: placing a semiconductor wafer into an evaporator dome, the semiconductor wafer including a first side and a second side; adding a material to a crucible at a predetermined distance from the semiconductor wafer; and coupling the material to the second side of the semiconductor wafer by heating; wherein heating includes one of resistive heating or electron beam heating; and wherein the semiconductor wafer has an average thickness less than 10 microns, the method further comprising: aligning the wafer using alignment features on a front side of the wafer; and cutting the wafer from the second side of the wafer.

5. The method of claim 4, wherein the semiconductor wafer includes an edge ring around a perimeter of the semiconductor wafer.

6. The method of claim 4, wherein the semiconductor wafer is not coupled to a carrier.

7. A method of forming a metal layer on a semiconductor wafer, the method comprising: placing a semiconductor wafer into an evaporator dome, the semiconductor wafer having an average thickness greater than or equal to 5 microns and less than 10 microns; coupling a material to a second side of the semiconductor wafer by heating; wherein heating includes one of resistive heating or electron beam heating; and wherein the semiconductor wafer includes an edge ring around a perimeter of the semiconductor wafer, the method further comprising: aligning the wafer using alignment features on a front side of the wafer; and cutting the wafer from the second side of the wafer.

8. The method of claim 7, further comprising etching the semiconductor wafer, wherein the etching includes a wet chemical etch to roughen a second side of the semiconductor wafer.

9. The method of claim 7, wherein a first side of the semiconductor wafer is coupled to a backside grind tape. ​ ​ ​

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