Drive device, power supply system and method for testing drive device

Abstract

The present application relates to a driving device, a power supply system, and a method for testing the driving device. The driving device includes: a sensor for detecting the state of stress applied to a power transistor; a threshold voltage setting circuit for outputting a threshold voltage; an abnormality monitoring circuit for determining whether the state of stress is abnormal by comparing the voltage of the detected sensor with the threshold voltage; and a control circuit for fixing the power transistor to be turned on or off when the state of stress is determined to be abnormal by the abnormality monitoring circuit. When the operation mode is a test mode, the control circuit tests whether the abnormality monitoring circuit determines that the state of stress is abnormal by switching the level of the threshold voltage set by the threshold voltage setting circuit, so as to determine that the state of stress applied to the power transistor is abnormal in the abnormality monitoring circuit in normal operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The entire disclosure of Japanese Patent Application No. 2019-081679 filed on April 23, 2019 including the specification, drawings and abstract is incorporated herein by reference. Technical Field

[0003] The present invention relates to a drive device, a power supply system and a test method for the drive device, for example, a drive device, a power supply system and a test method for the drive device that are suitable for improving safety. Background Art

[0004] Since high voltage and high current are used when controlling inverters mounted on electric vehicles and controlling large electric motors, high safety is required for the on / off control of power transistors such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

[0005] For example, if a power transistor is accidentally turned on when it is supposed to be turned off, an overcurrent may flow through the power transistor. In addition, when a surge or back electromotive force occurs, an overvoltage may be applied to the power transistor. Furthermore, under high load conditions, the power transistor overheats to exceed the rated temperature. Such overcurrent, overvoltage, or overheating conditions may result in breakdown or unintentional degradation of the power transistor.

[0006] Therefore, a gate driver for driving a power transistor is generally provided with a circuit for detecting and protecting the power transistor from overvoltage, overcurrent, and overheating conditions of the power transistor.

[0007] The disclosed technologies are listed below.

[0008] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2017-229151

[0009] [Patent Document 2] U.S. Patent No. 5,534,814

[0010] For example, Patent Document 1 discloses a configuration of a gate driver having a function of protecting a power transistor.

[0011] [Non-patent document 1] L. Dulau, et al., "A new gate driver integrated circuit for IGBT devices with advanced protections", IEEE Transactions on Power Electronics, Vol. 21, Issue 1, p. 38-44, 2006.

[0012] Patent Document 2 and Non-Patent Document 1 disclose configurations of active mirror clamp circuits for preventing noise generated in an IGBT gate voltage. Summary of the invention

[0013] However, in the configuration of the prior art, there is no function to test whether a protection circuit such as an overvoltage protection circuit operates normally. Therefore, there is a problem that when the protection circuit does not operate normally due to an open circuit failure caused by, for example, cracking of the solder of the terminal, adhesion of dust, or a short circuit caused by a component failure, the power transistor cannot be protected from excessive stress such as overvoltage. That is, in the configuration of the prior art, there is a problem that safety cannot be improved. Therefore, in the configuration of the prior art, the power transistor may be damaged or unintentionally degraded. Other purposes and novel features will become apparent from the description and drawings of this specification.

[0014] According to one embodiment, a driving device includes: a sensor configured to detect and output a state of stress applied to a power transistor as a detection voltage; a threshold voltage setting circuit configured to output a threshold voltage; an abnormality monitoring circuit configured to determine whether the state of stress applied to the power transistor is abnormal by comparing the detection voltage and the threshold voltage; and a control circuit configured to fix the power transistor to be turned on or off according to the type of stress when the abnormality monitoring circuit determines that the state of stress is abnormal. When the operation mode is a test mode, the control circuit is further configured to test whether the abnormality monitoring circuit determines that the state of stress is abnormal by switching the level of the threshold voltage set by the threshold voltage setting circuit, so as to determine that the state of stress applied to the power transistor is abnormal in the abnormality monitoring circuit in normal operation.

[0015] According to another embodiment, a testing method of a driving device includes: switching the level of a threshold voltage set by a threshold voltage setting circuit so as to determine that a state of stress applied to a power transistor is abnormal in an abnormality monitoring circuit in normal operation, and testing whether the abnormality monitoring circuit determines that the state of stress applied to the power transistor is abnormal by comparing a detection voltage of a sensor for detecting the state of stress applied to the power transistor with the threshold voltage.

[0016] According to the above embodiments, a driving device, a power supply system, and a driving device testing method that can improve safety can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a diagram showing a configuration example of a power supply system according to the first embodiment.

[0018] Figure 2 It shows that the Figure 1 Flow chart of the test operation of the gate drive circuit in the power supply system shown in .

[0019] Figure 3 It's a picture. Figure 1 Schematic diagram of a modified example of the power transmission system shown in .

[0020] Figure 4 is a diagram showing a configuration example of a power supply system according to the second embodiment.

[0021] Figure 5 is a diagram for explaining a test operation of a gate driving circuit provided corresponding to a lower arm of an inverter circuit.

[0022] Figure 6 is a diagram for explaining a test operation of a gate driving circuit provided corresponding to an upper arm of an inverter circuit.

[0023] Figure 7 is a diagram showing a configuration example of a power supply system according to the third embodiment.

[0024] Figure 8 is a diagram showing a configuration example of a power supply system according to a fourth embodiment.

[0025] Fig. 9 : is a diagram showing a configuration example of an active mirror clamp circuit.

[0026] Fig.10 is a diagram showing a configuration example of a power supply system according to a fifth embodiment.

[0027] Fig.11 yes Fig.10Truth table of input signals and output signals of the gate drive circuit provided in the power supply system shown in .

[0028] Fig.12 It shows Fig.10 0 is a timing diagram of the operation of the gate drive circuit provided in the power supply system shown in FIG. DETAILED DESCRIPTION

[0029] For the sake of clarity of explanation, the following description and drawings are appropriately omitted and simplified. Additionally, the elements described in the drawings as function blocks for performing various processing can be configured as CPU (central processing unit), memory and other circuits in hardware, and can be implemented by a program loaded into the memory in software. Therefore, it will be appreciated by those skilled in the art that these function blocks can be implemented in various forms by hardware alone, by software alone or by their combination, and the present invention is not limited to any of them. In the drawings, the same elements are represented by the same reference numerals, and their repeated description is omitted as required.

[0030] In addition, various types of non-transitory computer-readable media can be used to store the above-mentioned program and provide it to the computer. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (e.g., floppy disks, magnetic tapes, hard disk drives), magneto-optical recording media (e.g., magneto-optical disks), CD-ROMs (read-only memories), CD-Rs, CD-R / Ws, solid-state memories (e.g., mask ROMs, PROMs (programmable ROMs), EPROMs (erasable PROMs, flash ROMs, RAMs (random access memories)). Programs can also be provided to computers via various types of temporary computer-readable media. Examples of temporary computer-readable media include electrical signals, optical signals, and electromagnetic waves, which can provide programs to computers via wired or wireless communication paths such as wires and optical fibers.

[0031] First embodiment

[0032] Figure 1 1 is a diagram showing a configuration example of a power supply system SYS1 according to the first embodiment. The power supply system SYS1 of the present embodiment is used in, for example, an inverter for driving a motor or the like.

[0033] The power supply system SYS1 according to the present embodiment includes an abnormality monitoring circuit for monitoring the state of stress applied to the power transistor TR1, and has a function of testing whether the abnormality monitoring circuit operates normally. Therefore, the power supply system SYS1 according to the present embodiment can monitor the state of stress applied to the power transistor TR1 by using a highly reliable abnormality monitoring circuit, so that the safety of the power supply system SYS1 can be improved. A specific description will be given hereinafter.

[0034] like Figure 1 As shown, the power supply system SYS1 includes a power transistor TR1 and a driving device 1 for driving the power transistor TR1.

[0035] The power transistor TR1 is an IGBT, a MOSFET, or the like, and switches whether or not power is supplied to a load such as a motor. In the present embodiment, the power transistor TR1 is an IGBT.

[0036] The driving device 1 at least includes a gate driving circuit 10 , a sensor 16 , a control circuit 17 , and a resistor Rg.

[0037] The sensor 16 detects a state of stress applied to the power transistor TR1 and outputs a detected voltage Vs. The stress applied to the power transistor TR1 includes, for example, a voltage applied to the power transistor TR1, a current flowing through the power transistor TR1, and a temperature of the power transistor TR1.

[0038] The gate drive circuit 10 controls the gate voltage Vg of the power transistor TR1 based on an instruction from the control circuit 17. Specifically, the gate drive circuit 10 includes an abnormality monitoring circuit 11, a threshold voltage setting circuit 12, a buffer 14, a gate voltage monitoring circuit 15, and a logic circuit 13. For example, these components provided in the gate drive circuit 10 are formed on the same chip.

[0039] The logic circuit 13 generates a control signal OUT according to the control signal IN from the control circuit 17. The buffer 14 drives and outputs the control signal OUT. The control signal OUT output from the buffer 14 is applied to the gate of the power transistor TR1 through the resistor Rg. Thus, the power transistor TR1 is turned on and off.

[0040] The abnormality monitoring circuit 11 monitors whether the state of stress applied to the power transistor TR1 is abnormal based on the result detected by the sensor 16. Specifically, the abnormality monitoring circuit 11 compares the detection voltage Vs output from the sensor 16 with the threshold voltage Vt set in the threshold voltage setting circuit 12, and outputs the comparison result as the monitoring result.

[0041] For example, when the detected voltage Vs is within the allowable voltage defined by the threshold voltage Vt, the abnormality monitoring circuit 11 outputs a monitoring result indicating that the stress applied to the power transistor TR1 is normal. On the other hand, when the detected voltage Vs is outside the allowable voltage defined by the threshold voltage Vt, the abnormality detection circuit 11 outputs a monitoring result indicating that the stress applied to the power transistor TR1 is abnormal.

[0042] The logic circuit 13 activates the error signal ERR1 (e.g., H level) upon receiving the monitoring result from the abnormality monitoring circuit 11 indicating that the state of the stress applied to the power transistor TR1 is abnormal. When the control circuit 17 receives the error signal ERR1 in the activated state, the control circuit 17 instructs the gate drive circuit 10 to fix the power transistor TR1 to be turned on or off depending on the type of stress (voltage, current, or heat). The gate drive circuit 10 fixes the power transistor TR1 to be turned on or off based on the instruction from the control circuit 17. Therefore, the excessive stress applied to the power transistor TR1 is eliminated, so that the breakdown and unintentional degradation of the power transistor TR1 are suppressed.

[0043] The gate voltage monitor 15 monitors the gate voltage Vg of the power transistor TR1. Specifically, the gate voltage monitor circuit 15 compares the gate voltage Vg with the reference voltage Vr to monitor whether the gate voltage Vg indicates a desired voltage level.

[0044] The logic circuit 13 compares the monitoring result by the gate voltage monitoring circuit 15 with the control signal IN output from the control circuit 17. When the monitoring result of the gate voltage monitoring circuit 15 is different from the control signal IN output from the control circuit 17, the logic circuit 13 activates the error signal ERR2, for example, sets the error signal to the H level. Upon receiving the error signal ERR2 in the activated state, the control circuit 17, for example, stops operating the gate drive circuit 10 or notifies the user that the power transistor TR1 is not operating correctly.

[0045] Here, the gate voltage monitoring circuit 15 directly monitors the gate voltage Vg of the power transistor TR1. Therefore, unlike the case where the gate voltage Vg is indirectly monitored from the internal signal of the gate drive circuit 10, the gate voltage monitoring circuit 15 can detect that the gate voltage Vg does not exhibit an expected voltage level due to, for example, an open circuit failure or a short circuit failure occurring in a terminal of the chip or a component outside the chip.

[0046] In addition, the control circuit 17 has a function of testing whether each circuit in the abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15 is operating normally, for example, at the time of system startup before the system enters normal operation, during idling, or at the time of shutdown after the system completes normal operation.

[0047] (Test Operation of Gate Driving Circuit 10)

[0048] Then, reference will be made to Figure 2 A test operation of the gate drive circuit 10 provided in the power supply system SYS1 is described. Figure 2 1 is a flowchart showing the operation of testing the gate drive circuit 10 provided in the power supply system SYS1. Hereinafter, the operation mode in which normal operation is performed is referred to as the normal operation mode, and the operation mode in which the test of whether the abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15 are operating normally is referred to as the test mode.

[0049] First, in the test mode, a normal level of stress in the normal operation mode is applied to the power transistor TR1 (step S101 ).

[0050] Thereafter, the control circuit 17 switches the level of the threshold voltage Vt set by the threshold voltage setting circuit 12 so that the detection voltage Vs is outside the range of the permissible voltage defined by the threshold voltage Vt. In other words, the control circuit 17 switches the level of the threshold voltage Vt set by the threshold voltage setting circuit 12 so as to determine that the state of the stress applied to the power transistor TR1 is abnormal in the case where the abnormality monitoring circuit 11 operates normally. (Step S102).

[0051] Thereafter, the control circuit 17 checks the monitoring results of the abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15 respectively (step S103 ).

[0052] At this time, if the state is normal, the abnormality monitoring circuit 11 outputs a monitoring result indicating that the state of the stress applied to the power transistor TR1 is abnormal, and if the state is not normal, outputs a monitoring result opposite to the state of the stress applied to the power transistor TR1. Upon receiving the monitoring result indicating that the state of the stress applied to the power transistor TR1 is abnormal from the abnormality monitoring circuit 11, the logic circuit 13 activates the error signal ERR1 (e.g., H level). The control circuit 17 receives the error signal ERR1 in the activated state to determine that the abnormality monitoring circuit 11 is operating normally.

[0053] At this time, if normal, the gate voltage monitoring circuit 15 outputs a monitoring result indicating that the gate voltage Vg of the power transistor TR1 is forcibly fixed to a predetermined voltage, and if abnormal, outputs a monitoring result opposite thereto. When the result monitored by the gate voltage monitoring circuit 15 has the same value as the control signal IN output from the control circuit 17, the logic circuit 13 sets the error signal ERR2 to deactivation (e.g., L level). The control circuit 17 determines that the gate voltage monitoring circuit 15 is operating normally by receiving the deactivated error signal ERR2.

[0054] When the control circuit 17 determines that both the abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15 are operating normally (Yes in step S104 ), the threshold voltage Vt is returned to the level used in normal operation, and then normal operation is started (step S105 → S106 ).

[0055] In contrast, when it is determined that the abnormality monitoring circuit 11 or the gate voltage monitoring circuit 15 is not operating normally (No in step S104), the control circuit 17, for example, stops operating the gate drive circuit 10, or notifies the user that the power transistor TR1 is not operating normally (step S107).

[0056] As described above, when the operation mode is the test mode, the device 1 and the power supply system SYS1 including the device 1 are configured to test the abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15 after adjusting the threshold voltage Vt so as to determine that the state of stress applied to the power transistor TR1 is abnormal in the case where the abnormality monitoring circuit 11 operates normally. Therefore, the drive device 1 and the power supply system SYS1 can monitor the state of stress applied to the power transistor TR1 by using the highly reliable abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15, so that the safety of the power supply system can be improved.

[0057] Although the reference voltage Vr supplied to the gate voltage monitoring circuit 15 is fixed in the present embodiment, the reference voltage Vr may not be fixed. The reference voltage Vr may be adjustable by the threshold voltage setting circuit 12, etc. Therefore, the gate voltage monitoring circuit 15 can be tested in more detail.

[0058] Second embodiment

[0059] Figure 4 1 is a diagram illustrating a configuration example of a power supply system SYS1a according to a second embodiment. In the power supply system SYS1a, the abnormality monitoring circuit 11 is configured to monitor a voltage applied to the power transistor TR1. A detailed description will be given hereinafter. Figure 4 As shown, the power supply system SYS1a includes a power transistor TR1 and a driving device 1a for driving the power transistor TR1. The driving device 1a includes at least a gate driving circuit 10a, a sensor 16a, a control circuit 17 and a resistor Rg.

[0060] The sensor 16a corresponds to the sensor 16 and includes resistors R1 and R2. The resistive elements R1 and R2 are provided in series between the collector (first terminal) and the emitter (second terminal) of the power transistor TR1. The sensor 16a outputs the voltage of the node N11 between the resistor R1 and the resistor R2 as the detection voltage Vs. The detection voltage Vs increases as the voltage applied to the power transistor TR1 increases, and decreases as the voltage applied to the power transistor TR1 decreases.

[0061] The gate drive circuit 10a corresponds to the gate drive circuit 10, and includes a comparator CMP1a, a comparator CMP2, a logic circuit 13, a buffer 14, a register 121, and a digital-to-analog converter (DAC) 122. The comparator CMP1a serves as the abnormality monitoring circuit 11. The comparator CMP2 serves as the gate voltage monitoring circuit 15. The register 121 and the DA converter 122 serve as the threshold voltage setting circuit 12.

[0062] The register 121 stores information (digital value) DT of a threshold voltage Vt specified by the control circuit 17. The DA converter 122 converts the digital value DT stored in the register 121 into the threshold voltage Vt and outputs the threshold voltage Vt.

[0063] The comparator CMP1a compares the threshold voltage Vt with the detection threshold voltage Vs, and outputs the comparison result as the monitoring result performed by the abnormality monitoring circuit 11. For example, when the detection voltage Vs is less than the threshold voltage Vt, the comparator CMP1a outputs an L-level monitoring result indicating that the voltage applied to the power transistor TR1 is within the normal range. When the detection voltage Vs is equal to or higher than the threshold voltage Vt, the comparator CMP1a outputs an H-level monitoring result indicating that the voltage applied to the power transistor TR1 is in an overvoltage state.

[0064] The logic circuit 13 activates the error signal ERR1 upon receiving the H level monitoring result from the comparator CMP1a. When receiving the error signal ERR1 in the activated state, the control circuit 17 instructs the gate drive circuit 10a to forcibly turn on the power transistor TR1. The gate driver 10a forcibly turns on the power transistor TR1 by fixing the gate voltage Vg of the power transistor TR1 to the H level. This eliminates the overvoltage state of the power transistor TR1, thereby suppressing the breakdown and unintentional degradation of the power transistor TR1.

[0065] The comparator CMP2 compares the gate voltage Vg with the reference voltage Vr and outputs the comparison result as the monitoring result performed by the gate voltage monitoring circuit 15. The specific operation of the comparator CMP2 and the operations of the logic circuit 13 and the control circuit based on the monitoring result of the comparator CMP2 are the same as those of the gate voltage monitoring circuit 15, the logic circuit 13, and the control circuit 17 according to the first embodiment, and thus a description thereof is omitted.

[0066] (Test Operation of Gate Driving Circuit 10a)

[0067] Subsequently, a test operation of the gate drive circuit 10 a provided in the power supply system SYS1 a will be described.

[0068] First, in the test mode, a normal level voltage in the normal operation mode is applied to the power transistor TR1. Specifically, for example, a voltage of 400 V is applied to the collector of the power transistor TR1. At this time, the detection voltage Vs indicates, for example, 4V which is one hundredth of the collector voltage.

[0069] Thereafter, the control circuit 17 switches the level of the threshold voltage Vt so that the detection voltage Vs becomes equal to or higher than the threshold voltage Vt. In other words, the control circuit 17 lowers the level of the threshold voltage Vt (for example, from normal 6V to 3V) so that if the comparator CMP1a operates normally, an H-level monitoring result indicating that the power transistor TR1 is in an overvoltage state is output.

[0070] Thereafter, the controller 17 confirms the monitoring results of the comparators CMP1a and CMP2.

[0071] At this time, since the detection voltage Vs (=4V) becomes higher than the threshold voltage Vt (=3V), the comparator CMP1a outputs a monitoring result of an H level when the threshold voltage Vt is normal, and outputs a monitoring result of an L level when the threshold voltage Vt is abnormal. The logic circuit 13 receives the monitoring result of the H level from the comparator CMP1a to activate the error signal ERR1 (e.g., H level). The control circuit 17 receives the error signal ERR1 in the activated state to determine that the comparator CMP1a is operating normally.

[0072] At this time, if the gate voltage Vg is normal, the comparator CMP2 outputs a monitoring result of an H level indicating that the gate voltage Vg of the power transistor TR1 is forcibly fixed to an H level, and if the gate voltage Vg is abnormal, a monitoring result of an L level is output. When the monitoring result performed by the comparator CMP2 indicates the same value (H level) as the control signal IN output from the control circuit 17, the logic circuit 13 sets the error signal ERR2 to deactivation (e.g., L level). The control circuit 17 receives the deactivated error signal ERR2, and the control circuit 17 determines that the comparator CMP2 is operating normally.

[0073] When it is determined that both comparators CMP1a and CMP2 are operating normally, the control circuit 17 starts normal operation after returning the threshold voltage Vt to the level (e.g., 6V) used in normal operation. On the contrary, if it is determined that one of the comparators CMP1a or CMP2 is not operating normally, the control circuit 17, for example, stops the operation of the gate drive circuit 10a, or notifies the user that the power transistor TR1 is not operating normally. The remaining configuration and operation of the drive device 1a are the same as those of the drive device 1, so the description thereof is omitted.

[0074] As described above, when the operation mode is the test mode, the device 1a and the power supply system SYS1a including the device 1a are configured to test the comparators CMP1a and CMP2 after lowering the threshold voltage Vt so that if the comparator CMP1a operates normally, it is determined that the applied voltage of the power transistor TR1 is in an overvoltage state. Therefore, the drive device 1a and the power supply system SYS1a having the device 1a can monitor the applied voltage of the power transistor TR1 using reliable comparators CMP1a and CMP2, so that safety can be improved. It should be noted that the drive device 1a and the power supply system SYS1a provided with the drive device can be easily tested without generating a high voltage.

[0075] (Application example of power supply system SYS1a and its test operation)

[0076] Next, an application example of the power supply system SYS1a and a test operation thereof will be described. In the present embodiment, the power supply system SYS1a is applied to an inverter circuit.

[0077] Figure 5 is a diagram for explaining a test operation of a gate driving circuit provided corresponding to a lower arm of an inverter circuit. Figure 6 is a diagram for explaining a test operation of a gate driving circuit provided corresponding to an upper arm of an inverter circuit.

[0078] like Figure 5 and Figure 6As shown, the inverter circuit includes a power transistor TR1_1, a power transistor TR1_2, gate drive circuits 10_1 and 10_2, and sensors 16_1 and 16_2. The power transistors TR1_1 and TR1_2 are provided in series between a power supply voltage terminal (hereinafter referred to as the power supply voltage terminal Vbus) supplied with a power supply voltage Vbus and a ground voltage terminal GND. Each of the power transistors TR1_1 and TR1_2 corresponds to the power transistor TR1, and respectively constitutes an upper arm and a lower arm of the inverter circuit.

[0079] Each of the sensors 16_1 and 16_2 corresponds to the sensor 16a and detects the applied voltage of the power transistors TR1_1 and TR1_2, respectively. Each of the gate drive circuits 10_1 and 10_2 corresponds to the gate drive circuit 10a and drives the gates of the power transistors TR1_1 and TR1_2, respectively.

[0080] First, refer to Figure 5 A test operation of the gate drive circuit 10_2 provided corresponding to the lower arm TR1_2 is described.

[0081] In the initial state, in a state where both power transistors TR1_1 and TR1_2 are turned off, a power supply voltage Vbus of, for example, 400V is applied to the power supply voltage terminal. The threshold voltage Vt of each of the gate drive circuits 10_1 and 10_2 is set to, for example, 600V.

[0082] Thereafter, the power transistor TR1_1 is switched from off to on while the power transistor TR1_2 remains off. Therefore, the output terminal between the power transistors TR1_1 and TR1_2 is precharged to the power supply voltage Vbus level 400V. After the precharge is completed, the power transistor TR1_1 is switched from on to off again. At this time, the voltage of the power supply voltage Vbus is applied between the collector and emitter of the power transistor TR1_2.

[0083] Thereafter, the threshold voltage Vt of the gate drive circuit 10_2 is switched to a voltage level lower than the power supply voltage Vbus, for example, 300 V. Therefore, a test of the abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15 provided in the gate drive circuit 10_2 is performed. When the abnormality monitoring circuit 11 provided in the gate drive circuit 10_2 operates normally, the power transistor TR1_2 is forcibly controlled to be turned on.

[0084] Next, we will refer to Figure 6 A test operation of the gate driving circuit 10_1 provided corresponding to the upper arm TR1_1 is described.

[0085] In the initial state, in a state where both power transistors TR1_1 and TR1_2 are turned off, a power supply voltage Vbus of, for example, 400V is applied to the power supply voltage terminal. The threshold voltage Vt of each of the gate drive circuits 10_1 and 10_2 is set to, for example, 600V.

[0086] Thereafter, while the power transistor TR1_1 remains off, the power transistor TR1_2 is switched from off to on. Therefore, the output terminal between the power transistors TR1_1 and TR1_2 is precharged to the ground voltage GND level (0V). After the precharge is completed, the power transistor TR1_2 is switched from on to off again. At this time, the voltage of the power supply voltage Vbus is applied between the collector and emitter of the power transistor TR1_1.

[0087] Thereafter, the threshold voltage Vt of the gate driving circuit 10_1 is switched to a voltage level lower than the power supply voltage Vbus, for example, 300 V. Therefore, a test of the abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15 provided in the gate driving circuit 10_1 is performed. When the abnormality monitoring circuit 11 provided in the gate driving circuit 10_1 operates normally, the power transistor TR1_1 is forcibly controlled to be turned on.

[0088] As described above, the power supply system SYS1a applied to the inverter circuit tests the gate drive circuits 10_1 and 10_2 without short-circuiting the power supply voltage terminal Vbus and the ground voltage terminal GND. This suppresses damage and unintentional deterioration of the power transistors TR1_1 and TR1_2 and the load of the motor due to the short-circuit current.

[0089] Third embodiment

[0090] Figure 7 1 is a diagram illustrating a configuration example of a power supply system SYS1b according to the third embodiment. In the power supply system SYS1b, the abnormality monitoring circuit 11 is configured to monitor a current flowing through the power transistor TR1. A specific description will be given hereinafter.

[0091] like Figure 7 As shown, the power supply system SYS1b includes a power transistor TR1 and a driving device 1b for driving the power transistor TR1. The driving device 1b includes at least a gate driving circuit 10b, a sensor 16b, a control circuit 17, and a resistor Rg. In this embodiment, the power transistor TR1 is a multi-emitter IGBT. For example, 1 / 10000 of the current of the emitter flows through the current sensing emitter of the multi-emitter IGBT.

[0092] The sensor 16b corresponds to the sensor 16 and includes a resistor Rs. The sensor 16b converts the current flowing through the current sensing emitter of the power transistor TR1 into a detection voltage Vs using the resistor Rs and outputs the detection voltage Vs. As the current flowing through the power transistor TR1 increases, the detection voltage Vs increases, and as the current flowing through the power transistor TR1 decreases, the detection voltage Vs decreases.

[0093] The gate drive circuit 10b corresponds to the gate drive circuit 10, and includes a comparator CMP1b, a comparator CMP2, a logic circuit 13, a buffer 14, a register 121, and a digital-to-analog converter 122. The comparator CMP1b serves as the abnormality monitoring circuit 11. The comparator CMP2 serves as the gate voltage monitoring circuit 15. The register 121 and the DA converter 122 serve as the threshold voltage setting circuit 12.

[0094] The comparator CMP1 b compares the threshold voltage Vt with the detection threshold voltage Vs, and outputs the comparison result as a monitoring result performed by the abnormality monitoring circuit 11 .

[0095] For example, when the detection voltage Vs is less than the threshold voltage Vt, the comparator CMP1b outputs an L-level monitoring result indicating that the current flowing through the power transistor TR1 is within a normal range. When the detection voltage Vs is equal to or higher than the threshold voltage Vt, the comparator CMP1b outputs an H-level monitoring result indicating that the current flowing through the power transistor TR1 is in an overcurrent state.

[0096] The logic circuit 13 activates the error signal ERR1 upon receiving the H level monitoring result from the comparator CMP1b. When receiving the error signal ERR1 in the activated state, the control circuit 17 instructs the gate drive circuit 10b to forcibly turn off the power transistor TR1. The gate driver 10b forcibly turns off the power transistor TR1 by fixing the gate voltage Vg of the power transistor TR1 to the L level. This eliminates the overcurrent state of the power transistor TR1, thereby suppressing the breakdown and unintentional degradation of the power transistor TR1.

[0097] The comparator CMP2 compares the gate voltage Vg with the reference voltage Vr and outputs the comparison result as the monitoring result performed by the gate voltage monitoring circuit 15. The specific operation of the comparator CMP2 and the operations of the logic circuit 13 and the control circuit based on the monitoring result of the comparator CMP2 are the same as those of the gate voltage monitoring circuit 15, the logic circuit 13, and the control circuit 17 according to the first embodiment, and thus a description thereof is omitted.

[0098] (Test Operation of Gate Driving Circuit 10b)

[0099] Subsequently, a test operation of the gate drive circuit 10 b provided in the power supply system SYS1 b will be described.

[0100] First, in the test mode, a normal level current in the normal operation mode is supplied to the power transistor TR1.

[0101] Thereafter, the control circuit 17 switches the level of the threshold voltage Vt so that the detection voltage Vs becomes equal to or higher than the threshold voltage Vt. In other words, the control circuit 17 lowers the level of the threshold voltage Vt so that if the comparator CMP1b operates normally, an H-level monitoring result indicating that the current flowing through the power transistor TR1 is in an overcurrent state is output.

[0102] Although the present embodiment illustrates the case where a current flows through the power transistor TR1 and reduces the level of the threshold voltage Vt in the test mode, the present invention is not limited to this case. For example, the threshold voltage Vt may be reduced to a negative threshold voltage without causing a current to flow through the power transistor TR1. Alternatively, a DC offset may be added between the two inputs of the comparator CMP1b without causing a current to flow through the power transistor TR1.

[0103] Thereafter, the controller 17 confirms the monitoring results of the comparators CMP1 b and CMP2 .

[0104] At this time, if the comparator CMP1b is normal, the comparator CMP1b outputs a monitoring result of an H level, and if the comparator CMP1b is abnormal, it outputs a monitoring result of an L level. The logic circuit 13 receives the monitoring result of the H level from the comparator CMP1b to activate the error signal ERR1 (e.g., H level). The control circuit 17 receives the error signal ERR1 in an activated state to determine that the comparator CMP1b is operating normally.

[0105] At this time, if the comparator CMP2 is normal, the comparator outputs a monitoring result of an L level indicating that the gate voltage Vg of the power transistor TR1 is forcibly fixed to an L level within a predetermined period of time, for example, within 1 μs, and if the gate voltage Vg is abnormal, a monitoring result of an H level is output. When the monitoring result performed by the comparator CMP2 indicates the same value (L level) as the control signal IN output from the comparator 17, the logic circuit 13 deactivates the error signal ERR2 (for example, an L level). The control circuit 17 receives the deactivated error signal ERR2, and the control circuit 17 determines that the comparator CMP2 is operating normally.

[0106] When the control circuit 17 determines that all the comparators CMP1b and CMP2 are operating normally, the control circuit 17 returns the threshold voltage Vt to the level used in the normal operation and then starts the normal operation. On the contrary, if it is determined that one of the comparators CMP1b or CMP2 is not operating normally, the control circuit 17 stops the operation of the gate drive circuit 10b, for example, or notifies the user that the power transistor TR1 is not operating correctly.

[0107] The remaining configuration and operation of the driving device 1 b are the same as those of the driving device 1 , and thus description thereof is omitted.

[0108] In this way, when the operation mode is the test mode, the device 1b and the power supply system SYS1b including the device 1bs are configured to test the comparators CMP1b and CMP2 after lowering the threshold voltage Vt so that if the comparator CMP1b operates normally, it is determined that the current flowing through the power transistor TR1 is in an overcurrent state. Therefore, since the state of the current flowing through the power transistor TR1 can be monitored using the reliable comparators CMP1b and CMP2, the drive device 1b and the power supply system SYS1b having the drive device 1b can improve safety. By the way, the drive device 1b and the power supply system SYS1b having the drive device 1b can be easily tested without generating an overcurrent.

[0109] In the present embodiment, the power transistor TR1 is a multi-emitter IGBT, and the current flowing through the current sensing emitter of the power transistor TR1 is converted into the detection voltage Vs and used, but the present invention is not limited thereto. The power transistor TR1 may be a multi-source MOSFET, and the current flowing in the current sensing source of the power transistor TR1 may be converted into the detection voltage Vs and used. Additionally, for example, by utilizing the phenomenon that the collector-emitter voltage of the IGBT increases as the collector current of the IGBT increases, a voltage proportional to the collector-emitter voltage of the power transistor TR1 may be used as the detection voltage Vs (hereinafter, this current detection system is referred to as a DESAT method).

[0110] When the DESAT system is adopted, in the test mode, the power transistor TR1 is turned off to increase the collector voltage, thereby allowing the comparator CMP1c to test whether the overcurrent state of the power transistor TR1 is detected. However, in the normal operation mode, when the power transistor TR1 is turned off, even if the collector voltage increases, the comparator CMP1b needs to consider that the power transistor TR1 is not abnormal.

[0111] Fourth embodiment

[0112] Figure 81 is a diagram illustrating a configuration example of a power supply system SYS1c according to a fourth embodiment. In the power supply system SYS1c, the abnormality monitoring circuit 11 is configured to monitor the temperature of the power transistor TR1. Hereinafter, a specific description will be given.

[0113] like Figure 8 As shown, the power supply system SYS1c includes a power transistor TR1 and a driving device 1c for driving the power transistor TR1. The driving device 1c includes at least a gate drive circuit 10c, a sensor 16c, a control circuit 17, and a resistor Rg. The sensor 16c corresponds to the sensor 16, and includes a constant current source I1 and a diode D1. The diode D1 is provided near the power transistor TR1, for example, on a chip on which the power transistor TR1 is formed. Therefore, the temperature of the diode D1 is equal to the temperature of the power transistor TR1. On the other hand, the constant current source I1 is provided, for example, on a chip on which the gate drive circuit 10c is mounted.

[0114] The constant current output from the constant current source I1 flows through the diode D1. The sensor 16c outputs the forward voltage of the diode D1 as the detection voltage Vs. Even at normal temperature, the detection voltage Vs is higher than the 0V voltage. Specifically, even at room temperature, the detection voltage Vs indicates a value that is approximately an intermediate value between 0V and the logic power supply voltage or the analog power supply voltage. In addition, the forward voltage of the diode D1 becomes smaller as the temperature of the power transistor TR1 increases, and becomes larger as the temperature of the power transistor TR1 decreases. The sensor 16c is not limited to the above configuration, and may be configured by a thermistor or a thermocouple.

[0115] The gate drive circuit 10c corresponds to the gate drive circuit 10, and includes a comparator CMP1c, a comparator CMP2, a logic circuit 13, a buffer 14, a register 121, and a digital-to-analog converter 122. The comparator CMP1c serves as the abnormality monitoring circuit 11. The comparator CMP2 serves as the gate voltage monitoring circuit 15. The register 121 and the DA converter 122 serve as the threshold voltage setting circuit 12.

[0116] The comparator CMP1c compares the threshold voltage Vt with the detection threshold voltage Vs, and outputs the comparison result as the monitoring result performed by the abnormality monitoring circuit 11. For example, when the detection voltage Vs is equal to or higher than the threshold voltage Vt, the comparator CMP1c outputs an L-level monitoring result indicating that the temperature of the power transistor TR1 is within a normal range. When the detection voltage Vs is less than the threshold voltage Vt, the comparator CMP1c outputs an H-level monitoring result indicating that the temperature of the power transistor TR1 is overheated.

[0117] The logic circuit 13 activates the error signal ERR1 upon receiving the H level monitoring result from the comparator CMP1c. ​​When receiving the error signal ERR1 in the activated state, the control circuit 17 instructs the gate drive circuit 10c to forcibly turn off the power transistor TR1. The gate driver 10c forcibly turns off the power transistor TR1 by fixing the gate voltage Vg of the power transistor TR1 to the L level. This eliminates overheating of the power transistor TR1, thereby suppressing breakdown and unintentional degradation of the power transistor TR1.

[0118] The comparator CMP2 compares the gate voltage Vg with the reference voltage Vr, and outputs the comparison result as the monitoring result performed by the gate voltage monitoring circuit 15. The specific operation of the comparator CMP2 and the operations of the logic circuit 13 and the control circuit based on the monitoring result of the comparator CMP2 are the same as those of the gate voltage monitoring circuit 15, the logic circuit 13, and the control circuit 17 according to the first embodiment, and thus a description thereof is omitted.

[0119] (Test Operation of Gate Driving Circuit 10c)

[0120] Subsequently, the test operation of the gate drive circuit 10c provided in the power supply system SYS1c will be described. First, in the test mode, the power transistor TR1 is set to a normal temperature. Thereafter, the control circuit 17 switches the level of the threshold voltage Vt so that the detection voltage Vs becomes equal to or higher than the threshold voltage Vt. In other words, the control circuit 17 lowers the level of the threshold voltage Vt so that if the comparator CMP1c operates normally, the monitoring result of the H level indicating that the temperature of the power transistor TR1 is overheated is output.

[0121] Thereafter, the controller 17 confirms each monitoring result of the comparators CMP1c and CMP2.

[0122] At this time, if the comparator CMP1c is normal, the comparator CMP1c outputs a monitoring result of an H level, and if the comparator CMP1c is abnormal, it outputs a monitoring result of an L level. The logic circuit 13 receives the monitoring result of the H level from the comparator CMP1c to activate the error signal ERR1 (e.g., H level). The control circuit 17 receives the error signal ERR1 in an activated state to determine that the comparator CMP1c is operating normally.

[0123] At this time, if the comparator CMP2 is normal, the comparator outputs a monitoring result of an L level indicating that the gate voltage Vg of the power transistor TR1 is forcibly fixed to an L level within a predetermined period of time, for example, within 1 μs, and if the gate voltage Vg is abnormal, a monitoring result of an H level is output. When the monitoring result performed by the comparator CMP2 indicates the same value (L level) as the control signal IN output from the comparator 17, the logic circuit 13 deactivates the error signal ERR2 (for example, an L level). The control circuit 17 receives the deactivated error signal ERR2, and the control circuit 17 determines that the comparator CMP2 is operating normally.

[0124] When the control circuit 17 determines that both the comparators CMP1c, CMP2 are operating normally, the control circuit 17 returns the threshold voltage Vt to the level used in the normal operation and then starts the normal operation. Incidentally, if it is determined that one of the comparators CMP1c and CMP2 is not operating normally, the control circuit 17, for example, stops the operation of the gate drive circuit 10c, or notifies the user that the power transistor TR1 is not operating correctly. The remaining configuration and operation of the drive device 1c are the same as those of the drive device 1, so the description thereof is omitted.

[0125] As described above, when the operation mode is the test mode, the drive device 1c of the present embodiment and the power supply system SYS1c including the drive device 1c are configured to test the comparators CMP1c and CMP2 after lowering the threshold voltage Vt so as to determine that the power transistor TR1 is overheated if the comparator CMP1c operates normally. Therefore, the state of the current flowing through the power transistor TR1 can be monitored using the reliable comparators CMP1c and CMP2, so that the safety of the drive device 1c and the power supply system SYS1c having the drive device can be improved. It should be noted that the drive device 1c and the power supply system SYS1c provided with the drive device can be easily tested without overheating.

[0126] Fifth embodiment

[0127] The gate voltage monitoring circuit 15 according to the first to fourth embodiments may use a comparator provided in an active mirror clamp circuit to be described later. This suppresses an increase in the circuit scale of the gate drive circuit 10. Additionally, the active mirror clamp circuit may have a function of detecting whether noise is generated in the gate of the power transistor TR1, which noise is likely to cause erroneous ignition. Hereinafter, a specific description will be given.

[0128] First, a general active mirror clamp circuit will be described. Generally, when the collector voltage of the off-state power transistor TR1 rises sharply, the rise of the collector voltage is propagated to the gate through the feedback capacitor formed between the gate and the collector, and the gate voltage Vg rises unintentionally. Here, if the gate voltage Vg rises above the threshold voltage of the power transistor TR1, the power transistor TR1 is unintentionally turned on, so that the power transistor TR1 may be unintentionally damaged or deteriorated. In order to solve such a problem, the gate drive circuit 10 is generally provided with an active mirror clamp circuit for clamping the gate of the power transistor TR1.

[0129] Fig. 9 2 is a diagram showing a configuration example of the active mirror clamp circuit 20. Fig. 9 As shown, the active mirror clamp circuit 20 includes a comparator 21, a switch circuit 22, a buffer 23, and an N-channel MOS transistor MN1 (switching element; hereinafter simply referred to as a transistor).

[0130] The comparator 21 compares the gate voltage Vg of the power transistor TR1 with the reference voltage Vr and outputs a comparison result. Specifically, when the gate voltage Vg is equal to or higher than the reference voltage Vr, the comparator 21 outputs a comparison result of an L level, and when the gate voltage Vg is less than the reference voltage Vr, the comparator 21 outputs a comparison result of an H level. Note that the reference voltage Vr indicates a value lower than a boundary value (threshold) at which the power transistor TR1 is turned on and off.

[0131] The switch circuit 22 switches from the H level to the L level in response to the control signal IN (OUT) output from the control circuit 17, and switches the power transistor TR1 from on to off. Then, the gate voltage Vg is further reduced to be less than the reference voltage Vr, and the switch circuit 22 switches the control signal AMC from the L level to the H level.

[0132] The control signal AMC is applied to the gate of the transistor MN1 via the buffer 23. The transistor MN1 is provided between the gate of the power transistor TR1 and the ground voltage terminal, and is turned on and off based on the control signal AMC. For example, when the control signal AMC is switched from the L level to the H level, the transistor TR1 is switched from the off state to the on state in response to the control signal AMC. Therefore, the gate voltage Vg of the power transistor TR1 drops rapidly to the ground level. Note that even during the period when the control signal IN indicates the L level, when the gate voltage Vg temporarily rises above the reference voltage Vr, the switch circuit 22 continues to output the control signal AMC at the H level. Therefore, the gate voltage Vg of the power transistor TR1 is maintained at the ground level.

[0133] At this time, the gate voltage Vg of the power transistor TR1 is directly fixed to the ground level without passing through the resistor Rg. Therefore, even when the collector voltage Vc of the power transistor TR1 in the off state rises sharply, the rise of the gate voltage Vg is suppressed. Therefore, the power transistor TR1 is not turned on unintentionally, thereby suppressing the breakdown and unintentional degradation of the power transistor TR1.

[0134] During the turn-off process of the power transistor TR1, the gate voltage Vg is controlled by the control signal OUT supplied from the control circuit 17 via the resistor Rg until the gate voltage Vg drops below the boundary value (threshold) at which the power transistor TR1 is turned on and off. In addition, during the turn-on process of the power transistor TR1, the gate voltage Vg is controlled by the control signal OUT supplied from the control circuit 17 via the resistor Rg. Therefore, the on / off switching speed of the power transistor TR1 can be controlled to a desired speed by the control circuit 17 without being affected by the clamping of the active mirror clamp circuit 20.

[0135] Next, an active mirror clamp circuit according to the present embodiment having a function of detecting the occurrence of noise in the gate of the power transistor TR1 will be described. In the following explanation, a comparator provided in the active mirror clamp circuit according to the present embodiment is also used as the gate voltage monitoring circuit 15.

[0136] Fig.10 1 is a diagram showing a configuration example of a power supply system SYS1d according to the fifth embodiment. Fig.10 As shown, the power supply system SYS1d includes a power transistor TR1 and a driving device 1d for driving the power transistor TR1. The driving device 1d includes at least a gate driving circuit 10d, a control circuit 17 and a resistor Rg. Fig.10 In the example shown in , components corresponding to the abnormality monitoring circuit 11 are omitted from among the components of the gate drive circuit 10d. Therefore, the sensor 16 is also omitted.

[0137] The gate drive circuit 10d includes a comparator 21, a switch circuit 22d, a buffer 23, and a transistor MN1, which are constituent elements of the active mirror clamp circuit 20. Specifically, the gate drive circuit 10d includes a comparator 21, a switch circuit 22d, a buffer 14, a buffer 23, a transistor MN1, a register 123, and a D / A converter 124. The comparator 21 also functions as a gate voltage monitoring circuit 15. The switch circuit 22d also functions as a logic circuit 13. The register 123 and the DA converter 124 function as a setting circuit for setting the level of the reference voltage Vr. The level of the reference voltage Vr is adjustable.

[0138] The switch circuit 22d is a modified example of the switch circuit 22, and has, for example, an SR latch circuit 221 and a logical product circuit 222. In the SR latch circuit 221, the control signal IN from the control circuit 17 is input to the reset terminal R, the comparison result Vcmp of the comparator 21 is input to the set terminal S, and the control signal AMC is output from the output terminal Q. In this example, when the set and reset of the SR latch circuit 221 are input at the same time, the reset is prioritized. The logical product circuit 222 outputs the logical product of the control signal AMC and the inverted signal of the comparison result of the comparator 21 as the error signal ERR2.

[0139] Fig.11 It is a truth table of the input signal and output signal of the gate drive circuit 10d. Fig.12 10d is a timing chart showing the operation of the gate drive circuit 10d. Fig.11 and Fig.12 As shown, when the control signal IN output from the control circuit 17 is at the H level, the control signal AMC indicates the L level regardless of the comparison result Vcmp, and the error signal ERR2 indicates the L level. Thereafter, when the control signal IN is switched from the H level to the L level, the voltage of the control signal OUT, that is, the gate voltage Vg, decreases according to the change. However, during the period in which the voltage Vg of the control signal OUT is equal to or higher than the reference voltage Vr (for example, 3V), the comparison result Vcmp indicates the L level. At this time, the control signal AMC indicates the L level, and the error signal ERR2 indicates the L level, which indicates that an error has not occurred.

[0140] Since the control signal AMC indicates the L level, the transistor MN1 is turned off. Thereafter, when the voltage Vg of the control signal OUT becomes lower than the reference voltage Vr, the comparison result Vcmp switches from the L level to the H level. Therefore, the control signal AMC switches from the L level to the H level. The error signal ERR2 maintains the L level.

[0141] Since the control signal AMC indicates the H level, the transistor MN1 is turned on. After that, when the voltage Vg of the control signal OUT temporarily becomes equal to or higher than the reference voltage Vr due to noise or the like, even if the control signal IN indicates the L level, the comparison result Vcmp is temporarily switched to the L level. At this time, the error signal ERR2 is switched from the L level to the H level, indicating that the gate voltage Vg has unintentionally risen. At this time, the control signal AMC maintains the H level. Therefore, the transistor MN1 maintains the on state.

[0142] Upon receiving the H-level error signal ERR2, the control circuit 17 stops the operation of the gate drive circuit 10d, for example, or notifies the user that the power transistor TR1 is not operating correctly.

[0143] At this time, the control circuit 17 may suppress the degree of increase in the noise generated in the gate voltage Vg by, for example, reducing the switching speed of the power transistor TR1 or adjusting various other parameters.

[0144] Before normal operation, for example, by performing switching control of the power transistor TR1 while adjusting the reference voltage Vr, it is observed that the value of the gate voltage Vg including the noise component has a margin until the gate voltage Vg reaches the threshold value for switching the power transistor TR1 from off to on. The control circuit 17 can effectively adjust the switching speed by using the observation result.

[0145] For example, the threshold of the gate voltage Vg that switches the power transistor TR1 from the off state to the on state is set to 5.0V. Additionally, it is assumed that the gate voltage Vg is allowed to rise up to 2.0V due to the switching operation. In this example, with the reference voltage Vr set to 2.0V, by increasing the gate drive current as much as possible within the range where no error is detected and increasing the switching speed, a parameter setting value that can suppress the switching loss and prevent mis-ignition due to the switching operation can be automatically searched. When the search and adjustment of the parameter setting value are completed, the value of the register 123 is rewritten by the control circuit 17, and the reference voltage Vr returns to the level (e.g., 3V) used in normal operation.

[0146] Therefore, the drive device 1c and the power supply system SYS1d having the drive device 1c according to the present embodiment utilize the comparator provided in the active mirror clamp circuit to realize the gate voltage monitoring circuit 15. Therefore, the drive device 1c and the power supply system SYS1d having the drive device 1c can suppress an increase in circuit size.

[0147] In the drive device 1 and the power supply system SYS1d including the drive device 1 according to the present embodiment, the active mirror clamp circuit has a function of detecting whether noise is generated at the gate of the power transistor TR1, which noise may cause erroneous ignition. Therefore, the drive device 1 and the power supply system SYS1d having the drive device can, for example, adjust the switching speed to reduce the noise when noise that may cause erroneous ignition is detected at the gate of the power transistor TR1. Thereby, safety is improved.

[0148] As described above, the driving device, the power supply system, and the test method of the driving device according to the first to fifth embodiments are configured to test the abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15 after adjusting the threshold voltage Vt, so that when the operation mode is the test mode, if the abnormality monitoring circuit 11 operates normally, the state of the stress applied to the power transistor TR1 is determined to be abnormal. Therefore, the driving device and the power supply system according to the above-mentioned first to fifth embodiments can monitor the state of the stress applied to the power transistor TR1 by using the highly reliable abnormality monitoring circuit 11 and the gate voltage monitoring circuit 15. The safety of the driving device and the power supply system can be improved.

[0149] Although the invention made by the inventors has been specifically described based on the embodiments, the present invention is not limited to the embodiments that have been described, and it goes without saying that various modifications can be made without departing from the gist thereof.

[0150] In the above-described first to fifth embodiments, the power transistor TR1 is an IGBT, but is not limited to the IGBT. The power transistor TR1 may be, for example, a transistor other than the IGBT such as a MOSFET.

[0151] In addition, in the first to fifth embodiments described above, an example has been described when the gate voltage monitoring circuit 15 (or a circuit equivalent thereto) is provided, but it is not limited thereto. Of the abnormality monitoring circuit 11 (or a circuit corresponding thereto) and the gate voltage monitoring circuit 15 (or a circuit corresponding thereto), at least only the abnormality monitoring circuit 11 is required.

[0152] For example, in the above-described embodiments according to the semiconductor device, the conductivity type (p-type or n-type) of the semiconductor substrate, the semiconductor layer, the diffusion layer (diffusion region), etc. may be reversed. Therefore, in the case where one of the n-type and p-type conductivity types is the first conductivity type and the other conductivity type is the second conductivity type, the first conductivity type may be the p-type and the second conductivity type may be the n-type, or conversely, the first conductivity type may be the n-type and the second conductivity type may be the p-type.

Claims

1. A driving device, comprising: a sensor configured to detect and output a state of stress applied to the power transistor as a detection voltage; a threshold voltage setting circuit configured to output a threshold voltage; an abnormality monitoring circuit configured to determine whether the state of the stress applied to the power transistor is abnormal by comparing the detection voltage with the threshold voltage; as well as a control circuit configured to fix the power transistor to be turned on or off according to the type of the stress when the abnormality monitoring circuit determines that the state of the stress is abnormal, Wherein, when the operation mode is the test mode, the control circuit is further configured to test whether the abnormality monitoring circuit determines that the state of the stress is abnormal by switching the level of the threshold voltage set by the threshold voltage setting circuit, so as to determine that the state of the stress applied to the power transistor is abnormal in the abnormality monitoring circuit in normal operation, The driving device further comprises a gate voltage monitoring circuit, wherein the gate voltage monitoring circuit is configured to monitor the gate voltage of the power transistor. wherein the control circuit is configured to fix the gate voltage of the power transistor to a predetermined voltage according to the type of the stress when the abnormality monitoring circuit determines that the state of the stress is abnormal, and The control circuit is configured to test whether the gate voltage monitoring circuit determines that the gate voltage is fixed to the predetermined voltage when the operation mode is a test mode.

2. The driving device according to claim 1, in, The stress is the voltage applied to the power transistor, wherein the abnormality monitoring circuit is configured to determine whether the voltage applied to the power transistor is in an overvoltage state by comparing the detection voltage output from the sensor according to the power transistor applied to the power transistor with the threshold voltage, and The control circuit is configured to forcibly turn on the power transistor when it is determined by the abnormality monitoring circuit that the voltage applied to the power transistor is in an overvoltage state.

3. The driving device according to claim 2, in, The sensor comprises a first resistive element and a second resistive element, the first resistive element and the second resistive element being arranged in series between a first terminal and a second terminal of the power transistor, and The sensor outputs a voltage at a node between the first resistive element and the second resistive element as the detection voltage.

4. The driving device according to claim 1, in, The stress is the current flowing through the power transistor, wherein the abnormality monitoring circuit is configured to determine whether the current flowing through the power transistor is in an overcurrent state by comparing the detection voltage output from the sensor according to the current flowing through the power transistor with the threshold voltage, and The control circuit is configured to forcibly turn off the power transistor when the abnormality monitoring circuit determines that the current flowing through the power transistor is in an overcurrent state.

5. The driving device according to claim 4, in, The power transistor is an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET), and The sensor is configured to output a collector voltage or a drain voltage of the power transistor as the detection voltage, wherein the collector voltage or the drain voltage indicates a voltage value corresponding to a collector current or a drain current of the power transistor.

6. The driving device according to claim 4, in, The power transistor is a multi-emitter insulated gate bipolar transistor (IGBT) or a multi-source metal oxide semiconductor field effect transistor (MOSFET), and The sensor has a resistor, and the resistor is used to convert the current output from the current sensing emitter or the current sensing source of the power transistor into the detection voltage.

7. The driving device according to claim 1, in, The stress is the temperature of the power transistor, wherein the abnormality monitoring circuit is configured to compare the detection voltage output from the sensor according to the temperature of the power transistor with the threshold voltage, and Wherein, the control circuit is configured to forcibly turn off the power transistor when the abnormality monitoring circuit determines that the temperature of the power transistor is overheated.

8. The driving device according to claim 7, in, The sensor comprises: A constant current source, and a diode through which the constant current output from the constant current source flows, The sensor outputs a forward voltage of the diode as the detection voltage, and the forward voltage of the diode changes according to a temperature of the power transistor.

9. The driving device according to claim 1, wherein: The gate voltage monitoring circuit is configured to directly monitor the gate voltage of the power transistor.

10. The driving device according to claim 1, wherein: The gate voltage monitoring circuit includes a comparator configured to compare a gate voltage of the power transistor with a reference voltage.

11. The driving device according to claim 1, further comprising: an active mirror clamp circuit configured to clamp the gate voltage of the power transistor to a ground level in response to the gate voltage of the power transistor decreasing below an on / off switching boundary value of the power transistor; The active mirror clamp circuit comprises: a switching element provided between the gate of the power transistor and a ground voltage terminal; a comparator configured to compare the gate voltage with a reference voltage lower than the boundary value; and a switch circuit configured to control the switch element to be turned on when the comparator determines that the gate voltage is less than the reference voltage, Here, the comparator provided in the active mirror clamp circuit is also used as the gate voltage monitoring circuit.

12. The driving device according to claim 11, in, The active mirror clamp circuit is configured to keep the switching element turned on when the switching element is controlled to be turned on, until the control circuit starts controlling the power transistor from being turned off to being turned on.

13. The driving device according to claim 11, in, Even if the power transistor is controlled to be turned off by the control circuit, when the gate voltage of the power transistor is equal to or higher than the reference voltage, the comparator outputs a comparison result indicating noise generation in the gate of the power transistor.

14. The driving device according to claim 13, in, The control circuit is configured to be able to switch the level of the reference voltage.

15. The driving device according to claim 14, in, The control circuit is configured to adjust the reference voltage to a maximum value allowed as an increase in the gate voltage caused by the noise when the operation mode is a test mode, and then adjust the on-off switching speed of the power transistor within a range in which the gate voltage indicates a maximum value less than the reference voltage.

16. A power supply system, comprising: The drive device comprises: a sensor configured to detect and output a state of stress applied to the power transistor as a detection voltage; a threshold voltage setting circuit configured to output a threshold voltage; an abnormality monitoring circuit configured to determine whether the state of the stress applied to the power transistor is abnormal by comparing the detection voltage with the threshold voltage; and a control circuit configured to fix the power transistor to be turned on or off according to the type of the stress when the abnormality monitoring circuit determines that the state of the stress is abnormal, Wherein, when the operation mode is the test mode, the control circuit is further configured to test whether the abnormality monitoring circuit determines that the state of the stress is abnormal by switching the level of the threshold voltage set by the threshold voltage setting circuit, so that the abnormality monitoring circuit operating normally determines that the state of the stress is abnormal, The driving device further comprises a gate voltage monitoring circuit, wherein the gate voltage monitoring circuit is configured to monitor the gate voltage of the power transistor. wherein the control circuit is configured to fix the gate voltage of the power transistor to a predetermined voltage according to the type of the stress when the abnormality monitoring circuit determines that the state of the stress is abnormal, and wherein the control circuit is configured to test whether the gate voltage monitoring circuit determines that the gate voltage is fixed to the predetermined voltage when the operation mode is the test mode, and Power transistor.

17. A method for testing a drive device, comprising: switching the level of the threshold voltage set by the threshold voltage setting circuit so as to determine that the state of the stress applied to the power transistor is abnormal in the abnormality monitoring circuit in normal operation, testing whether the abnormality monitoring circuit determines that the state of the stress applied to the power transistor is abnormal by comparing a detection voltage of a sensor for detecting the state of the stress applied to the power transistor with the threshold voltage, monitoring the gate voltage of the power transistor by a gate voltage monitoring circuit, When the abnormality monitoring circuit determines that the state of the stress is abnormal, fixing the gate voltage of the power transistor to a predetermined voltage according to the type of the stress by a control circuit, and When the operation mode is the test mode, whether the gate voltage monitoring circuit determines that the gate voltage is fixed to the predetermined voltage is tested by the control circuit.

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