Alignment pattern, semiconductor structure having alignment pattern and manufacturing method thereof

Abstract

The present invention relates to an alignment pattern, a semiconductor structure having the alignment pattern and a manufacturing method thereof, the manufacturing method comprising: at least two standard pattern areas arranged along a first direction, each standard pattern area comprising at least two discrete sub-pattern areas, along the first direction, the distance between adjacent sub-pattern areas in each standard pattern area is a first distance, the distance between adjacent standard pattern areas is a second distance, and the second distance is greater than the first distance; a shielding pattern, the shielding pattern is located between adjacent standard pattern areas, and there is a gap between the shielding pattern and the adjacent standard pattern areas. The present invention can reduce the area of ​​the empty area in the alignment pattern, avoid defects caused by etching residues, and thus improve the alignment quality.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an alignment pattern, a semiconductor structure with the alignment pattern and a manufacturing method thereof. Background Art

[0002] Alignment is one of the most critical factors in the semiconductor manufacturing process. For example, in photolithography technology, attention should be paid to the alignment between the exposure machine and the mask, and in the chip dicing process, attention should be paid to the alignment between the actual dicing area and the dicing groove.

[0003] Taking the alignment in photolithography as an example, the commonly used alignment methods in photolithography are mainly divided into the following categories: alignment based on bright and dark fields, grating diffraction alignment and video image alignment. In order to achieve alignment, it is necessary to set a corresponding alignment pattern (Alignment mask) on the substrate, chip or mask, and use the alignment pattern to perform alignment.

[0004] When using existing alignment patterns for alignment, there is a problem of low alignment accuracy. Summary of the invention

[0005] The object of the present invention is to provide an alignment pattern, a semiconductor structure having the alignment pattern and a manufacturing method thereof, so as to solve the problem of poor alignment quality.

[0006] In order to solve the above technical problems, an embodiment of the present invention provides an alignment pattern, including: at least two standard pattern areas arranged along a first direction, each standard pattern area includes at least two discrete sub-pattern areas, each sub-pattern area has at least one standard pattern, and along the first direction, the distance between adjacent sub-pattern areas in each of the standard pattern areas is a first distance, the distance between adjacent standard pattern areas is a second distance, and the second distance is greater than the first distance; an occluding pattern, the occluding pattern is located between adjacent standard pattern areas, and there is a gap between the occluding pattern and the adjacent standard pattern areas.

[0007] In addition, the sub-pattern area extends along a second direction, and the second direction is perpendicular to the direction.

[0008] In addition, along the first direction, the distance between the shielding pattern and the adjacent sub-pattern area is a third distance, and the third distance is 285 nm to 315 nm.

[0009] In addition, it also includes: a light shielding pattern, which is located between adjacent sub-pattern areas, and there is a gap between the light shielding pattern and the adjacent sub-pattern areas.

[0010] In addition, the sub-graphic area is in the shape of a strip; the shielding graphic is in the shape of a strip; and the shading graphic is in the shape of a strip.

[0011] The present invention also provides a method for manufacturing a semiconductor structure with an alignment pattern, comprising: providing a substrate, the substrate comprising a plurality of first regions and second regions located between adjacent first regions, a plurality of discrete first functional layers and a sacrificial layer located on the top surface of the first functional layer are formed on the substrate, the first region has at least two first functional layers, the first functional layer of the second region spans the second region, and in a direction from the first region to the second region, the distance between adjacent first functional layers of the first region is less than the width of the first functional layer of the second region;

[0012] A second functional layer is formed on the substrate, wherein the second functional layer also covers the side walls of the sacrificial layer and the side walls of the first functional layer, and the thickness of the second functional layer is different from that of the first functional layer in a direction perpendicular to the surface of the substrate; a mask layer is formed on the surface of the second functional layer, and the mask layer fills the area between adjacent sacrificial layers; after forming the mask layer, the second functional layer located on the side walls of the sacrificial layer and the side walls of the first functional layer is removed; the sacrificial layer is removed by a wet process or an ashing process to expose the top surface of the first functional layer; the mask layer is removed to expose the remaining top surface of the second functional layer, and the first functional layer and the remaining second functional layer constitute an alignment pattern.

[0013] In addition, before forming the mask layer, the second functional layer also covers the top of the sacrificial layer; in the process step of removing the second functional layer located on the sidewalls of the sacrificial layer and the sidewalls of the first functional layer, the second functional layer located on the top of the sacrificial layer is also removed.

[0014] In addition, the material of the mask layer is different from the material of the first functional layer; the material of the mask layer is different from the material of the second functional layer.

[0015] In addition, the material of the sacrificial layer includes photoresist material or amorphous carbon.

[0016] In addition, the sacrificial layer is removed first and then the mask layer is removed; or, the mask layer is removed first and then the sacrificial layer is removed.

[0017] The present invention also provides a semiconductor structure with an alignment pattern, comprising: a substrate, the substrate comprising a plurality of first regions and second regions located between adjacent first regions; a plurality of discrete first functional layers located on the substrate, the first region having at least two first functional layers, the first functional layer of the second region spanning the second region, and in a direction from the first region to the second region, the distance between adjacent first functional layers of the first region is less than the width of the first functional layer of the second region; a plurality of discrete second functional layers located on the substrate in the first region, in a direction from the first region to the second region, the second functional layers are arranged alternately with the first functional layers, and in a direction perpendicular to the surface of the substrate, the thickness of the second functional layers is different from the thickness of the first functional layers, and the first functional layers and the second functional layers constitute the alignment pattern.

[0018] In addition, along the first direction, the width of the second functional layer in the second region is greater than the width of the second functional layer in the first region, and the width of the second functional layer in the second region is greater than the width of the first functional layer in the first region.

[0019] In addition, the material of the first functional layer is the same as that of the second functional layer; or, the material of the first functional layer is different from that of the second functional layer.

[0020] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages:

[0021] The technical solution of the alignment pattern provided by the embodiment of the present invention includes at least two standard pattern areas arranged along the first direction, each standard pattern area includes at least two discrete sub-pattern areas, and along the first direction, the first distance between adjacent sub-pattern areas is less than the second distance between adjacent standard pattern areas, that is, there is a relatively large open area between adjacent standard pattern areas; the shielding pattern is located between adjacent standard pattern areas, and there is a gap between the adjacent standard pattern areas, and the setting of the shielding pattern is conducive to reducing the area of ​​the open area. When manufacturing the alignment pattern, since the area of ​​the open area is reduced, the etching load effect problem caused by the excessively large area of ​​the open area is reduced or even eliminated, thereby avoiding the generation of etching residues, improving the quality of the alignment pattern, and improving the alignment accuracy of the alignment using the alignment pattern.

[0022] The embodiment of the present invention also improves a technical solution of a method for manufacturing a semiconductor structure with an alignment pattern, wherein a discrete first functional layer and a sacrificial layer located on the top surface of the first functional layer are formed in a first region and a second region of a substrate, the first region has at least two first functional layers, the first functional layer of the second region spans the second region, and the width of the first functional layer of the second region is greater than the distance between adjacent first functional layers of the first region; then a second functional layer is formed, and the thickness of the second functional layer is different from the thickness of the first functional layer; then a mask layer is filled between adjacent sacrificial layers; after forming the mask layer, the second functional layer on the sidewall of the sacrificial layer and the sidewall of the first functional layer is removed; the sacrificial layer and the mask layer are removed, and the first functional layer and the remaining second functional layer constitute an alignment pattern. Although the width of the second region is greater than the width of the first functional layer of the first region, since the space position above the second region between the adjacent first regions is occupied by the sacrificial layer instead of the mask layer, the removal rate of the sacrificial layer in the process of removing the sacrificial layer is little affected by the size of the sacrificial layer area, thereby reducing or even eliminating the etching load effect, ensuring that the sacrificial layer of the second region is completely removed, avoiding the generation of defects, thereby improving the quality of the formed alignment pattern and improving the process production yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0024] Figures 1 to 4 It is a structural schematic diagram corresponding to each step of a method for forming a semiconductor structure with an alignment pattern;

[0025] Figure 5 A schematic diagram of an alignment pattern provided by an embodiment of the present invention;

[0026] Figures 6 to 14 A schematic structural diagram corresponding to each step of the method for manufacturing a semiconductor structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] As can be seen from the background art, the accuracy of alignment using existing alignment patterns needs to be improved.

[0028] Figures 1 to 4 The present invention is a schematic structural diagram corresponding to each step of a method for forming a semiconductor structure with an alignment pattern.

[0029] refer to Figure 1A substrate including a first region i and a second region ii located between adjacent first regions i is provided, wherein the substrate includes a substrate 10 and a polysilicon layer 20 located on the surface of the substrate 10, a discrete first dielectric layer 21 is formed on the surface of the substrate in the first region i, and a photoresist layer 22 is provided on the top surface of the first dielectric layer 21; a second dielectric layer 23 is also formed on the surface of the substrate, and the second dielectric layer 23 also covers the top and sidewalls of the photoresist layer 22, and the thickness of the second dielectric layer 23 is less than the thickness of the first dielectric layer 21; a mask layer 24 is located on the surface of the second dielectric layer 23, and the mask layer 24 of the second region ii spans the second region ii.

[0030] The surface area of ​​the mask layer 24 in the second region ii is greater than the surface area of ​​the mask layer 24 in the first region i.

[0031] refer to Figure 2 , the second dielectric layer 23 located on the top and sidewalls of the photoresist layer 22 is removed to expose the surface of the substrate 20 .

[0032] refer to Figure 3 , remove the photoresist layer 22 (refer to Figure 2 ).

[0033] refer to Figure 4 , using a dry etching process, etching and removing the mask layer 24 (reference Figure 3 ), the first dielectric layer 21 and the remaining second dielectric layer 23 constitute an alignment pattern.

[0034] The surface area of ​​the mask layer 24 in the second region ii is larger than the surface area of ​​the mask layer 24 in the first region i. It can be considered that the surface size of the mask layer 24 to be etched in the second region ii is large. Therefore, there is a large etching loading effect in the etching of the mask layer 24 in the second region ii. The etching rate of the middle region of the mask layer 24 in the second region ii is lower than the etching rate of the edge region. As a result, after the mask layer 24 in the first region i is etched away, part of the mask layer 24 material remains in the middle region of the second region ii to form etching residues 25, resulting in defects in the alignment pattern.

[0035] Further analysis revealed that although the surface area of ​​the mask layer 24 in the first region i is smaller than the surface area of ​​the mask layer 24 in the second region ii, the etching of the surface of the mask layer 24 in the first region i will also have a certain etching load effect, resulting in some mask layer 24 material remaining in the middle area of ​​the first region i to form etching residues (not shown).

[0036] During the alignment process using the alignment pattern, the presence of the etching residues 25 in the first region i and the second region ii affects the alignment process, resulting in poor alignment accuracy.

[0037] To solve the above problems, an embodiment of the present invention provides an alignment pattern, in which a shielding pattern is set in the open area between adjacent standard pattern areas. The setting of the shielding pattern reduces the area of ​​the open area, thereby avoiding the etching residue problem caused by the etching load effect, reducing the generation of defects in the alignment pattern, improving the alignment quality, and increasing the semiconductor production yield.

[0038] In order to make the purpose, technical scheme and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are provided to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented.

[0039] It is understood that the terms "first", "second", etc. used in the present invention may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of the present invention, a first functional layer may be referred to as a second functional layer, and a second functional layer may be referred to as a first functional layer.

[0040] Figure 5 A schematic diagram of an alignment pattern provided in accordance with an embodiment of the present invention.

[0041] refer to Figure 5 The alignment pattern provided in this embodiment includes: at least two standard pattern areas 100 arranged along a first direction Y, each standard pattern area 100 includes at least two discrete sub-pattern areas 101, along the first direction Y, the distance between adjacent sub-pattern areas 101 in each standard pattern area 101 is a first distance L1, the distance between adjacent standard pattern areas 100 is a second distance L2, and the second distance L2 is greater than the first distance L1; a shielding pattern 102, the shielding pattern 102 is located between adjacent standard pattern areas 100, and there is a gap 103 between the shielding pattern 102 and the adjacent standard pattern area 100.

[0042] The alignment pattern provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0043] The graphics of the standard graphics area 100 can be used for alignment. Specifically, the standard graphics area 100 includes at least two separate sub-graphic areas 101, and each sub-graphic area 101 has at least one sub-graphic (not shown), which is used for the first alignment. It should be noted that the shape and number of the sub-graphics in the sub-graphic area 101 can be set according to the actual alignment requirements. For example, the sub-graphics can be strip graphics extending perpendicular to the first direction Y, or can be strip graphics extending in a direction that forms an inclined angle with the first direction Y.

[0044] In this embodiment, the sub-pattern area 101 is in a strip shape, and the sub-pattern area 101 extends along a second direction X, and the second direction X is perpendicular to the first direction Y.

[0045] In the first direction Y, the distance between adjacent sub-pattern areas 101 in the same standard pattern area 100 is a first distance L1, and the distance between adjacent standard pattern areas 100 is a second distance L2, which is greater than the first distance L1. In other words, there is a large empty area between adjacent standard pattern areas 100.

[0046] To this end, the setting of the shielding pattern 102 located between adjacent standard pattern areas 100 is conducive to reducing the area of ​​the empty area between adjacent standard pattern areas 100. The shielding pattern 102 can also be used for alignment, thereby facilitating improving the alignment accuracy. In this embodiment, the shielding pattern 102 is also in the shape of a strip, and the shielding pattern 102 extends along the second direction X.

[0047] In order to further improve the alignment accuracy when using the alignment pattern for alignment, in this embodiment, the distance between the occluding pattern 102 and the sub-pattern area 101 on one side is equal to the distance between the occluding pattern 102 and the sub-pattern area 101 on the other side, that is, the occluding pattern 102 is located in the middle of the adjacent standard pattern area 100.

[0048] In the first direction Y, the distance between the shielding pattern 102 and the adjacent sub-pattern area 101 is a third distance L3, which is the width of the gap 103. In this embodiment, the third distance is 285nm to 315nm, for example, 290nm, 300nm, and 310nm. Such a setting is conducive to ensuring high alignment accuracy when using the alignment pattern for alignment without increasing the difficulty of manufacturing the alignment pattern.

[0049] In this embodiment, in order to further improve the alignment accuracy, the alignment pattern further includes: a shading pattern 104, which is located between adjacent sub-pattern areas 101, and there is a gap between the shading pattern 104 and the adjacent sub-pattern area 104. When aligning, the shading pattern 104 can also be used for alignment to further improve the alignment accuracy.

[0050] The light shielding pattern 104 is in a strip shape, and the light shielding pattern 104 extends along the second direction X.

[0051] The alignment pattern provided in this embodiment has a shielding pattern 102 disposed between adjacent standard pattern areas 100. After or before alignment using the pattern of the standard pattern area 100, alignment can also be performed using the shielding pattern 102, which is beneficial to improving alignment accuracy.

[0052] Accordingly, an embodiment of the present invention also provides a method for manufacturing a semiconductor structure having the above alignment pattern, which improves the quality of the formed alignment pattern, thereby improving the alignment accuracy. The method for manufacturing a semiconductor structure having an alignment pattern provided by an embodiment of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0053] Figures 6 to 14 A schematic structural diagram corresponding to each step of the method for manufacturing a semiconductor structure provided by an embodiment of the present invention.

[0054] refer to Figures 6 to 8 , providing a substrate 200, the substrate 200 includes a plurality of first regions I and second regions II located between adjacent first regions I, and a plurality of discrete first functional layers 203 and a sacrificial layer 204 located on the top surface of the first functional layer 203 are formed on the substrate 200.

[0055] Figures 6 to 8 It is a schematic diagram of the cross-sectional structure. Unless otherwise specified, the schematic diagrams provided subsequently are all schematic diagrams of the cross-sectional structure.

[0056] The first region I has at least two first functional layers 203, and the first functional layer 203 of the second region II spans the second region II, that is, in the direction from the first region I to the second region II, the width of the second region II is the same as the width of the first functional layer 203 of the second region II; and in the direction from the first region I to the second region II, the distance between adjacent first functional layers 203 of the first region I is smaller than the width of the first functional layer 203 of the second region II.

[0057] The formed semiconductor structure can be located in the wafer scribe groove (also called cutting road), and the semiconductor structure can be used to align the scribe area; the formed semiconductor structure can also be located in other positions in the wafer with alignment requirements; or the formed semiconductor structure can also be located in a mask with alignment requirements, and used for alignment between the mask and the exposure machine. According to the application of different alignment requirements of the semiconductor structure, the number of substrate layers and the corresponding materials can be reasonably set.

[0058] The base 200 includes a substrate 201 and a cover layer 202 located on the surface of the substrate 201 as an example. The substrate 201 can be a semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a III-V substrate or a sapphire substrate. The cover layer 202 can be a single-layer structure or a stacked-layer structure; the material of the cover layer 202 can be one or more of polysilicon, silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbide, titanium nitride, tantalum nitride, titanium or tantalum, etc.

[0059] In this embodiment, the substrate 201 is a silicon substrate, and the material of the cover layer 202 is polysilicon.

[0060] The first functional layer 203 is a part of the alignment pattern and is located on a surface of a portion of the substrate 200. In order to ensure a large etching selectivity between the cover layer 202 and the first functional layer 203 and avoid process damage to the cover layer 202 during the process of forming the first functional layer 203, the material of the cover layer 202 is different from that of the first functional layer 203.

[0061] The material of the first functional layer 203 may be a dielectric material, a metal material or a metal compound material. The dielectric material may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride or silicon carbonitride oxynitride, etc., the metal material may be titanium, tantalum or nickel, etc., and the metal compound material may be titanium nitride, tantalum nitride or nickel oxide, etc.

[0062] In this embodiment, the material of the first functional layer 203 is silicon oxide.

[0063] The width of the first functional layer 203 in the second region II is greater than the width of the first functional layer 203 in the first region I, and the width of the first functional layer 203 in the second region II is also greater than the distance between adjacent first functional layers 203 in the first region I, so as to meet the morphology requirements of the alignment pattern formed subsequently. The specific size ranges of the first region I and the second region II can be reasonably set according to actual process requirements, for example, the width of the first functional layer 203 in the first region I can also be greater than the width of the second functional layer 203 in the second region II.

[0064] The sacrificial layer 204 is used to protect the first functional layer 203 in subsequent process steps; in addition, the sacrificial layer 204 located in the second region II occupies a certain spatial position, so that a mask layer will not be formed in the second region II in the subsequent process steps of forming a mask layer, thereby avoiding the problem of etching residues in the second region II caused by removing the mask layer in the second region II.

[0065] It should be noted that the material of the sacrificial layer 204 can be removed by a wet process or an ashing process, thereby avoiding the etching load effect problem caused by the dry etching process and ensuring that the sacrificial layer 204 in the second region II can be completely removed in the subsequent process step of removing the sacrificial layer 204.

[0066] The material of the sacrificial layer 204 includes a photoresist material or amorphous carbon. In this embodiment, the material of the sacrificial layer 204 is a photoresist material, which is conducive to simplifying the process steps.

[0067] The following will be combined Figures 6 to 8 The specific process steps for forming the first functional layer 203 and the sacrificial layer 204 are described in detail.

[0068] refer to Figure 6 , providing a substrate 200 including a first region I and a second region II; forming a first functional film 213 on the surface of the substrate 200 .

[0069] The first functional film 213 provides a process basis for subsequently forming the first functional layer. It can be considered that the material of the first functional film 213 is the same as that of the first functional layer 203 , and the thickness of the first functional film 213 is the same as that of the first functional layer 203 .

[0070] The first functional film 213 may be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0071] refer to Figure 7 A sacrificial layer 204 is formed on a portion of the surface of the first functional film 213 .

[0072] The sacrificial layer 204 is used to define the position and shape of the first functional layer. In this embodiment, taking the sacrificial layer 204 as a photoresist as an example, the process steps of forming the sacrificial layer 204 include: forming a sacrificial film on the surface of the first functional film 213; exposing and developing the sacrificial film to form a patterned sacrificial layer 204.

[0073] In other embodiments, when the material of the sacrificial layer is amorphous carbon, the process steps for forming the sacrificial layer include: forming a sacrificial film on the surface of the first functional film; forming a patterned photoresist layer on the surface of the sacrificial film; using the patterned photoresist layer as a mask, etching the sacrificial film until a portion of the surface of the first functional film is exposed to form a patterned sacrificial layer; and removing the patterned photoresist layer.

[0074] refer to Figure 8 , the first functional film 213 exposed by etching the sacrificial layer 204 (refer to Figure 7 ) until the surface of the substrate 200 is exposed, thereby forming a first functional layer 203.

[0075] The first functional film 213 may be etched by using a dry etching process.

[0076] refer to Fig. 9 A second functional layer 205 is formed on the substrate 200 , and the second functional layer 205 also covers the side wall surface of the sacrificial layer 204 and the side wall surface of the first functional layer 203 , and in a direction perpendicular to the surface of the substrate 200 , the thickness of the second functional layer 205 is different from the thickness of the first functional layer 203 .

[0077] Specifically, the second functional layer 205 is located on the surface of the substrate 200 , and the second functional layer 205 conformally covers the sacrificial layer 204 , that is, the second functional layer 205 also covers the top surface of the sacrificial layer 204 .

[0078] Part of the second functional layer 205 will subsequently constitute a part of the alignment pattern. In order to facilitate the distinction between the first functional layer 203 and the second functional layer 205 in the alignment pattern, the thickness of the second functional layer 205 is different from that of the first functional layer 203 in a direction perpendicular to the surface of the substrate 200. It should be noted that the thickness of the second functional layer 205 here refers to the thickness of the second functional layer 204 located on the surface of the substrate 200 other than the sidewalls of the sacrificial layer 204 and the sidewalls of the first functional layer 203.

[0079] In this embodiment, the thickness of the second functional layer 205 is less than the thickness of the first functional layer 203. In other embodiments, the thickness of the second functional layer may be greater than the thickness of the first functional layer.

[0080] The material of the second functional layer 205 is different from that of the substrate 200. More specifically, the material of the second functional layer 205 is different from that of the covering layer 202, which helps to ensure that the covering layer 202 is less damaged in the subsequent process step of removing part of the second functional layer 205. The material of the second functional layer 205 can be the same as or different from that of the first functional layer 203.

[0081] The material of the second functional layer 205 may be a dielectric material, a metal material or a metal compound material. The dielectric material may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride or silicon carbonitride oxynitride, etc. The metal material may be titanium, tantalum or nickel, etc. The metal compound material may be titanium nitride, tantalum nitride or nickel oxide, etc.

[0082] In this embodiment, taking the material of the second functional layer 205 being the same as the material of the first functional layer 203 as an example, the material of the second functional layer 205 is silicon oxide.

[0083] In this embodiment, an atomic layer deposition process is used to form the second functional layer 205. In other embodiments, a chemical vapor deposition process or a physical vapor deposition process may also be used to form the second functional layer.

[0084] refer to Fig.10 A mask layer 207 is formed on the surface of the second functional layer 205 , and the mask layer 207 fills the area between adjacent sacrificial layers 204 .

[0085] In the subsequent process step of removing the second functional layer 205 located on the side wall surface of the sacrificial layer 204, the mask layer 207 provides protection for the second functional layer 205 located on the surface of the substrate 200, preventing the second functional layer 205 located on the surface of the substrate 200 from being removed, thereby ensuring that the second functional layer 205 located on the surface of the substrate 200 can serve as part of the alignment pattern.

[0086] To ensure that the subsequent process of removing the second functional layer 205 on the sidewall surface of the sacrificial layer 204 proceeds smoothly, in this embodiment, the mask layer 207 exposes the top surface of the second functional layer 205 on the sidewall surface of the sacrificial layer 204 .

[0087] The material of the mask layer 207 is different from that of the second functional layer 205 , and the material of the mask layer 207 is different from that of the first functional layer 203 , thereby preventing the subsequent process step of removing the mask layer 207 from causing process damage to the first functional layer 203 or the second functional layer 205 .

[0088] In this embodiment, the material of the mask layer 207 is silicon nitride. In other embodiments, the material of the mask layer may also be silicon oxide, silicon oxynitride or silicon oxycarbonitride. It should be noted that in other embodiments, the material of the mask layer may also be the same as the material of the sacrificial layer, that is, the material of the mask layer may be a photoresist material or amorphous carbon.

[0089] The process steps for forming the mask layer 207 may include: forming an initial mask on the surface of the second functional layer 205, wherein the initial mask fills the area between adjacent sacrificial layers 204, and the top surface of the initial mask is higher than the surface of the second functional layer 205 located on the top of the sacrificial layer 204; planarizing the initial mask, removing the initial mask that is higher than the surface of the second functional layer 205 located on the top of the sacrificial layer 204, and forming a mask layer 207.

[0090] refer to Fig.11 After forming the mask layer 207 , the second functional layer 205 located on the sidewalls of the sacrificial layer 204 and the sidewalls of the first functional layer 203 is removed to expose a portion of the surface of the substrate 200 .

[0091] Specifically, an anisotropic etching process is used to etch and remove the second functional layer 205 located on the sidewalls of the sacrificial layer 204 and the sidewalls of the first functional layer 203. The anisotropic etching process is used to ensure that only the etching is in the vertical direction, that is, the direction perpendicular to the surface of the substrate 200, so as to avoid mis-etching of the first functional layer 203. It should be noted that in other embodiments, when the isotropic etching process has a large etching selectivity ratio between the materials of the first functional layer and the second functional layer, the isotropic etching process can also be used to etch and remove the second functional layer located on the sidewalls of the sacrificial layer and the sidewalls of the first functional layer.

[0092] In the process step of etching the second functional layer 205 on the sidewalls of the sacrificial layer 204 and the first functional layer 203 , the sacrificial layer 204 protects the first functional layer 203 thereunder, and the mask layer 207 protects the second functional layer 205 thereunder.

[0093] In this embodiment, since the second functional layer 205 is formed on the top of the sacrificial layer 204, in the process step of removing the second functional layer 205 located on the sidewalls of the sacrificial layer 204 and the sidewalls of the first functional layer 203, the second functional layer 205 located on the top of the sacrificial layer 204 is also removed.

[0094] refer to Fig.12 , remove the sacrificial layer 204 (refer to Fig.11 ), exposing the top surface of the first functional layer 203.

[0095] In the process step of removing the sacrificial layer 204 , the removal rate of the sacrificial layer 204 surface is little affected by the surface area of ​​the sacrificial layer 204 , so that the time for completely etching and removing the sacrificial layer 204 on the substrate 200 can be kept consistent.

[0096] The sacrificial layer 204 is removed by wet process or ashing process, and the gas used for ashing includes O2 and may also include SF6. Specifically, in this embodiment, the material of the sacrificial layer 204 is a photoresist material, and the sacrificial layer 204 can be removed by wet stripping or ashing process.

[0097] In other embodiments, when the material of the sacrificial layer is amorphous carbon, the sacrificial layer can be removed by wet etching or ashing process.

[0098] Although the sacrificial layer 204 in the second region II is relatively wide, the sacrificial layer 204 can be removed by a wet process or an ashing process. Therefore, the influence of the etching load effect in the process step of removing the sacrificial layer 204 can be ignored or even does not exist, thereby ensuring that the sacrificial layer 204 in the second region II can be completely removed, and thus no residue exists on the top surface of the first functional layer 203 in the second region II.

[0099] refer to Fig.13 and Fig.14 , Fig.13 This is a top view of the structure. Fig.14 for Fig.13 The schematic diagram of the cross-sectional structure cut along the AA1 direction, removing the mask layer 207 (reference Fig.12 ), exposing the top surface of the remaining second functional layer 205, the first functional layer 203 and the remaining second functional layer 205 constitute an alignment pattern.

[0100] The mask layer 207 is removed by etching using a dry etching process.

[0101] Compared with the solution in the prior art in which the mask layer is still located in the second area, in this embodiment, since the surface dimensions of the mask layer 207 at various locations on the substrate 200 are not very different, the etching load problem can be effectively avoided, ensuring that the mask layer 207 at various locations on the substrate 200 can be completely etched and removed.

[0102] In the direction from the first region I to the second region II, the second functional layer 205 and the first functional layer 203 are arranged at intervals, and the thickness of the first functional layer 203 is different from that of the second functional layer 205. The first functional layer 203 and the remaining second functional layer 205 form an uneven alignment structure on the substrate 200, and the alignment structure has an alignment pattern for alignment.

[0103] In this embodiment, the sacrificial layer 204 is first removed (refer to Fig.11) and then remove the mask layer 207, which is beneficial to avoid exposing the surface of the substrate 200 to the process environment of removing the sacrificial layer 204, and prevent the surface of the substrate 200 from being damaged by the process. It should be noted that in other embodiments, the mask layer may be removed first and then the sacrificial layer; or, when the material of the sacrificial layer is the same as that of the mask layer, the sacrificial layer and the mask layer may be removed at the same time.

[0104] The area where the first functional layer 203 and the second functional layer 205 are located in the first area I serves as a part of the standard pattern area in the alignment pattern, and the first functional layer 203 in the second area II serves as a shielding pattern between adjacent standard pattern areas in the alignment pattern.

[0105] Since the sacrificial layer 204 occupies the spatial position above the second region II with a larger area, it replaces the solution in the prior art in which the mask layer occupies the spatial position, thereby avoiding the etching residue problem caused by etching away the mask layer in the second region, ensuring that the sacrificial layer 205 in the second region II is completely etched away, reducing the generation of defects in the alignment pattern, thereby improving the alignment pattern morphology and improving the alignment accuracy of the alignment using the alignment pattern.

[0106] In addition, using the alignment pattern in the semiconductor structure manufactured by this embodiment for alignment is conducive to increasing the alignment pass rate and improving the efficiency of goods passing, thereby reducing the number of alignment cycles. At the same time, it reduces the probability of the situation where alignment cannot be achieved due to defects in the alignment pattern, reducing the load on engineers.

[0107] Correspondingly, the embodiment of the present invention further provides a semiconductor structure with an alignment pattern manufactured by the above manufacturing method. The semiconductor structure provided by the embodiment of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0108] refer to Fig.13 and Fig.14The semiconductor structure with an alignment pattern provided in this embodiment includes: a substrate 200, the substrate 200 includes a plurality of first regions I and a second region II located between adjacent first regions I; a plurality of discrete first functional layers 203 located on the substrate 200, the first region I has at least two first functional layers 203, the first functional layer 203 of the second region II spans the second region II, and in a direction from the first region I to the second region II, the distance between adjacent first functional layers 203 of the first region I is smaller than the width of the first functional layer 203 of the second region II; a plurality of discrete second functional layers 205 located on the substrate 200 in the first region I, in a direction from the first region I to the second region II, the second functional layers 205 are arranged alternately with the first functional layers 203, and in a direction perpendicular to the surface of the substrate 200, the thickness of the second functional layer 205 is different from the thickness of the first functional layer 203, and the first functional layer 203 and the second functional layer 205 constitute an alignment pattern.

[0109] The semiconductor structure provided by this embodiment will be described in detail below with reference to the accompanying drawings.

[0110] The base 200 includes a substrate 201 and a cover layer 202 located on the surface of the substrate 201. The detailed description of the base 200 can refer to the corresponding description of the above embodiment, which will not be repeated here.

[0111] In the direction from the first region I to the second region I, the width of the first functional layer 203 in the second region II is equal to the width of the second region II; and the width of the first functional layer 203 in the second region II is greater than the width between adjacent first functional layers 203 in the first region I, and the width of the first functional layer 203 in the second region II is also greater than the width of the first functional layer 203 in the first region I.

[0112] The material of the first functional layer 203 may be the same as or different from the material of the second functional layer 205. In this embodiment, the material of the first functional layer 203 is silicon oxide, and the material of the second functional layer 205 is silicon oxide. In other embodiments, the materials of the first functional layer and the second functional layer may also refer to the specific description of the above embodiments, which will not be repeated here.

[0113] The first functional layer 203 and the second functional layer 205 are arranged alternately on the substrate 200, and the thickness of the first functional layer 203 is different from the thickness of the second functional layer 205, so as to form a top surface concave-convex alignment pattern on the substrate 200. In this embodiment, the thickness of the second functional layer 205 is less than the thickness of the first functional layer 203. In other embodiments, the thickness of the second functional layer may also be greater than the thickness of the first functional layer.

[0114] When the semiconductor structure provided by this embodiment is used for alignment, since the alignment pattern has high quality, it is helpful to improve the alignment accuracy.

[0115] Those skilled in the art will appreciate that the above embodiments are specific examples of the present invention, and in practical applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention, and therefore the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure having an alignment pattern, characterized in that: include: Providing a substrate, the substrate comprising a plurality of first regions and a second region located between adjacent first regions, a plurality of discrete first functional layers and a sacrificial layer located on the top surface of the first functional layer are formed on the substrate, the first region has at least two first functional layers, the first functional layer of the second region spans the second region, and in a direction from the first region to the second region, the distance between adjacent first functional layers of the first region is smaller than the width of the first functional layer of the second region; forming a second functional layer on the substrate, wherein the second functional layer also covers the sidewalls of the sacrificial layer and the sidewalls of the first functional layer, and the thickness of the second functional layer is different from that of the first functional layer in a direction perpendicular to the surface of the substrate; forming a mask layer on the surface of the second functional layer, wherein the mask layer fills the area between adjacent sacrificial layers; After forming the mask layer, removing the second functional layer located on the sidewalls of the sacrificial layer and the sidewalls of the first functional layer; removing the sacrificial layer to expose the top surface of the first functional layer; The mask layer is removed to expose the remaining top surface of the second functional layer, and the first functional layer and the remaining second functional layer constitute an alignment pattern.

2. The manufacturing method according to claim 1, characterized in that Before forming the mask layer, the second functional layer also covers the top of the sacrificial layer; in the process step of removing the second functional layer located on the sidewalls of the sacrificial layer and the sidewalls of the first functional layer, the second functional layer located on the top of the sacrificial layer is also removed.

3. The manufacturing method according to claim 1 or 2, characterized in that: The material of the mask layer is different from the material of the first functional layer; the material of the mask layer is different from the material of the second functional layer.

4. The manufacturing method according to claim 3, characterized in that: The sacrificial layer is removed by a wet process or an ashing process.

5. The manufacturing method according to claim 4, characterized in that: The material of the sacrificial layer includes photoresist material or amorphous carbon.

6. The manufacturing method according to claim 1 or 2, characterized in that: The sacrificial layer is removed first, and then the mask layer is removed; or, the mask layer is removed first, and then the sacrificial layer is removed.

7. A semiconductor structure having an alignment pattern, characterized in that: include: A substrate, the substrate comprising a plurality of first regions and second regions located between adjacent first regions, the substrate comprising a substrate and a covering layer located on a surface of the substrate; A plurality of discrete first functional layers are disposed on the substrate, the material of the cover layer is different from that of the first functional layers, the first region has at least two first functional layers, the first functional layers of the second region span the second region, and in a direction from the first region to the second region, the distance between adjacent first functional layers of the first region is less than the width of the first functional layers of the second region; A plurality of discrete second functional layers are located on the substrate of the first region, wherein the second functional layers are arranged alternately with the first functional layers in a direction pointing from the first region to the second region, and the thickness of the second functional layers is different from the thickness of the first functional layers in a direction perpendicular to the surface of the substrate, and the first functional layers and the second functional layers constitute the alignment pattern.

8. The semiconductor structure according to claim 7, wherein: In a direction from the first region to the second region, the width of the second functional layer in the second region is greater than that of the second functional layer in the first region, and the width of the second functional layer in the second region is greater than that of the first functional layer in the first region.

9. The semiconductor structure according to claim 7, wherein: The material of the first functional layer is the same as that of the second functional layer; or, the material of the first functional layer is different from that of the second functional layer.

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