eMMC chip testing system and power-on and power-off testing method

Abstract

The present application provides an eMMC chip test system and a power-on and power-off test method, which are applied to the technical field of storage chip security test. The eMMC test system is composed of an XU4 platform and an eMMC chip test platform. The XU4 platform includes a data transmission circuit, a storage device, an XU4 main control chip, a first signal transmission interface, a power module and a first power interface. The XU4 main control chip is connected to the first signal transmission interface, and the power module is connected to the first power interface; the eMMC chip test platform includes a second power interface, a second signal transmission interface, a voltage conversion module and a test chip circuit. The second power interface is connected to the voltage conversion module. The voltage conversion module has a first output end and a second output end, both of which are connected to the test chip circuit, and the second signal transmission interface is connected to the test chip circuit. The power state of the eMMC chip when it is accidentally or intentionally powered on or off at any time can be simulated to achieve the test of the impact of all power-on and power-off conditions of the eMMC on data transmission.

Description

Technical Field

[0001] The present application relates to the technical field of storage chip security testing, and in particular to an eMMC chip testing system and a power-on and power-off testing method. Background Art

[0002] eMMC (Embedded Multi Media Card) is a standard specification for embedded memory established by the MMC Association, mainly for products such as mobile phones and tablets. It is currently the most popular storage chip for mobile devices.

[0003] The existing tests for eMMC generally include read, write, erase and other related tests, but the power-on and power-off tests for eMMC are still a vacant area in the industry. In mobile devices and other products, the power of the eMMC is often cut off at any time due to user restarting the device or the device running out of power. The power of the eMMC can be restored at any time, so the power-on and power-off tests of the eMMC are extremely important. Summary of the invention

[0004] The present application provides an eMMC chip testing system and a power-on / off testing method, which simulate the power state of the eMMC chip when it is accidentally or intentionally powered on or off at any time, so as to test the impact of all power-on and power-off conditions of the eMMC on data transmission, thereby ensuring the good manufacturing rate of the eMMC chip.

[0005] This application adopts the following technical means to solve the technical problem:

[0006] The present application proposes an eMMC chip test system, which is composed of an XU4 platform and an eMMC chip test platform. The eMMC test system performs a power-on and power-off test on the eMMC chip, wherein:

[0007] The XU4 platform includes a data transmission circuit, a storage device, an XU4 main control chip, a first signal transmission interface, a power module and a first power interface, wherein the data transmission circuit and the power module are both connected to the storage device, the data transmission circuit is also connected to the XU4 main control chip, the storage device is connected to the XU4 main control chip, the XU4 main control chip is connected to the first signal transmission interface, and the power module is connected to the first power interface;

[0008] The eMMC chip test platform includes a second power supply interface, a second signal transmission interface, a voltage conversion module and a test chip circuit, the second power supply interface is connected to the voltage conversion module, the voltage conversion module has a first output end and a second output end, both of which are connected to the test chip circuit, and the second signal transmission interface is connected to the test chip circuit;

[0009] The data transmission circuit is connected to an external PC device, the first power interface is connected to the second power interface, and the first signal transmission interface is connected to the second signal transmission interface.

[0010] Furthermore, the XU4 platform also includes a burning circuit, and the burning circuit is connected to the XU4 main control chip.

[0011] Furthermore, the eMMC chip testing platform also includes an external power interface, and the external power interface is connected to the second power interface.

[0012] Furthermore, the eMMC test platform also includes a 3.3V external interface and a 1.8V external interface, the 3.3V external interface and the first output end of the voltage conversion module are connected to the line of the test chip circuit, and the 1.8V external interface and the second output end interface of the voltage conversion module are connected to the line of the test chip circuit.

[0013] Furthermore, the eMMC test platform also includes a signal external interface, and the signal external interface is connected to the line between the second signal transmission interface and the test chip circuit.

[0014] Further, the voltage conversion module includes a first voltage output circuit and a second voltage output circuit, the first voltage output circuit is connected to the first output terminal of the voltage conversion module, and the second voltage output circuit is connected to the second output terminal;

[0015] The first voltage output circuit is provided with a 3.3V GPIO unit, and the second voltage output circuit is provided with a 1.8V GPIO unit.

[0016] Further, the eMMC test system performs a power-on and power-off test method, the method comprising:

[0017] S1, the data transmission circuit receives the test start instruction and test data input by the PC device, and sends the test start instruction and test data to the XU4 main control chip, and the XU4 main control chip stores the test data in the storage device;

[0018] S2, according to the test start instruction, the power module outputs 5V power to the first power interface, the first power interface outputs 5V power to the voltage conversion module through the second power interface, the voltage conversion module converts the 5V power to generate 3.3V power and 1.8V power, and outputs the 3.3V power and 1.8V power to the test chip circuit through the first output terminal and the second output terminal respectively, so as to supply power to the eMMC chip in the test chip circuit;

[0019] S3, the XU4 main control chip retrieves the test data from the storage device and outputs it to the second signal transmission interface through the first signal transmission interface, the second signal transmission interface outputs the test data to the test chip circuit, the eMMC chip in the test chip circuit performs a test related to the test data and then outputs feedback data, the feedback data is fed back to the XU4 main control chip through the second signal transmission interface and the first signal transmission interface;

[0020] S4, the XU4 main control chip uses a preset power-on and power-off rule to power on and off the test chip circuit;

[0021] S5, judging whether the feedback data fed back to the XU4 main control chip and the test data conform to the preset reading and writing rules, and forming a test result;

[0022] S6, the XU4 main control chip outputs the test result to the PC device through the data transmission circuit.

[0023] Further, in S4 of the power on and off test method, the preset power on and off rule is:

[0024] Mode 1: The power-off sequence is that during the process of the first signal transmission interface outputting the test data transmission, the 1.8V power-off is followed by the 3.3V power-off, and then the 1.8V power-on is followed by the 3.3V power-on;

[0025] Mode 2: The power-off sequence is that during the process of the first signal transmission interface outputting the test data transmission, the 3.3V is powered off at a random time, followed by the 1.8V being powered off, and then the 3.3V being powered on after the 1.8V being powered on;

[0026] Mode 3: The power-off sequence is that during the process of the first signal transmission interface outputting the test data transmission, the 1.8V power-off sequence is followed by the 3.3V power-off sequence, and then the 3.3V power-on sequence is followed by the 1.8V power-on sequence;

[0027] Mode 4: The power-off sequence is that 1.8V is powered off and then 3.3V is powered off at a random time during the process of the first signal transmission interface outputting the test data transmission, and then 1.8V is powered on and then 3.3V is powered on.

[0028] Further, in S5 of the power on / off test method, the preset read / write rule is:

[0029] The XU4 writes the data values ​​carried in the test data into each unit of the eMMC chip in the positive or reverse order of the eMMC chip address;

[0030] Read the data value carried by the feedback data in the positive or reverse order of the eMMC chip address;

[0031] Determine whether the data values ​​read and written are consistent.

[0032] Further, the steps before S1 in the power-on and power-off test method are performed according to the above-mentioned eMMC chip test system, and the steps include:

[0033] The PC device burns the functional application of the XU4 main control chip;

[0034] The formed burning data is stored in the storage device, and then the power is turned off;

[0035] After restarting, the test command and test data of the PC device are received again, and the burning data is retrieved from the storage device for autonomous testing, and the power-on and power-off testing method is executed.

[0036] The present application provides an eMMC chip testing system and a power-on / off testing method, which have the following beneficial effects:

[0037] (1) The unique power-on and power-off test method of the present invention can be combined with the test platform included in the present invention to perform four power-on and power-off tests, which can simulate the power state of the eMMC chip when it is accidentally or intentionally powered on or off at any time, thereby achieving the test of the impact of all power-on and power-off conditions of the eMMC on data transmission.

[0038] (2) The test platform of the present invention can be used for testing multiple test controllers. Not only can the test platform of the present invention be used for testing, but different control platforms can also be tested through an extended signal interface, thereby improving the scalability of the test platform.

[0039] (3) The test platform of the present invention increases the compatibility of the test platform with different main control platforms through the design of multiple power supply access methods;

[0040] (4) The test platform of the present invention is compatible with different main control platforms and can perform tests on multiple main control platforms on one test platform to avoid the problem that the chip is only compatible with a single main control platform;

[0041] (5) The present invention adopts a connection socket that can be directly connected to the XU4 platform, avoiding the use of external wiring to transmit signals when using XU4 testing, thereby improving signal quality;

[0042] (6) The signal transmission external interface and power supply external interface of the present invention can be used to accurately measure the signal using an oscilloscope when using the signal transmission circuit.

[0043] (7) Read-write test and power-on / off test can be performed simultaneously, greatly shortening the test process. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic block diagram of a test system of an embodiment of an eMMC chip test system and a power-on / off test method of the present application;

[0045] Figure 2 A circuit diagram of a voltage conversion circuit of an embodiment of an eMMC chip testing system and a power-on / off testing method of the present application;

[0046] Figure 3 This is a flow chart of a test method in one embodiment of an eMMC chip test system and a power-on / off test method of the present application.

[0047] The implementation, functional features and advantages of the present application will be further described in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0048] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0049] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0050] It should be noted that the terms "include", "comprises" and "have" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices. In the claims, specification and drawings of the present application, relational terms such as "first" and "second" are merely used to distinguish one entity / operation / object from another entity / operation / object, and do not necessarily require or imply any such actual relationship or order between these entities / operations / objects.

[0051] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0052] Reference Figure 1 , is a structural block diagram of an eMMC chip testing system in an embodiment of the present application;

[0053] An eMMC chip test system, which is composed of an XU4 platform 101 and an eMMC chip test platform, performs a power-on and power-off test on the eMMC chip.

[0054] The XU4 platform 101 includes a data transmission circuit 109, a storage device 104, an XU4 main control chip 106, a first signal transmission interface 110, a power module 103 and a first power interface 107. The data transmission circuit 109 and the power module 103 are both connected to the storage device 104, the data transmission circuit 109 is also connected to the XU4 main control chip 106, the storage device 104 is connected to the XU4 main control chip 106, the XU4 main control chip 106 is connected to the first signal transmission interface 110, and the power module 103 is connected to the first power interface 107;

[0055] The eMMC chip test platform includes a second power interface 111, a second signal transmission interface 113, a voltage conversion module 112 and a test chip circuit 116, the second power interface 111 is connected to the voltage conversion module 112, the voltage conversion module 112 has a first output end and a second output end both connected to the test chip circuit 116, and the second signal transmission interface 113 is connected to the test chip circuit 116;

[0056] The data transmission circuit 109 is connected to the external PC device 108 , the first power interface 107 is connected to the second power interface 111 , and the first signal transmission interface 110 is connected to the second signal transmission interface 113 .

[0057] Specifically,

[0058] The XU4 platform 101 is a control platform composed of XU4 control cards, which is easy to operate and has low cost.

[0059] The storage device 104 is a device for storing test data for the XU4 main control chip 106 to call.

[0060] The power module 103 outputs a power supply with a voltage of 5V.

[0061] The first power interface 107 is connected to the second power interface 111 to input 5V power to the eMMC test platform 102 .

[0062] The first signal transmission interface 110 is connected to the second signal transmission interface 113 to input the retrieved test data to the eMMC test platform 102 and obtain feedback data output by the eMMC test platform 102 .

[0063] In the process of implementation

[0064] The power supply module 103 obtains instructions, outputs 5V power to the first power supply interface 107, and then outputs the 5V power to the voltage conversion module 112 through the second power supply interface 111. The voltage conversion module 112 has a first voltage conversion circuit and a second voltage conversion circuit. The first voltage conversion circuit converts the 5V power supply into a 3.3V power supply after obtaining the 5V power supply, and the second voltage conversion circuit converts the 5V power supply into a 1.8V power supply after obtaining the 5V power supply. The 3.3V power supply and the 1.8V power supply are respectively output to the first output terminal and the second output terminal of the voltage conversion module 112, and finally are simultaneously input into the test chip circuit 116 to power the eMMC chip in the test chip circuit 116.

[0065] The XU4 main control chip 106 obtains instructions and test data, stores the test data in a storage device, and then retrieves the burned data and the newly stored test data from the storage device for data transmission, and outputs the test data to the test chip circuit 116 through the first signal transmission interface 110 and the second signal transmission interface 113 to test the eMMC chip.

[0066] In one embodiment, the test data retrieved by the XU4 main control chip 106 from the storage device 104 carries data values ​​used for testing and writing to the test chip. The data values ​​are written to the test chip through the first signal transmission interface 110 and the second signal transmission interface 113, and then the data values ​​are read from the test chip. The read data values ​​are fed back to the XU4 main control chip 106 via the second signal transmission interface 113 and the first signal transmission interface 110 by the feedback data, thereby realizing the read and write test process of the test chip.

[0067] In one embodiment, the voltage conversion module 112 includes a first voltage output circuit and a second voltage output circuit, the first voltage output circuit is connected to the first output end of the voltage conversion module 112, and the second voltage output circuit is connected to the second output end; a 3.3VGPIO unit is provided in the first voltage output circuit, and a 1.8VGPIO unit is provided in the second voltage output circuit; the 3.3VGPIO unit and the 1.8VGPIO unit control the on and off of the 3.3V power supply and the 1.8V power supply output to the test chip circuit 116.

[0068] The way to control the on and off of the 3.3V power supply and 1.8V power supply for the 3.3V GPIO unit and the 1.8V GPIO unit is as follows:

[0069] Reference Figure 2 , is a circuit diagram of a first voltage output circuit and a second voltage output circuit included in the voltage conversion module 112 of the present application;

[0070] It is preset that a high-low level sequence (sequence for example: 1000111011101010···) is input to the first voltage conversion chip U7 and the second voltage conversion chip U8. When the first voltage conversion chip U7 outputs a high level according to "1" in the high-low level sequence, the 3.3V GPIO unit turns on the connection between the first output terminal and the test chip circuit 116 according to the high level, so that the 3.3V power supply is output to the test chip circuit 116. When the first voltage conversion chip U7 outputs a low level according to "0" in the high-low level sequence, the 3.3V GPIO unit disconnects the connection between the first output terminal and the test chip circuit 116 according to the low level, so that the test chip circuit 116 is powered off. Similarly, the control method of the GPIO unit of the second voltage output single channel is consistent, and this description will not be repeated.

[0071] In one embodiment, the XU4 platform 101 further includes a burning circuit 105 , and the burning circuit 105 is connected to the storage device 104 and the XU4 main control chip 106 .

[0072] In order to realize the autonomous testing process of the test system for the eMMC chip, a burning circuit 105 is set on the XU4 platform 101. First, the PC device 108 burns the application function of the XU4 main control chip 106 through the burning circuit 105, and then the PC device 108 outputs data to the storage device 104, and then the power is cut off and restarted, and then the test command and test data of the PC device 108 are received, and the burned data is retrieved from the storage device 104 for autonomous testing, so that the XU4 main control chip 106 retrieves the test data from the storage device 104 and autonomously executes the test process.

[0073] In another embodiment, the eMMC chip testing platform further includes an external power interface 120 , and the external power interface 120 is connected to the second power interface 111 .

[0074] In order to realize multiple power on and off tests and improve the problem of single power supply and single power on and off method of testing eMMC test system, the present invention proposes a power external interface 120, which is combined with the second power interface 111 to replace the above-mentioned power module 103.

[0075] In another embodiment, the eMMC test platform 102 also includes a 3.3V external interface 119 and a 1.8V external interface 118, the 3.3V external interface 119 and the first output end of the voltage conversion module 112 are connected to the line of the test chip circuit 116 in a common line, and the 1.8V external interface 118 and the second output end interface test chip circuit 116 of the voltage conversion module 112 are connected to the line of the test chip circuit 116 in a common line.

[0076] In order to realize multiple power on and off tests and improve the problem of single power supply and single power on and off method of testing eMMC test system, the present invention proposes 3.3V external interface 119 and 1.8V external interface 118, which can replace the above-mentioned power module 103. That is, it can be imagined that the output of 3.3V power supply and 1.8V power supply to the test chip circuit 116 can be controlled by an external control device to replace the function of GPIO in the voltage conversion module.

[0077] In one embodiment, the eMMC test platform 102 further includes an external signal interface 117 , and the external signal interface 117 is connected to a line between the second signal transmission interface 113 and the test chip circuit 116 .

[0078] Based on compatibility considerations, the signal transmission external interface of this design can also directly input control signals to perform chip control and data transmission to achieve testing purposes, avoiding single platform testing and possible incompatibility issues with other platforms. The present invention proposes a signal external interface 117, which is connected to other external test terminals through the signal external interface 117, and other test terminals output test data to the test chip circuit 116.

[0079] Reference Figure 3 , is a flow chart of a method for performing a power-on and power-off test on an eMMC test system, wherein the method for performing a power-on and power-off test on an eMMC test system includes:

[0080] S1, the data transmission circuit 109 receives the test start instruction and test data input by the PC device 108, and sends the test start instruction and test data to the XU4 main control chip 106, and the XU4 main control chip 106 stores the test data in the storage device 104;

[0081] S2, according to the test start instruction, the power module 103 outputs 5V power to the first power interface 107, the first power interface 107 outputs 5V power to the voltage conversion module 112 through the second power interface 111, the voltage conversion module 112 converts the 5V power to generate 3.3V power and 1.8V power, and outputs the 3.3V power and 1.8V power to the test chip circuit 116 through the first output terminal and the second output terminal respectively, so as to supply power to the eMMC chip in the test chip circuit 116;

[0082] S3, the XU4 main control chip 106 retrieves the test data from the storage device 104 and outputs it to the second signal transmission interface 113 through the first signal transmission interface 110, the second signal transmission interface 113 outputs the test data to the test chip circuit 116, the eMMC chip in the test chip circuit 116 performs a test related to the test data and then outputs feedback data, and the feedback data is fed back to the XU4 main control chip 106 through the second signal transmission interface 113 and the first signal transmission interface 110;

[0083] S4, the XU4 main control chip 106 uses a preset power-on and power-off rule to power on and off the test chip circuit 116;

[0084] S5, judging whether the feedback data fed back to the XU4 main control chip 106 and the test data conform to the preset read and write rules, and forming a test result;

[0085] S6, the XU4 main control chip 106 outputs the test result to the PC device 108 through the data transmission circuit 109 for display.

[0086] In one embodiment, in S4 of the power on and off test method, the preset power on and off rule is:

[0087] Mode 1: The power-off sequence is that the first signal transmission interface 110 outputs the test data transmission at a random time during which 3.3V is powered off and then 1.8V is powered off, and then 3.3V is powered on and then 1.8V is powered on;

[0088] Mode 2: The power-off sequence is that the first signal transmission interface 110 outputs the test data transmission at a random time during which 3.3V is powered off and then 1.8V is powered off, and then 1.8V is powered on and then 3.3V is powered on;

[0089] Mode 3: The power-off sequence is that the first signal transmission interface 110 outputs the test data transmission at a random time during which 1.8V is powered off and then 3.3V is powered off, and then 3.3V is powered on and then 1.8V is powered on;

[0090] Mode 4: The power-off sequence is that 1.8V is powered off and then 3.3V is powered off at a random time during the process of the first signal transmission interface 110 outputting the test data transmission, and then 1.8V is powered on and then 3.3V is powered on.

[0091] In one embodiment, in S5 of the power on / off test method, the preset read / write rule is:

[0092] XU4 writes the data values ​​carried in the test data into each unit of the eMMC chip in the positive or reverse order of the eMMC chip address;

[0093] Read the data value carried in the feedback data in the positive or reverse order of the eMMC chip address;

[0094] Determine whether the data values ​​read and written are consistent.

[0095] In one embodiment, the eMMC chip test system performs the steps before S1 in the power-on and power-off test method, and the steps include:

[0096] The PC device 108 burns the functional application of the XU4 main control chip 106;

[0097] The formed burning data is stored in the storage device 104, and then the power is turned off;

[0098] After restarting, the test command and test data of the PC device are received again, and the burning data is retrieved from the storage device for autonomous testing, and the power-on and power-off testing method is executed.

[0099] The present invention greatly shortens the test process and improves the manufacturing rate of good eMMC products by simultaneously executing the power-on and power-off test and the read-write test.

[0100] Although the embodiments of the present application have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. An eMMC chip testing system, characterized in that: The eMMC test system, which is composed of the XU4 platform and the eMMC chip test platform, performs power-on and power-off tests on the eMMC chip, wherein: The XU4 platform includes a data transmission circuit, a storage device, an XU4 main control chip, a first signal transmission interface, a power module and a first power interface, wherein the data transmission circuit and the power module are both connected to the storage device, the data transmission circuit is also connected to the XU4 main control chip, the storage device is connected to the XU4 main control chip, the XU4 main control chip is connected to the first signal transmission interface, and the power module is connected to the first power interface; The eMMC chip test platform includes a second power supply interface, a second signal transmission interface, a voltage conversion module and a test chip circuit, the second power supply interface is connected to the voltage conversion module, the voltage conversion module has a first output end and a second output end, both of which are connected to the test chip circuit, and the second signal transmission interface is connected to the test chip circuit; The data transmission circuit is connected to an external PC device, the first power interface is connected to the second power interface, and the first signal transmission interface is connected to the second signal transmission interface; The eMMC test system performs a power-on and power-off test method, which includes: S1, the data transmission circuit receives the test start instruction and test data input by the PC device, and sends the test start instruction and test data to the XU4 main control chip, and the XU4 main control chip stores the test data in the storage device; S2, according to the test start instruction, the power module outputs 5V power to the first power interface, the first power interface outputs 5V power to the voltage conversion module through the second power interface, the voltage conversion module converts the 5V power to generate 3.3V power and 1.8V power, and outputs the 3.3V power and 1.8V power to the test chip circuit through the first output terminal and the second output terminal respectively, so as to supply power to the eMMC chip in the test chip circuit; S3, the XU4 main control chip retrieves the test data from the storage device and outputs it to the second signal transmission interface through the first signal transmission interface, the second signal transmission interface outputs the test data to the test chip circuit, the eMMC chip in the test chip circuit performs a test related to the test data and then outputs feedback data, the feedback data is fed back to the XU4 main control chip through the second signal transmission interface and the first signal transmission interface; S4, the XU4 main control chip uses a preset power-on and power-off rule to power on and off the test chip circuit; S5, judging whether the feedback data fed back to the XU4 main control chip and the test data conform to the preset reading and writing rules, and forming a test result; S6, the XU4 main control chip outputs the test results to the PC device through the data transmission circuit; Among them, in S4 of the power on and off test method, the preset power on and off rule is: Mode 1: The power-off sequence is that during the process of the first signal transmission interface outputting the test data transmission, the 1.8V power-off is followed by the 3.3V power-off, and then the 1.8V power-on is followed by the 3.3V power-on; Mode 2: The power-off sequence is that during the process of the first signal transmission interface outputting the test data transmission, the 3.3V is powered off at a random time, followed by the 1.8V being powered off, and then the 3.3V being powered on after the 1.8V being powered on; Mode 3: The power-off sequence is that during the process of the first signal transmission interface outputting the test data transmission, the 1.8V power-off sequence is followed by the 3.3V power-off sequence, and then the 3.3V power-on sequence is followed by the 1.8V power-on sequence; Mode 4: The power-off sequence is that during the process of the first signal transmission interface outputting the test data transmission, the 1.8V power-off sequence is followed by the 3.3V power-off sequence, and then the 1.8V power-on sequence is followed by the 3.3V power-on sequence; Among them, in S5 of the power-on and power-off test method, the preset read-write rule is: The XU4 writes the data values ​​carried in the test data into each unit of the eMMC chip in the positive or reverse order of the eMMC chip address; Read the data value carried by the feedback data in the positive or reverse order of the eMMC chip address; Determine whether the data values ​​read and written are consistent.

2. The eMMC chip testing system according to claim 1, characterized in that, The XU4 platform also includes a burning circuit, and the burning circuit is connected to the XU4 main control chip.

3. The eMMC chip testing system according to claim 1, characterized in that, The eMMC chip testing platform also includes an external power interface, which is connected to the second power interface.

4. The eMMC chip testing system according to claim 1, characterized in that: The eMMC test platform also includes a 3.3V external interface and a 1.8V external interface. The 3.3V external interface is connected to the line of the test chip circuit connected to the first output end of the voltage conversion module in a common line, and the 1.8V external interface is connected to the line of the test chip circuit connected to the second output end interface of the voltage conversion module in a common line.

5. The eMMC chip testing system according to claim 1, characterized in that: The eMMC test platform also includes a signal external interface, and the signal external interface is connected to the line between the second signal transmission interface and the test chip circuit.

6. The eMMC chip testing system according to claim 1, characterized in that: The voltage conversion module comprises a first voltage output circuit and a second voltage output circuit, wherein the first voltage output circuit is connected to the first output terminal of the voltage conversion module, and the second voltage output circuit is connected to the second output terminal; The first voltage output circuit is provided with a 3.3V GPIO unit, and the second voltage output circuit is provided with a 1.8V GPIO unit.

7. The eMMC chip testing system according to claim 1, characterized in that: The eMMC chip testing system according to claim 2 performs the steps before S1 in the power-on and power-off testing method, the steps comprising: The PC device burns the functional application of the XU4 main control chip; The formed burning data is stored in the storage device, and then the power is turned off; After restarting, the test command and test data of the PC device are received again, and the burning data is retrieved from the storage device for autonomous testing, and the power-on and power-off testing method is executed.

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