Method, apparatus and system for level shifting latch with embedded logic

Abstract

In certain aspects of the present disclosure, an apparatus (100) includes a latch element (110) having a data input (118b), a first feedback input (118a), a second feedback input (118c), and an output (140). A pull-up input block (122) is coupled to the data input and has at least a first pull-up input, and a pull-down input block (124) is also coupled to the data input and has at least a first pull-down input. A feedback pull-down block (132) that implements a logic function complementary to the pull-up input block (122) is coupled to a feedback pull-down control device (116) and is responsive to the first pull-up input, and a feedback pull-up block (134) that implements a logic function complementary to the pull-down input block (124) is coupled to a feedback pull-up control device (114) and is responsive to the first pull-down input. The pull-up input block (122) and the pull-down input block (124) are guaranteed not to be enabled at the same time.

Description

[0001] Priority claim

[0002] This patent application claims priority to application No. 15 / 987,936, filed on May 24, 2018, entitled “METHOD, APPARATUS, AND SYSTEM FOR LEVEL-SHIFT LATCH WITH EMBEDDED LOGIC,” which is assigned to the assignee of this case and is expressly incorporated herein by reference. Technical Field

[0003] Various aspects of the present disclosure relate generally to latch circuits and, more particularly, to a level-shifting set-reset (SR) latch with embedded logic. Background Art

[0004] When designing integrated circuits, such as processors, achieving timing closure is a challenging problem and involves many trade-offs between circuit power, performance, area, and other considerations. As part of such integrated circuits, latch circuits may be used to capture and retain data. Ensuring that the clock signal that controls the latch circuit and the data signal captured by the latch have proper timing relative to each other so that the data is correctly captured and retained can be particularly challenging where some of those signals are naturally offset relative to each other due to the design of the surrounding circuitry that generates those signals.

[0005] Further, such an integrated circuit may be designed with multiple voltage domains, and voltage level conversion circuits may be used to enable signals to move between those voltage domains. In the case where the voltages of some of the signals fed into the latch circuits are different from the voltages of other signals fed into the latch circuits, the complexity of the timing issues increases, and may cause the circuit designer to make other adverse trade-offs, such as reducing the design frequency and increasing the design area to add additional circuitry to control the relative timing of the signals fed into the latch circuits.

[0006] Therefore, a latch circuit with fewer complex timing parameters is desired while maintaining sufficient performance and optimizing the power and area of ​​the latch circuit. Summary of the invention

[0007] A simplified summary of one or more aspects is given below to provide a basic understanding of these aspects. This summary is not an extensive overview of all contemplated aspects, and is neither intended to identify key elements or important elements of all aspects, nor to describe the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the detailed embodiments presented later.

[0008] In one aspect, a device includes a latch element having a data input, a first feedback input, a second feedback input, and an output. The device also includes a pull-up input block and a pull-down input block, the pull-up input block is coupled to the data input of the latch element and has at least a first pull-up input; the pull-down input block is coupled to the data input of the latch element and has at least a first pull-down input. The device also includes a feedback pull-down block and a feedback pull-up block, the feedback pull-down block is coupled to a feedback pull-down control device, the feedback pull-down block is responsive to the first pull-up input and implements a logical function opposite to that of the pull-up input block; the feedback pull-up block is coupled to a feedback pull-up control device, the feedback pull-up block is responsive to the first pull-down input and implements a logical function opposite to that of the pull-down input block. The pull-up input block and the pull-down input block are configured not to be enabled at the same time.

[0009] In another aspect, a device includes a device for latching, the device for latching having a data input, a first feedback input, a second feedback input, and an output. The device also includes a device for pull-up and a device for pull-down, the device for pull-up being coupled to the data input of the device for latching and having at least a first pull-up input; the device for pull-down being coupled to the data input of the device for latching and having at least a first pull-down input. The device also includes a device for feedback pull-down and a device for feedback pull-up, the device for feedback pull-down being coupled to a device for controlling feedback pull-down, the device for feedback pull-down being responsive to the first pull-up input and implementing a logic function opposite to that of the device for pull-up; the device for feedback pull-up being coupled to a device for controlling feedback pull-up, the device for feedback pull-up being responsive to the first pull-down input and implementing a logic function opposite to that of the device for pull-down. The device for pull-up and the device for pull-down are configured not to be enabled at the same time.

[0010] In another aspect, a method includes: enabling a pull-up input block or a pull-down input block of a data input fed into a latch element, the pull-up input block and the pull-down input block being configured not to be enabled simultaneously, the pull-up input block having an associated feedback pull-down block, the feedback pull-down block implementing a logic function complementary to the pull-up input block, the pull-down input block having an associated feedback pull-up block, the feedback pull-up block implementing a logic function complementary to the pull-down input block. The method also includes: disabling a feedback block associated with the enabled input block. The method also includes: disabling a previously enabled input block and enabling the associated feedback block.

[0011] One advantage of one or more disclosed aspects is that the disclosed aspects enable certain logic functions to be embedded in a level-shifting set-reset latch, thereby saving silicon area and improving latch performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1A diagram showing a generalized latch circuit in accordance with certain aspects of the present disclosure.

[0013] Figure 2 A diagram illustrating a particular set-reset (SR) latch circuit in accordance with certain aspects of the present disclosure.

[0014] Figure 3 A diagram illustrating a clock edge synchronizer in accordance with certain aspects of the present disclosure.

[0015] Figure 4 A block diagram illustrating a method of operating a generalized latch circuit in accordance with certain aspects of the present disclosure is shown.

[0016] Figure 5 A system-level diagram of a computing device including a latch circuit according to certain aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0017] Various aspects of the inventive teachings herein are disclosed in the following description and in the related drawings for specific aspects. Alternative aspects may be envisioned without departing from the scope of the inventive concepts herein. Additionally, well-known elements of the environment will not be described in detail, or may be omitted, so as not to obscure the relevant details of the inventive teachings herein.

[0018] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects. Likewise, the term "aspects of the invention" does not require that all aspects of the invention include the discussed feature, advantage, or mode of operation.

[0019] The terms used herein are only for the purpose of describing specific aspects and are not intended to limit the various aspects of the present invention. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are also intended to include plural forms. It should also be understood that when used herein, the terms "comprises", "comprising", "includes" and / or "including" specify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups thereof.

[0020] Further, many aspects are described according to sequences of actions to be performed by, for example, elements of a computing device. It should be appreciated that the various actions described herein may be performed by specific circuits (e.g., application specific integrated circuits (ASICs)), program instructions executed by one or more processors, or a combination of the two. Additionally, the sequences of actions described herein may be considered to be fully embodied in any form of computer-readable storage medium having a corresponding set of computer instructions stored therein, which, when executed, causes the associated processor to perform the functions described herein. Therefore, various aspects of the present invention may be embodied in several different forms, all of which are considered to be within the scope of the claimed subject matter. In addition, for each of the various aspects described herein, the corresponding form of any such aspect may be described herein as, for example, "logically configured to" to perform the described actions.

[0021] In this regard, in one aspect, Figure 1 A diagram of a generalized latch circuit 100 according to certain aspects of the present disclosure as described herein is shown. The latch circuit 100 includes a latch element 110, a pull-up input block 122, a pull-down input block 124, a feedback pull-down block 132, a feedback pull-up block 134, and a latch output 140. The latch element 110 includes an inverter 112 coupled to a pull-up feedback control device 114 and a pull-down feedback control device 116. The input of the inverter 112 is coupled to the output of the pull-up feedback control device 114, the output of the pull-down feedback control device 116, the output of the pull-up input block 122, and the output of the pull-down input block 124. The output of the inverter 112 is coupled to the gate input of the pull-up feedback control device 114 and the gate input of the pull-down feedback control device 116 and the latch output 140. The pull-up input block 122 and the pull-down input block 124 are coupled to the data input 118b of the latch element 110. The feedback pull-up block 134 is coupled to the first feedback input 118 a of the latch element 110 , and the feedback pull-down block 132 is coupled to the second feedback input 118 c of the latch element 110 .

[0022] The pull-up input block 122 may receive a first set of input signals, and the pull-down input block 124 may receive a second set of input signals. In some aspects, some input signals may be common between the first set of input signals and the second set of input signals, while in other aspects, the first set of input signals and the second set of input signals are disjoint. The first set of input signals is also provided to the pull-down feedback block 132, and the second set of input signals is provided to the pull-up feedback block 134.

[0023] As further described herein, the pull-up input block 122 and the feedback pull-down block 132 implement complementary logic functions with respect to each other, and the pull-down input block 124 and the feedback pull-up input block 134 implement complementary logic functions with respect to each other. This ensures that a complete circuit path from power to ground is not created through the pull-up input block 122 and the feedback pull-down block 132, and through the pull-down input block 124 and the feedback pull-up block 134, respectively.

[0024] To further ensure that a direct current path from power to ground is not created, the corresponding logic functions implemented by each input block (function A implemented by the pull-up input block 122, function B implemented by the pull-down input block 124) must be designed to ensure that the pull-up input block 122 and the pull-down input block 124 are not enabled at the same time. Those skilled in the art will recognize that this can be accomplished in different ways, such as referring to Figure 2 and Figure 3 As discussed in the exemplary aspects. For example, in one aspect, the inputs of each block can be selected so that at least one of the inputs is common between two logic functions, and one PMOS transistor coupled in series with the power supply and one NMOS transistor coupled in series with the ground are controlled so that because the PMOS transistor and the NMOS transistor are not turned on at the same time (e.g., the inputs are at a logic low value or a logic high value) during normal circuit operation, it is logically guaranteed that a complete circuit path from power to ground will never occur. In another exemplary aspect, the timing of the inputs of each input block can be controlled so that a complete circuit path from power to ground is not created due to the relative timing of the inputs.

[0025] Those skilled in the art will appreciate that only the signal input to the pull-down input block 124 can be level-shifted from the lower voltage domain to the higher voltage domain (where the inverter 112 is in the higher voltage domain) without adding additional circuit elements to support the level shifting function. This can be achieved because the pull-up feedback control device 114 is controlled by the inverter 112, and thus even if the feedback pull-up block 134 is only slightly turned off due to its input signal from the lower voltage domain, the pull-up feedback control device 114 will mitigate any driving conflict between the pull-down input block 124 and the feedback pull-up block 134. Therefore, if the input of the pull-down input block 124 is appropriately selected, the generalized latch circuit 100 can also be used as a level shifter between voltage domains.

[0026] In one aspect, Figure 2 A set-reset (SR) latch circuit 200 is shown, which is based on Figure 1The generalized latch circuit 100 of FIG. 1 is designed and includes a latch element 110, a pull-up input block 222, a pull-down input block 224, a feedback pull-down block 232, a feedback pull-up block 234, and a latch output 140. The SR latch 200 also includes a reset_bar input 252, a select input 254, and a set input 256. As further described with respect to Figure 2 As depicted, select input 254 is coupled to pull-up input block 222 and pull-down input block 224 such that a complete circuit path from power to ground is guaranteed not to occur.

[0027] Pull-up input block 222 and feedback pull-down block 232 implement logically complementary functions with respect to reset_bar input 252 and select input 254. Pull-up input block 222 is enabled when reset_bar input 252 and select input 254 are logic low (and therefore both PMOS transistors 262 and 264 are turned on), while feedback pull-down block 232 is enabled when reset_bar input 252 or select input 254 is logic high (and therefore one or both of NMOS transistors 272 and 274 are turned on). In a similar manner, pull-down input block 224 and feedback pull-up block 234 implement logically complementary functions with respect to set input 256 and select input 254. When both the set input 256 and the select input 254 are logic high (and therefore both NMOS transistors 266 and 268 are turned on), the pull-down input block 224 is enabled, and when either the set input 256 or the select input 254 is logic low (and therefore one or both of the PMOS transistors 276 and 278 are turned on), the feedback pull-up block 234 is enabled. As discussed above, because the select input 254 is used directly as an input to the series transistors in both the pull-up input block 222 and the pull-down input block 224, it is logically guaranteed that the pull-up input block 222 and the pull-down input block 224 will never be enabled at the same time, and therefore it is guaranteed that a complete circuit path from power to ground will not occur under normal operating conditions.

[0028] On the other hand, Figure 3 A clock edge synchronizer circuit 300 is shown, which is based on Figure 1The generalized latch circuit 100 of the present invention is designed and includes a latch element 110, a pull-up input block 322 and a pull-down input block 324, a feedback pull-down block 332, a feedback pull-up block 334, and a latch output 140. The clock edge synchronizer 300 also includes a ready_falling_bar input 352, a phi_2 input 354, a phi_1 input 356, and a ready_rising input 358. The phi_1 input 356 and the phi_2 input 354 are non-overlapping clock inputs, which means that the relative timing of the high periods of the phi_1 input 356 and the phi_2 input 354 has been guaranteed (via static timing or other methods known to those skilled in the art) to be non-overlapping. In one aspect, the phi_2 input 354, the phi_1 input 356, and the ready_rising input 358 can originate from the first clock domain 302, while the ready_falling_bar input 352 can originate from the second clock domain 304.

[0029] The pull-up input block 322 and the pull-down feedback block 332 implement logically complementary functions with respect to the ready_falling_bar input 352 and the phi_2 input 354. When both the ready_falling_bar input 352 and the phi_2 input 354 are logic low (and therefore both the PMOS transistors 362 and 364 are turned on), the pull-up input block 322 is enabled, and when either the ready_falling_bar input 352 or the phi_2 input 354 is logic high (and therefore one or both of the NMOS transistors 372 and 374 are turned on), the feedback pull-down block 332 is enabled. In a similar manner, the pull-down input block 324 and the feedback pull-up block 334 implement logically complementary functions with respect to the ready_rise input 358 and the phi_1 input 356. When both the ready_up input 358 and the phi_1 input 356 are logic high (and therefore both NMOS transistors 368 and 366 are turned on), the pull-down input block 324 is enabled, and when either the ready_up input 358 or the phi_1 input 356 is logic low (and therefore one or both of the PMOS transistors 376 and 378 are turned on), the feedback pull-up block 334 is enabled. Because the phi_1 input 356 and the phi_2 input 354 are non-overlapping clock inputs, it is guaranteed that the pull-up input block 322 and the pull-down input block 324 are never enabled at the same time, and therefore it is guaranteed that a complete circuit path from power to ground does not occur under normal operating conditions.

[0030] Those skilled in the art will recognize that other circuits and logic functions may be implemented without departing from the scope of the teachings of the present disclosure. For example, the inputs of the various pull-up input blocks and the inputs of the various pull-down input blocks may originate from the same or different clock domains. Likewise, they may originate from the same or different voltage domains (as long as they meet the requirements of Figure 1level shifting parameters discussed in the context of ). Figure 2 and Figure 3 The described circuits are exemplary aspects and should not be construed as limiting the teachings of the present disclosure.

[0031] On the other hand, Figure 4 A block diagram of a method 400 for operating a generalized latch circuit is shown. The method 400 may be applied to Figure 2 SR latch 200, Figure 3 The clock edge synchronizer circuit 300, or according to Figure 1 The features of the generalized latch circuit 100 are no different from any other circuit design.

[0032] The method 400 begins at block 410, where one of the pull-up input block or the pull-down input block is enabled, wherein the pull-up input block and the pull-down input block are configured not to be enabled at the same time. As described with reference to the previous figures, the pull-up input block and the pull-down input block can be configured not to be enabled at the same time by virtue of their logic design, by virtue of the timing relationship of the respective input signals of each of the blocks, or by other methods known to those skilled in the art. For example and with reference to Figure 1 The generalized latch circuit 100 can enable the pull-up input block 122 while disabling the pull-down input block 124.

[0033] The method 400 continues at block 420 where the feedback block of the latch element associated with the enabled input block is disabled. Again, for example and with reference to Figure 1 The generalized latch circuit 100 of FIG. 1 disables the feedback pull-down block 132 associated with the input pull-up block 122 .

[0034] The method continues at block 430 where the previously enabled input block is now disabled and the associated feedback block is enabled. Again, for example and with reference to Figure 1 The generalized latch circuit 100 disables the pull-up input block 122 while enabling the feedback pull-down block 132 .

[0035] Now, combined with Figure 5 Example devices are discussed in which various aspects of the disclosure may be utilized. Figure 5 Shows the combination Figure 1 FIG. 5 is a diagram of a computing device 500 that may include one or more aspects of the generalized latch circuit 100. For example, the computing device 500 may include Figure 2 The set-reset latch circuit of Figure 3The clock edge synchronizer circuit of the generalized latch circuit 100 may be a clock edge synchronizer circuit, or any other circuit that satisfies the parameters of the generalized latch circuit 100. The memory 504 may also store non-transitory computer readable instructions that, when executed by the processor 102, may perform Figure 4 Method 400.

[0036] Figure 5 Also shown in dashed lines are optional blocks such as a coder / decoder (CODEC) 534 (e.g., an audio and / or voice CODEC) coupled to the processor 502, and a speaker 536 and a microphone 538 may be coupled to the CODEC 534, and a wireless antenna 542 coupled to a wireless controller 540, which is coupled to the processor 502. Further, the system 502 also shows a display controller 526 coupled to the processor 502 and a display 528, and a wired network controller 570 coupled to the processor 502 and a network 572. In certain aspects, where one or more of these optional blocks are present, the processor 502, the display controller 526, the memory 532, and the wireless controller 540 may be included in a system-in-package or system-on-chip device 522.

[0037] Thus, in one particular aspect, input device 530 and power supply 544 are coupled to system-on-chip device 522. Also, in one particular aspect, as Figure 5 As shown, in the presence of one or more optional blocks, the display 528, input device 530, speaker 536, microphone 538, wireless antenna 542, and power supply 544 are external to the system-on-chip device 522. However, each of the display 528, input device 530, speaker 536, microphone 538, wireless antenna 542, and power supply 544 may be coupled to a component of the system-on-chip device 522, such as an interface or controller.

[0038] It should be noted that although Figure 5 A computing device is generally depicted, but processor 502 and memory 504 may also be integrated into a mobile phone, communication device, computer, server, laptop, tablet computer, personal digital assistant, music player, video player, entertainment unit, set-top box, or other similar device.

[0039] Those skilled in the art will appreciate that any of a variety of different technologies may be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the specification above may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0040] Further, it will be appreciated by those skilled in the art that the various illustrative logic blocks, modules, circuits and algorithmic steps described in conjunction with the various aspects disclosed herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits and steps have been generally described above according to their functions. Whether this functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system. The technician can implement the described functions in various ways for each specific application, but this implementation decision should not be interpreted as causing departure from the scope of the present invention.

[0041] The methods, sequences and / or algorithms described in conjunction with the various aspects disclosed herein may be directly embodied in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and can write information to the storage medium. In an alternative, the storage medium may be integrated with the processor.

[0042] Thus, one aspect of the present invention may include a computer readable medium embodying the invention as described with reference to Figure 4 The described method of operating a generalized latch circuit. Therefore, the present invention is not limited to the illustrated examples, and any means for performing the functions described herein are included in various aspects of the present invention.

[0043] Although the foregoing disclosure shows various illustrative aspects of the present invention, it should be noted that various changes and modifications may be made herein without departing from the scope of the present invention as defined by the appended claims. The functions, steps and / or actions of the method claims according to the various aspects of the present invention described herein do not have to be performed in any particular order. Further, although the elements of the present invention may be described or claimed in the singular, plural forms may be contemplated unless it is explicitly stated that they are limited to the singular.

Claims

1. A device comprising: a latch element having a data input, a first feedback input, a second feedback input, and an output; a pull-up input block coupled to the data input of the latch element and having at least a first pull-up input; a pull-down input block coupled to the data input of the latch element and having at least a first pull-down input; a feedback pull-down block coupled to a feedback pull-down control device, the feedback pull-down block being responsive to the first pull-up input and implementing an opposite logic function of the pull-up input block; as well as a feedback pull-up block coupled to a feedback pull-up control device, the feedback pull-up block being responsive to the first pull-down input and implementing a logic function opposite to that of the pull-down input block; The pull-up input block and the pull-down input block are configured not to be enabled at the same time.

2. The apparatus of claim 1, wherein the first pull-up input and the first pull-down input are logically complementary. 3 . The apparatus of claim 1 , wherein the relative timing of the first pull-up input and the first pull-down input is configured to ensure that the pull-up input block and the pull-down input block are not enabled at the same time. 4 . The apparatus of claim 1 , wherein the first pull-up input originates from a first voltage domain and the first pull-down input originates from a second voltage domain. 5 . The apparatus of claim 4 , wherein the feedback pull-up block is configured to be decoupled from the data input in response to a control signal from the first voltage domain.

6. The device according to claim 1, wherein The pull-up input block also has a second pull-up input, and the feedback pull-down block is also responsive to the second pull-up input; and The pull-down input block also has a second pull-down input, and the feedback pull-up block is also responsive to the second pull-down input.

7. The apparatus of claim 6, wherein the apparatus comprises a set-reset latch, and wherein The first pull-up input of the pull-up input block is a non-reset input, and the first pull-down input of the pull-down input block is a set input; The second pull-up input and the second pull-down input are coupled together as a select input.

8. The apparatus of claim 6, wherein the apparatus comprises a clock edge synchronizer, and wherein The first pull-up input of the pull-up input block is a not_ready_to_fall input; The second pull-up input of the pull-up input block is a clock_2 input; The first pull-down input of the pull-down input block is a ready_up input; The second pull-down input of the pull-down input block is a clock_1 input.

9. The apparatus of claim 1, integrated into a computing device.

10. The apparatus of claim 9, wherein the computing device is further integrated into a device selected from the group consisting of a mobile phone, a communication device, a computer, a server, a laptop computer, a tablet computer, a personal digital assistant, a music player, a video player, an entertainment unit, and a set-top box.

11. An apparatus comprising: A device for latching, having a data input, a first feedback input, a second feedback input, and an output; means for pulling up coupled to the data input of the means for latching and having at least a first pull-up input; a means for pulling down coupled to the data input of the means for latching and having at least a first pull-down input; a means for feedback pull-down coupled to the means for controlling feedback pull-down, the means for feedback pull-down being responsive to the first pull-up input and performing an opposite logic function of the means for pull-up; as well as a means for feedback pull-up coupled to the means for controlling feedback pull-up, the means for feedback pull-up being responsive to the first pull-down input and performing an opposite logic function of the means for pull-down; The device for pulling up and the device for pulling down are configured not to be enabled at the same time.

12. A method comprising: enabling a pull-up input block or a pull-down input block of a data input fed into a latch element, the pull-up input block and the pull-down input block being configured not to be enabled simultaneously, the pull-up input block having an associated feedback pull-down block, the associated feedback pull-down block implementing a logic function complementary to the pull-up input block, the pull-down input block having an associated feedback pull-up block, the associated feedback pull-up block implementing a logic function complementary to the pull-down input block; disabling a feedback block associated with the enabled input block; and The previously enabled input block is disabled and the associated feedback block is enabled.

13. The method of claim 12, wherein the pull-up input block and the pull-down input block are logically complementary.

14. The method of claim 12, wherein the relative timing of at least one input to the pull-up input block and at least one input to the pull-down input block is configured to ensure that the pull-up input block and the pull-down input block are not enabled simultaneously.

15. The method of claim 12, wherein at least one input to the pull-up input block originates from a first voltage domain and at least one input to the pull-down input block originates from a second voltage domain, wherein the pull-down input block performs a level conversion function to convert the at least one input to the pull-down input block originating from the second voltage domain into an associated signal in the first voltage domain. 16 . The method of claim 15 , wherein the feedback pull-up block is decoupled from the data input in response to a control signal from the first voltage domain.

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